@yowasp/yosys 0.37.647 → 0.38.21-dev.654

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (5) hide show
  1. package/gen/bundle.js +9 -10
  2. package/gen/resources-yosys.js +3 -3
  3. package/gen/share/quicklogic/qlf_k6n10f/bram_types_sim.v +1 -1
  4. package/gen/yosys.core.wasm +0 -0
  5. package/package.json +5 -5
package/gen/bundle.js CHANGED
@@ -460,28 +460,28 @@ function fetchResources({ modules, filesystem }) {
460
460
  });
461
461
  }
462
462
  var Application = class {
463
- constructor(resourceFileURL2, instantiate2, argv0) {
464
- this.resourceFileURL = resourceFileURL2;
465
- this.resources = null;
463
+ constructor(resources, instantiate2, argv0) {
464
+ this.resources = resources;
465
+ this.resourceData = null;
466
466
  this.instantiate = instantiate2;
467
467
  this.argv0 = argv0;
468
468
  }
469
469
  // The `printLine` option is deprecated and not documented but still accepted for compatibility.
470
470
  async run(args = null, files = {}, { stdout, stderr, decodeASCII = true, printLine } = {}) {
471
- if (this.resources === null)
472
- this.resources = await import(this.resourceFileURL).then(fetchResources);
471
+ if (this.resourceData === null)
472
+ this.resourceData = await this.resources().then(fetchResources);
473
473
  if (args === null)
474
474
  return;
475
475
  const environment = new Environment();
476
476
  environment.args = [this.argv0].concat(args);
477
477
  environment.root = directoryFromTree(files);
478
- for (const [dirName, dirContents] of Object.entries(this.resources.filesystem))
478
+ for (const [dirName, dirContents] of Object.entries(this.resourceData.filesystem))
479
479
  environment.root.files[dirName] = directoryFromTree(dirContents);
480
480
  const lineBufferedConsole = lineBuffered(printLine ?? console.log);
481
481
  environment.stdout = stdout === void 0 ? lineBufferedConsole : stdout;
482
482
  environment.stderr = stderr === void 0 ? lineBufferedConsole : stderr;
483
483
  const wasmCommand = await this.instantiate(
484
- (filename) => this.resources.modules[filename],
484
+ (filename) => this.resourceData.modules[filename],
485
485
  { runtime: environment.exports }
486
486
  );
487
487
  let error = null;
@@ -493,7 +493,7 @@ var Application = class {
493
493
  if (e instanceof Exit && e.code !== 0)
494
494
  error = e;
495
495
  }
496
- for (const dirName of Object.keys(this.resources.filesystem))
496
+ for (const dirName of Object.keys(this.resourceData.filesystem))
497
497
  delete environment.root.files[dirName];
498
498
  files = directoryIntoTree(environment.root, { decodeASCII });
499
499
  if (error !== null) {
@@ -4640,8 +4640,7 @@ async function instantiate(getCoreModule, imports, instantiateCore = WebAssembly
4640
4640
  }
4641
4641
 
4642
4642
  // lib/api.js
4643
- var resourceFileURL = new URL("./resources-yosys.js", import.meta.url);
4644
- var yosys = new Application(resourceFileURL, instantiate, "yowasp-yosys");
4643
+ var yosys = new Application(() => import("./resources-yosys.js"), instantiate, "yowasp-yosys");
4645
4644
  var runYosys = yosys.run.bind(yosys);
4646
4645
  var commands = { "yosys": runYosys };
4647
4646
  export {
package/gen/resources-yosys.js CHANGED
@@ -91,7 +91,7 @@ export const filesystem = {
91
91
  "gowin": {
92
92
  "arith_map.v": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n * Copyright (C) 2018 gatecat <gatecat@ds0.me>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n(* techmap_celltype = \"$alu\" *)\nmodule _80_gw1n_alu(A, B, CI, BI, X, Y, CO);\n parameter A_SIGNED = 0;\n parameter B_SIGNED = 0;\n parameter A_WIDTH = 1;\n parameter B_WIDTH = 1;\n parameter Y_WIDTH = 1;\n\n (* force_downto *)\n input [A_WIDTH-1:0] A;\n (* force_downto *)\n input [B_WIDTH-1:0] B;\n (* force_downto *)\n output [Y_WIDTH-1:0] X, Y;\n\n input \t\tCI, BI;\n (* force_downto *)\n output [Y_WIDTH-1:0] CO;\n\n wire \t\t_TECHMAP_FAIL_ = Y_WIDTH <= 2;\n\n (* force_downto *)\n wire [Y_WIDTH-1:0] \tA_buf, B_buf;\n \\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n \\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));\n\n (* force_downto *)\n wire [Y_WIDTH-1:0] \tAA = A_buf;\n (* force_downto *)\n wire [Y_WIDTH-1:0] \tBB = B_buf;\n (* force_downto *)\n wire [Y_WIDTH-1:0] \tC = {CO, CI};\n\n genvar \t\ti;\n generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice\n ALU #(.ALU_MODE(2)) // ADDSUB I3 ? add : sub\n alu(.I0(AA[i]),\n\t .I1(BB[i]),\n\t .I3(~BI),\n\t .CIN(C[i]),\n\t .COUT(CO[i]),\n\t .SUM(Y[i])\n\t );\n end endgenerate\n assign X = AA ^ BB ^ {Y_WIDTH{BI}};\nendmodule\n\n",
93
93
  "brams.txt": "ram block $__GOWIN_SP_ {\n\tabits 14;\n\twidths 1 2 4 9 18 36 per_port;\n\tbyte 9;\n\tcost 128;\n\tinit no_undef;\n\tport srsw \"A\" {\n\t\tclock posedge;\n\t\tclken;\n\t\twrbe_separate;\n\t\toption \"RESET_MODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\toption \"RESET_MODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t\tportoption \"WRITE_MODE\" 0 {\n\t\t\trdwr no_change;\n\t\t}\n\t\tportoption \"WRITE_MODE\" 1 {\n\t\t\trdwr new;\n\t\t}\n\t\tportoption \"WRITE_MODE\" 2 {\n\t\t\trdwr old;\n\t\t}\n\t}\n}\n\nram block $__GOWIN_DP_ {\n\tabits 14;\n\twidths 1 2 4 9 18 per_port;\n\tbyte 9;\n\tcost 128;\n\tinit no_undef;\n\tport srsw \"A\" \"B\" {\n\t\tclock posedge;\n\t\tclken;\n\t\twrbe_separate;\n\t\toption \"RESET_MODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\toption \"RESET_MODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t\tportoption \"WRITE_MODE\" 0 {\n\t\t\trdwr no_change;\n\t\t}\n\t\tportoption \"WRITE_MODE\" 1 {\n\t\t\trdwr new;\n\t\t}\n\t\tportoption \"WRITE_MODE\" 2 {\n\t\t\trdwr old;\n\t\t}\n\t}\n}\n\nram block $__GOWIN_SDP_ {\n\tabits 14;\n\twidths 1 2 4 9 18 36 per_port;\n\tbyte 9;\n\tcost 128;\n\tinit no_undef;\n\tport sr \"R\" {\n\t\tclock posedge;\n\t\tclken;\n\t\toption \"RESET_MODE\" \"SYNC\" {\n\t\t\trdsrst zero ungated;\n\t\t}\n\t\toption \"RESET_MODE\" \"ASYNC\" {\n\t\t\trdarst zero;\n\t\t}\n\t\trdinit zero;\n\t}\n\tport sw \"W\" {\n\t\tclock posedge;\n\t\tclken;\n\t\twrbe_separate;\n\t}\n}\n",
94
- "brams_map.v": "`define DEF_FUNCS \\\n\tfunction [255:0] init_slice_x8; \\\n\t\tinput integer idx; \\\n\t\tinteger i; \\\n\t\tfor (i = 0; i < 32; i = i + 1) begin \\\n\t\t\tinit_slice_x8[i*8+:8] = INIT[(idx * 32 + i) * 9+:8]; \\\n\t\tend \\\n\tendfunction \\\n\tfunction [287:0] init_slice_x9; \\\n\t\tinput integer idx; \\\n\t\tinit_slice_x9 = INIT[idx * 288+:288]; \\\n\tendfunction \\\n\n`define x8_width(width) (width / 9 * 8 + width % 9)\n`define x8_rd_data(data) {1'bx, data[31:24], 1'bx, data[23:16], 1'bx, data[15:8], 1'bx, data[7:0]}\n`define x8_wr_data(data) {data[34:27], data[25:18], data[16:9], data[7:0]}\n`define wre(width, wr_en, wr_be) (width < 18 ? wr_en | wr_be[0] : wr_en)\n`define addrbe(width, addr, wr_be) (width < 18 ? addr : {addr[13:4], wr_be})\n\n\n`define INIT(func) \\\n\t.INIT_RAM_00(func('h00)), \\\n\t.INIT_RAM_01(func('h01)), \\\n\t.INIT_RAM_02(func('h02)), \\\n\t.INIT_RAM_03(func('h03)), \\\n\t.INIT_RAM_04(func('h04)), \\\n\t.INIT_RAM_05(func('h05)), \\\n\t.INIT_RAM_06(func('h06)), \\\n\t.INIT_RAM_07(func('h07)), \\\n\t.INIT_RAM_08(func('h08)), \\\n\t.INIT_RAM_09(func('h09)), \\\n\t.INIT_RAM_0A(func('h0a)), \\\n\t.INIT_RAM_0B(func('h0b)), \\\n\t.INIT_RAM_0C(func('h0c)), \\\n\t.INIT_RAM_0D(func('h0d)), \\\n\t.INIT_RAM_0E(func('h0e)), \\\n\t.INIT_RAM_0F(func('h0f)), \\\n\t.INIT_RAM_10(func('h10)), \\\n\t.INIT_RAM_11(func('h11)), \\\n\t.INIT_RAM_12(func('h12)), \\\n\t.INIT_RAM_13(func('h13)), \\\n\t.INIT_RAM_14(func('h14)), \\\n\t.INIT_RAM_15(func('h15)), \\\n\t.INIT_RAM_16(func('h16)), \\\n\t.INIT_RAM_17(func('h17)), \\\n\t.INIT_RAM_18(func('h18)), \\\n\t.INIT_RAM_19(func('h19)), \\\n\t.INIT_RAM_1A(func('h1a)), \\\n\t.INIT_RAM_1B(func('h1b)), \\\n\t.INIT_RAM_1C(func('h1c)), \\\n\t.INIT_RAM_1D(func('h1d)), \\\n\t.INIT_RAM_1E(func('h1e)), \\\n\t.INIT_RAM_1F(func('h1f)), \\\n\t.INIT_RAM_20(func('h20)), \\\n\t.INIT_RAM_21(func('h21)), \\\n\t.INIT_RAM_22(func('h22)), \\\n\t.INIT_RAM_23(func('h23)), \\\n\t.INIT_RAM_24(func('h24)), \\\n\t.INIT_RAM_25(func('h25)), \\\n\t.INIT_RAM_26(func('h26)), \\\n\t.INIT_RAM_27(func('h27)), \\\n\t.INIT_RAM_28(func('h28)), \\\n\t.INIT_RAM_29(func('h29)), \\\n\t.INIT_RAM_2A(func('h2a)), \\\n\t.INIT_RAM_2B(func('h2b)), \\\n\t.INIT_RAM_2C(func('h2c)), \\\n\t.INIT_RAM_2D(func('h2d)), \\\n\t.INIT_RAM_2E(func('h2e)), \\\n\t.INIT_RAM_2F(func('h2f)), \\\n\t.INIT_RAM_30(func('h30)), \\\n\t.INIT_RAM_31(func('h31)), \\\n\t.INIT_RAM_32(func('h32)), \\\n\t.INIT_RAM_33(func('h33)), \\\n\t.INIT_RAM_34(func('h34)), \\\n\t.INIT_RAM_35(func('h35)), \\\n\t.INIT_RAM_36(func('h36)), \\\n\t.INIT_RAM_37(func('h37)), \\\n\t.INIT_RAM_38(func('h38)), \\\n\t.INIT_RAM_39(func('h39)), \\\n\t.INIT_RAM_3A(func('h3a)), \\\n\t.INIT_RAM_3B(func('h3b)), \\\n\t.INIT_RAM_3C(func('h3c)), \\\n\t.INIT_RAM_3D(func('h3d)), \\\n\t.INIT_RAM_3E(func('h3e)), \\\n\t.INIT_RAM_3F(func('h3f)),\n\nmodule $__GOWIN_SP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESET_MODE = \"SYNC\";\n\nparameter PORT_A_WIDTH = 36;\nparameter PORT_A_WR_BE_WIDTH = 4;\nparameter PORT_A_OPTION_WRITE_MODE = 0;\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput PORT_A_WR_EN;\ninput PORT_A_RD_SRST;\ninput PORT_A_RD_ARST;\ninput [13:0] PORT_A_ADDR;\ninput [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;\ninput [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;\n\n`DEF_FUNCS\n\nwire RST = OPTION_RESET_MODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST;\nwire WRE = `wre(PORT_A_WIDTH, PORT_A_WR_EN, PORT_A_WR_BE);\nwire [13:0] AD = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE);\n\ngenerate\n\nif (PORT_A_WIDTH < 9) begin\n\n\twire [31:0] DI = `x8_wr_data(PORT_A_WR_DATA);\n\twire [31:0] DO;\n\n\tassign PORT_A_RD_DATA = `x8_rd_data(DO);\n\n\tSP #(\n\t\t`INIT(init_slice_x8)\n\t\t.READ_MODE(1'b0),\n\t\t.WRITE_MODE(PORT_A_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH(`x8_width(PORT_A_WIDTH)),\n\t\t.BLK_SEL(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSEL(3'b000),\n\t\t.CLK(PORT_A_CLK),\n\t\t.CE(PORT_A_CLK_EN),\n\t\t.WRE(WRE),\n\t\t.RESET(RST),\n\t\t.OCE(1'b0),\n\t\t.AD(AD),\n\t\t.DI(DI),\n\t\t.DO(DO),\n\t);\n\nend else begin\n\n\twire [35:0] DI = PORT_A_WR_DATA;\n\twire [35:0] DO;\n\n\tassign PORT_A_RD_DATA = DO;\n\n\tSPX9 #(\n\t\t`INIT(init_slice_x9)\n\t\t.READ_MODE(1'b0),\n\t\t.WRITE_MODE(PORT_A_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH(PORT_A_WIDTH),\n\t\t.BLK_SEL(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSEL(3'b000),\n\t\t.CLK(PORT_A_CLK),\n\t\t.CE(PORT_A_CLK_EN),\n\t\t.WRE(WRE),\n\t\t.RESET(RST),\n\t\t.OCE(1'b0),\n\t\t.AD(AD),\n\t\t.DI(DI),\n\t\t.DO(DO),\n\t);\n\nend\n\nendgenerate\n\nendmodule\n\n\nmodule $__GOWIN_DP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESET_MODE = \"SYNC\";\n\nparameter PORT_A_WIDTH = 18;\nparameter PORT_A_WR_BE_WIDTH = 2;\nparameter PORT_A_OPTION_WRITE_MODE = 0;\n\nparameter PORT_B_WIDTH = 18;\nparameter PORT_B_WR_BE_WIDTH = 2;\nparameter PORT_B_OPTION_WRITE_MODE = 0;\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput PORT_A_WR_EN;\ninput PORT_A_RD_SRST;\ninput PORT_A_RD_ARST;\ninput [13:0] PORT_A_ADDR;\ninput [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;\ninput [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;\n\ninput PORT_B_CLK;\ninput PORT_B_CLK_EN;\ninput PORT_B_WR_EN;\ninput PORT_B_RD_SRST;\ninput PORT_B_RD_ARST;\ninput [13:0] PORT_B_ADDR;\ninput [PORT_A_WR_BE_WIDTH-1:0] PORT_B_WR_BE;\ninput [PORT_A_WIDTH-1:0] PORT_B_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_B_RD_DATA;\n\n`DEF_FUNCS\n\nwire RSTA = OPTION_RESET_MODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST;\nwire RSTB = OPTION_RESET_MODE == \"SYNC\" ? PORT_B_RD_SRST : PORT_B_RD_ARST;\nwire WREA = `wre(PORT_A_WIDTH, PORT_A_WR_EN, PORT_A_WR_BE);\nwire WREB = `wre(PORT_B_WIDTH, PORT_B_WR_EN, PORT_B_WR_BE);\nwire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE);\nwire [13:0] ADB = `addrbe(PORT_B_WIDTH, PORT_B_ADDR, PORT_B_WR_BE);\n\ngenerate\n\nif (PORT_A_WIDTH < 9 || PORT_B_WIDTH < 9) begin\n\n\twire [15:0] DIA = `x8_wr_data(PORT_A_WR_DATA);\n\twire [15:0] DIB = `x8_wr_data(PORT_B_WR_DATA);\n\twire [15:0] DOA;\n\twire [15:0] DOB;\n\n\tassign PORT_A_RD_DATA = `x8_rd_data(DOA);\n\tassign PORT_B_RD_DATA = `x8_rd_data(DOB);\n\n\tDP #(\n\t\t`INIT(init_slice_x8)\n\t\t.READ_MODE0(1'b0),\n\t\t.READ_MODE1(1'b0),\n\t\t.WRITE_MODE0(PORT_A_OPTION_WRITE_MODE),\n\t\t.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH_0(`x8_width(PORT_A_WIDTH)),\n\t\t.BIT_WIDTH_1(`x8_width(PORT_B_WIDTH)),\n\t\t.BLK_SEL(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSEL(3'b000),\n\n\t\t.CLKA(PORT_A_CLK),\n\t\t.CEA(PORT_A_CLK_EN),\n\t\t.WREA(WREA),\n\t\t.RESETA(RSTA),\n\t\t.OCEA(1'b0),\n\t\t.ADA(ADA),\n\t\t.DIA(DIA),\n\t\t.DOA(DOA),\n\n\t\t.CLKB(PORT_B_CLK),\n\t\t.CEB(PORT_B_CLK_EN),\n\t\t.WREB(WREB),\n\t\t.RESETB(RSTB),\n\t\t.OCEB(1'b0),\n\t\t.ADB(ADB),\n\t\t.DIB(DIB),\n\t\t.DOB(DOB),\n\t);\n\nend else begin\n\n\twire [17:0] DIA = PORT_A_WR_DATA;\n\twire [17:0] DIB = PORT_B_WR_DATA;\n\twire [17:0] DOA;\n\twire [17:0] DOB;\n\n\tassign PORT_A_RD_DATA = DOA;\n\tassign PORT_B_RD_DATA = DOB;\n\n\tDPX9 #(\n\t\t`INIT(init_slice_x9)\n\t\t.READ_MODE0(1'b0),\n\t\t.READ_MODE1(1'b0),\n\t\t.WRITE_MODE0(PORT_A_OPTION_WRITE_MODE),\n\t\t.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH_0(PORT_A_WIDTH),\n\t\t.BIT_WIDTH_1(PORT_B_WIDTH),\n\t\t.BLK_SEL(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSEL(3'b000),\n\n\t\t.CLKA(PORT_A_CLK),\n\t\t.CEA(PORT_A_CLK_EN),\n\t\t.WREA(WREA),\n\t\t.RESETA(RSTA),\n\t\t.OCEA(1'b0),\n\t\t.ADA(ADA),\n\t\t.DIA(DIA),\n\t\t.DOA(DOA),\n\n\t\t.CLKB(PORT_B_CLK),\n\t\t.CEB(PORT_B_CLK_EN),\n\t\t.WREB(WREB),\n\t\t.RESETB(RSTB),\n\t\t.OCEB(1'b0),\n\t\t.ADB(ADB),\n\t\t.DIB(DIB),\n\t\t.DOB(DOB),\n\t);\n\nend\n\nendgenerate\n\nendmodule\n\n\nmodule $__GOWIN_SDP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESET_MODE = \"SYNC\";\n\nparameter PORT_R_WIDTH = 18;\n\nparameter PORT_W_WIDTH = 18;\nparameter PORT_W_WR_BE_WIDTH = 2;\n\ninput PORT_R_CLK;\ninput PORT_R_CLK_EN;\ninput PORT_R_RD_SRST;\ninput PORT_R_RD_ARST;\ninput [13:0] PORT_R_ADDR;\noutput [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;\n\ninput PORT_W_CLK;\ninput PORT_W_CLK_EN;\ninput PORT_W_WR_EN;\ninput [13:0] PORT_W_ADDR;\ninput [PORT_W_WR_BE_WIDTH-1:0] PORT_W_WR_BE;\ninput [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;\n\n`DEF_FUNCS\n\nwire RST = OPTION_RESET_MODE == \"SYNC\" ? PORT_R_RD_SRST : PORT_R_RD_ARST;\nwire WRE = `wre(PORT_W_WIDTH, PORT_W_WR_EN, PORT_W_WR_BE);\nwire [13:0] ADW = `addrbe(PORT_W_WIDTH, PORT_W_ADDR, PORT_W_WR_BE);\n\ngenerate\n\nif (PORT_W_WIDTH < 9 || PORT_R_WIDTH < 9) begin\n\n\twire [31:0] DI = `x8_wr_data(PORT_W_WR_DATA);\n\twire [31:0] DO;\n\n\tassign PORT_R_RD_DATA = `x8_rd_data(DO);\n\n\tSDP #(\n\t\t`INIT(init_slice_x8)\n\t\t.READ_MODE(1'b0),\n\t\t.BIT_WIDTH_0(`x8_width(PORT_W_WIDTH)),\n\t\t.BIT_WIDTH_1(`x8_width(PORT_R_WIDTH)),\n\t\t.BLK_SEL(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSEL(3'b000),\n\n\t\t.CLKA(PORT_W_CLK),\n\t\t.CEA(PORT_W_CLK_EN),\n\t\t.WREA(WRE),\n\t\t.RESETA(1'b0),\n\t\t.ADA(ADW),\n\t\t.DI(DI),\n\n\t\t.CLKB(PORT_R_CLK),\n\t\t.CEB(PORT_R_CLK_EN),\n\t\t.WREB(1'b0),\n\t\t.RESETB(RST),\n\t\t.OCE(1'b0),\n\t\t.ADB(PORT_R_ADDR),\n\t\t.DO(DO),\n\t);\n\nend else begin\n\n\twire [35:0] DI = PORT_W_WR_DATA;\n\twire [35:0] DO;\n\n\tassign PORT_R_RD_DATA = DO;\n\n\tSDPX9 #(\n\t\t`INIT(init_slice_x9)\n\t\t.READ_MODE(1'b0),\n\t\t.BIT_WIDTH_0(PORT_W_WIDTH),\n\t\t.BIT_WIDTH_1(PORT_R_WIDTH),\n\t\t.BLK_SEL(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSEL(3'b000),\n\n\t\t.CLKA(PORT_W_CLK),\n\t\t.CEA(PORT_W_CLK_EN),\n\t\t.WREA(WRE),\n\t\t.RESETA(1'b0),\n\t\t.ADA(ADW),\n\t\t.DI(DI),\n\n\t\t.CLKB(PORT_R_CLK),\n\t\t.CEB(PORT_R_CLK_EN),\n\t\t.WREB(1'b0),\n\t\t.RESETB(RST),\n\t\t.OCE(1'b0),\n\t\t.ADB(PORT_R_ADDR),\n\t\t.DO(DO),\n\t);\n\nend\n\nendgenerate\n\nendmodule\n",
94
+ "brams_map.v": "`define DEF_FUNCS \\\n\tfunction [255:0] init_slice_x8; \\\n\t\tinput integer idx; \\\n\t\tinteger i; \\\n\t\tfor (i = 0; i < 32; i = i + 1) begin \\\n\t\t\tinit_slice_x8[i*8+:8] = INIT[(idx * 32 + i) * 9+:8]; \\\n\t\tend \\\n\tendfunction \\\n\tfunction [287:0] init_slice_x9; \\\n\t\tinput integer idx; \\\n\t\tinit_slice_x9 = INIT[idx * 288+:288]; \\\n\tendfunction \\\n\n`define x8_width(width) (width / 9 * 8 + width % 9)\n`define x8_rd_data(data) {1'bx, data[31:24], 1'bx, data[23:16], 1'bx, data[15:8], 1'bx, data[7:0]}\n`define x8_wr_data(data) {data[34:27], data[25:18], data[16:9], data[7:0]}\n`define wre(width, wr_en, wr_be) (width < 18 ? wr_en | wr_be[0] : wr_en)\n`define addrbe(width, addr, wr_be) (width < 18 ? addr : {addr[13:4], wr_be})\n\n\n`define INIT(func) \\\n\t.INIT_RAM_00(func('h00)), \\\n\t.INIT_RAM_01(func('h01)), \\\n\t.INIT_RAM_02(func('h02)), \\\n\t.INIT_RAM_03(func('h03)), \\\n\t.INIT_RAM_04(func('h04)), \\\n\t.INIT_RAM_05(func('h05)), \\\n\t.INIT_RAM_06(func('h06)), \\\n\t.INIT_RAM_07(func('h07)), \\\n\t.INIT_RAM_08(func('h08)), \\\n\t.INIT_RAM_09(func('h09)), \\\n\t.INIT_RAM_0A(func('h0a)), \\\n\t.INIT_RAM_0B(func('h0b)), \\\n\t.INIT_RAM_0C(func('h0c)), \\\n\t.INIT_RAM_0D(func('h0d)), \\\n\t.INIT_RAM_0E(func('h0e)), \\\n\t.INIT_RAM_0F(func('h0f)), \\\n\t.INIT_RAM_10(func('h10)), \\\n\t.INIT_RAM_11(func('h11)), \\\n\t.INIT_RAM_12(func('h12)), \\\n\t.INIT_RAM_13(func('h13)), \\\n\t.INIT_RAM_14(func('h14)), \\\n\t.INIT_RAM_15(func('h15)), \\\n\t.INIT_RAM_16(func('h16)), \\\n\t.INIT_RAM_17(func('h17)), \\\n\t.INIT_RAM_18(func('h18)), \\\n\t.INIT_RAM_19(func('h19)), \\\n\t.INIT_RAM_1A(func('h1a)), \\\n\t.INIT_RAM_1B(func('h1b)), \\\n\t.INIT_RAM_1C(func('h1c)), \\\n\t.INIT_RAM_1D(func('h1d)), \\\n\t.INIT_RAM_1E(func('h1e)), \\\n\t.INIT_RAM_1F(func('h1f)), \\\n\t.INIT_RAM_20(func('h20)), \\\n\t.INIT_RAM_21(func('h21)), \\\n\t.INIT_RAM_22(func('h22)), \\\n\t.INIT_RAM_23(func('h23)), \\\n\t.INIT_RAM_24(func('h24)), \\\n\t.INIT_RAM_25(func('h25)), \\\n\t.INIT_RAM_26(func('h26)), \\\n\t.INIT_RAM_27(func('h27)), \\\n\t.INIT_RAM_28(func('h28)), \\\n\t.INIT_RAM_29(func('h29)), \\\n\t.INIT_RAM_2A(func('h2a)), \\\n\t.INIT_RAM_2B(func('h2b)), \\\n\t.INIT_RAM_2C(func('h2c)), \\\n\t.INIT_RAM_2D(func('h2d)), \\\n\t.INIT_RAM_2E(func('h2e)), \\\n\t.INIT_RAM_2F(func('h2f)), \\\n\t.INIT_RAM_30(func('h30)), \\\n\t.INIT_RAM_31(func('h31)), \\\n\t.INIT_RAM_32(func('h32)), \\\n\t.INIT_RAM_33(func('h33)), \\\n\t.INIT_RAM_34(func('h34)), \\\n\t.INIT_RAM_35(func('h35)), \\\n\t.INIT_RAM_36(func('h36)), \\\n\t.INIT_RAM_37(func('h37)), \\\n\t.INIT_RAM_38(func('h38)), \\\n\t.INIT_RAM_39(func('h39)), \\\n\t.INIT_RAM_3A(func('h3a)), \\\n\t.INIT_RAM_3B(func('h3b)), \\\n\t.INIT_RAM_3C(func('h3c)), \\\n\t.INIT_RAM_3D(func('h3d)), \\\n\t.INIT_RAM_3E(func('h3e)), \\\n\t.INIT_RAM_3F(func('h3f)),\n\nmodule $__GOWIN_SP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESET_MODE = \"SYNC\";\n\nparameter PORT_A_WIDTH = 36;\nparameter PORT_A_WR_BE_WIDTH = 4;\nparameter PORT_A_OPTION_WRITE_MODE = 0;\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput PORT_A_WR_EN;\ninput PORT_A_RD_SRST;\ninput PORT_A_RD_ARST;\ninput [13:0] PORT_A_ADDR;\ninput [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;\ninput [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;\n\n`DEF_FUNCS\n\nwire RST = OPTION_RESET_MODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST;\nwire WRE = `wre(PORT_A_WIDTH, PORT_A_WR_EN, PORT_A_WR_BE);\nwire [13:0] AD = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE);\n\ngenerate\n\nif (PORT_A_WIDTH < 9) begin\n\n\twire [31:0] DI = `x8_wr_data(PORT_A_WR_DATA);\n\twire [31:0] DO;\n\n\tassign PORT_A_RD_DATA = `x8_rd_data(DO);\n\n\tSP #(\n\t\t`INIT(init_slice_x8)\n\t\t.READ_MODE(1'b0),\n\t\t.WRITE_MODE(PORT_A_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH(`x8_width(PORT_A_WIDTH)),\n\t\t.BLK_SEL(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSEL(3'b000),\n\t\t.CLK(PORT_A_CLK),\n\t\t.CE(PORT_A_CLK_EN),\n\t\t.WRE(WRE),\n\t\t.RESET(RST),\n\t\t.OCE(1'b1),\n\t\t.AD(AD),\n\t\t.DI(DI),\n\t\t.DO(DO),\n\t);\n\nend else begin\n\n\twire [35:0] DI = PORT_A_WR_DATA;\n\twire [35:0] DO;\n\n\tassign PORT_A_RD_DATA = DO;\n\n\tSPX9 #(\n\t\t`INIT(init_slice_x9)\n\t\t.READ_MODE(1'b0),\n\t\t.WRITE_MODE(PORT_A_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH(PORT_A_WIDTH),\n\t\t.BLK_SEL(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSEL(3'b000),\n\t\t.CLK(PORT_A_CLK),\n\t\t.CE(PORT_A_CLK_EN),\n\t\t.WRE(WRE),\n\t\t.RESET(RST),\n\t\t.OCE(1'b1),\n\t\t.AD(AD),\n\t\t.DI(DI),\n\t\t.DO(DO),\n\t);\n\nend\n\nendgenerate\n\nendmodule\n\n\nmodule $__GOWIN_DP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESET_MODE = \"SYNC\";\n\nparameter PORT_A_WIDTH = 18;\nparameter PORT_A_WR_BE_WIDTH = 2;\nparameter PORT_A_OPTION_WRITE_MODE = 0;\n\nparameter PORT_B_WIDTH = 18;\nparameter PORT_B_WR_BE_WIDTH = 2;\nparameter PORT_B_OPTION_WRITE_MODE = 0;\n\ninput PORT_A_CLK;\ninput PORT_A_CLK_EN;\ninput PORT_A_WR_EN;\ninput PORT_A_RD_SRST;\ninput PORT_A_RD_ARST;\ninput [13:0] PORT_A_ADDR;\ninput [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;\ninput [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;\n\ninput PORT_B_CLK;\ninput PORT_B_CLK_EN;\ninput PORT_B_WR_EN;\ninput PORT_B_RD_SRST;\ninput PORT_B_RD_ARST;\ninput [13:0] PORT_B_ADDR;\ninput [PORT_A_WR_BE_WIDTH-1:0] PORT_B_WR_BE;\ninput [PORT_A_WIDTH-1:0] PORT_B_WR_DATA;\noutput [PORT_A_WIDTH-1:0] PORT_B_RD_DATA;\n\n`DEF_FUNCS\n\nwire RSTA = OPTION_RESET_MODE == \"SYNC\" ? PORT_A_RD_SRST : PORT_A_RD_ARST;\nwire RSTB = OPTION_RESET_MODE == \"SYNC\" ? PORT_B_RD_SRST : PORT_B_RD_ARST;\nwire WREA = `wre(PORT_A_WIDTH, PORT_A_WR_EN, PORT_A_WR_BE);\nwire WREB = `wre(PORT_B_WIDTH, PORT_B_WR_EN, PORT_B_WR_BE);\nwire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE);\nwire [13:0] ADB = `addrbe(PORT_B_WIDTH, PORT_B_ADDR, PORT_B_WR_BE);\n\ngenerate\n\nif (PORT_A_WIDTH < 9 || PORT_B_WIDTH < 9) begin\n\n\twire [15:0] DIA = `x8_wr_data(PORT_A_WR_DATA);\n\twire [15:0] DIB = `x8_wr_data(PORT_B_WR_DATA);\n\twire [15:0] DOA;\n\twire [15:0] DOB;\n\n\tassign PORT_A_RD_DATA = `x8_rd_data(DOA);\n\tassign PORT_B_RD_DATA = `x8_rd_data(DOB);\n\n\tDPB #(\n\t\t`INIT(init_slice_x8)\n\t\t.READ_MODE0(1'b0),\n\t\t.READ_MODE1(1'b0),\n\t\t.WRITE_MODE0(PORT_A_OPTION_WRITE_MODE),\n\t\t.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH_0(`x8_width(PORT_A_WIDTH)),\n\t\t.BIT_WIDTH_1(`x8_width(PORT_B_WIDTH)),\n\t\t.BLK_SEL_0(3'b000),\n\t\t.BLK_SEL_1(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSELA(3'b000),\n\t\t.BLKSELB(3'b000),\n\n\t\t.CLKA(PORT_A_CLK),\n\t\t.CEA(PORT_A_CLK_EN),\n\t\t.WREA(WREA),\n\t\t.RESETA(RSTA),\n\t\t.OCEA(1'b1),\n\t\t.ADA(ADA),\n\t\t.DIA(DIA),\n\t\t.DOA(DOA),\n\n\t\t.CLKB(PORT_B_CLK),\n\t\t.CEB(PORT_B_CLK_EN),\n\t\t.WREB(WREB),\n\t\t.RESETB(RSTB),\n\t\t.OCEB(1'b1),\n\t\t.ADB(ADB),\n\t\t.DIB(DIB),\n\t\t.DOB(DOB),\n\t);\n\nend else begin\n\n\twire [17:0] DIA = PORT_A_WR_DATA;\n\twire [17:0] DIB = PORT_B_WR_DATA;\n\twire [17:0] DOA;\n\twire [17:0] DOB;\n\n\tassign PORT_A_RD_DATA = DOA;\n\tassign PORT_B_RD_DATA = DOB;\n\n\tDPX9B #(\n\t\t`INIT(init_slice_x9)\n\t\t.READ_MODE0(1'b0),\n\t\t.READ_MODE1(1'b0),\n\t\t.WRITE_MODE0(PORT_A_OPTION_WRITE_MODE),\n\t\t.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),\n\t\t.BIT_WIDTH_0(PORT_A_WIDTH),\n\t\t.BIT_WIDTH_1(PORT_B_WIDTH),\n\t\t.BLK_SEL_0(3'b000),\n\t\t.BLK_SEL_1(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSELA(3'b000),\n\t\t.BLKSELB(3'b000),\n\n\t\t.CLKA(PORT_A_CLK),\n\t\t.CEA(PORT_A_CLK_EN),\n\t\t.WREA(WREA),\n\t\t.RESETA(RSTA),\n\t\t.OCEA(1'b1),\n\t\t.ADA(ADA),\n\t\t.DIA(DIA),\n\t\t.DOA(DOA),\n\n\t\t.CLKB(PORT_B_CLK),\n\t\t.CEB(PORT_B_CLK_EN),\n\t\t.WREB(WREB),\n\t\t.RESETB(RSTB),\n\t\t.OCEB(1'b1),\n\t\t.ADB(ADB),\n\t\t.DIB(DIB),\n\t\t.DOB(DOB),\n\t);\n\nend\n\nendgenerate\n\nendmodule\n\n\nmodule $__GOWIN_SDP_ (...);\n\nparameter INIT = 0;\nparameter OPTION_RESET_MODE = \"SYNC\";\n\nparameter PORT_R_WIDTH = 18;\n\nparameter PORT_W_WIDTH = 18;\nparameter PORT_W_WR_BE_WIDTH = 2;\n\ninput PORT_R_CLK;\ninput PORT_R_CLK_EN;\ninput PORT_R_RD_SRST;\ninput PORT_R_RD_ARST;\ninput [13:0] PORT_R_ADDR;\noutput [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;\n\ninput PORT_W_CLK;\ninput PORT_W_CLK_EN;\ninput PORT_W_WR_EN;\ninput [13:0] PORT_W_ADDR;\ninput [PORT_W_WR_BE_WIDTH-1:0] PORT_W_WR_BE;\ninput [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;\n\n`DEF_FUNCS\n\nwire RST = OPTION_RESET_MODE == \"SYNC\" ? PORT_R_RD_SRST : PORT_R_RD_ARST;\nwire WRE = `wre(PORT_W_WIDTH, PORT_W_WR_EN, PORT_W_WR_BE);\nwire [13:0] ADW = `addrbe(PORT_W_WIDTH, PORT_W_ADDR, PORT_W_WR_BE);\n\ngenerate\n\nif (PORT_W_WIDTH < 9 || PORT_R_WIDTH < 9) begin\n\n\twire [31:0] DI = `x8_wr_data(PORT_W_WR_DATA);\n\twire [31:0] DO;\n\n\tassign PORT_R_RD_DATA = `x8_rd_data(DO);\n\n\tSDPB #(\n\t\t`INIT(init_slice_x8)\n\t\t.READ_MODE(1'b0),\n\t\t.BIT_WIDTH_0(`x8_width(PORT_W_WIDTH)),\n\t\t.BIT_WIDTH_1(`x8_width(PORT_R_WIDTH)),\n\t\t.BLK_SEL_0(3'b000),\n\t\t.BLK_SEL_1(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSELA(3'b000),\n\t\t.BLKSELB(3'b000),\n\n\t\t.CLKA(PORT_W_CLK),\n\t\t.CEA(PORT_W_CLK_EN),\n\t\t.RESETA(1'b0),\n\t\t.ADA(ADW),\n\t\t.DI(DI),\n\n\t\t.CLKB(PORT_R_CLK),\n\t\t.CEB(PORT_R_CLK_EN),\n\t\t.RESETB(RST),\n\t\t.OCE(1'b1),\n\t\t.ADB(PORT_R_ADDR),\n\t\t.DO(DO),\n\t);\n\nend else begin\n\n\twire [35:0] DI = PORT_W_WR_DATA;\n\twire [35:0] DO;\n\n\tassign PORT_R_RD_DATA = DO;\n\n\tSDPX9B #(\n\t\t`INIT(init_slice_x9)\n\t\t.READ_MODE(1'b0),\n\t\t.BIT_WIDTH_0(PORT_W_WIDTH),\n\t\t.BIT_WIDTH_1(PORT_R_WIDTH),\n\t\t.BLK_SEL_0(3'b000),\n\t\t.BLK_SEL_1(3'b000),\n\t\t.RESET_MODE(OPTION_RESET_MODE),\n\t) _TECHMAP_REPLACE_ (\n\t\t.BLKSELA(3'b000),\n\t\t.BLKSELB(3'b000),\n\n\t\t.CLKA(PORT_W_CLK),\n\t\t.CEA(PORT_W_CLK_EN),\n\t\t.RESETA(1'b0),\n\t\t.ADA(ADW),\n\t\t.DI(DI),\n\n\t\t.CLKB(PORT_R_CLK),\n\t\t.CEB(PORT_R_CLK_EN),\n\t\t.RESETB(RST),\n\t\t.OCE(1'b1),\n\t\t.ADB(PORT_R_ADDR),\n\t\t.DO(DO),\n\t);\n\nend\n\nendgenerate\n\nendmodule\n",
95
95
  "cells_map.v": "`default_nettype none\n//All DFF* have INIT, but the hardware is always initialised to the reset\n//value regardless. The parameter is ignored.\n\n// DFFN\t\t\t D Flip-Flop with Negative-Edge Clock\nmodule\t\\$_DFF_N_ (input D, C, output Q);\n\tDFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFF\t\t\t D Flip-Flop\nmodule\t\\$_DFF_P_ (input D, C, output Q);\n\tDFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFE\t\t\t D Flip-Flop with Clock Enable\nmodule\t\\$_DFFE_PP_ (input D, C, E, output Q);\n\tDFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNE\t\t D Flip-Flop with Negative-Edge Clock and Clock Enable\nmodule\t\\$_DFFE_NP_ (input D, C, E, output Q);\n\tDFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFR\t\t\t D Flip-Flop with Synchronous Reset\nmodule\t\\$_SDFF_PP0_ (input D, C, R, output Q);\n\tDFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNR\t\t D Flip-Flop with Negative-Edge Clock and Synchronous Reset\nmodule\t\\$_SDFF_NP0_ (input D, C, R, output Q);\n\tDFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFRE\t\t D Flip-Flop with Clock Enable and Synchronous Reset\nmodule\t\\$_SDFFE_PP0P_ (input D, C, R, E, output Q);\n\tDFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNRE\t\t D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset\nmodule\t\\$_SDFFE_NP0P_ (input D, C, R, E, output Q);\n\tDFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFS\t\t\t D Flip-Flop with Synchronous Set\nmodule\t\\$_SDFF_PP1_ (input D, C, R, output Q);\n\tDFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNS\t\t D Flip-Flop with Negative-Edge Clock and Synchronous Set\nmodule\t\\$_SDFF_NP1_ (input D, C, R, output Q);\n\tDFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFSE\t\t D Flip-Flop with Clock Enable and Synchronous Set\nmodule\t\\$_SDFFE_PP1P_ (input D, C, R, E, output Q);\n\tDFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNSE\t\t D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set\nmodule\t\\$_SDFFE_NP1P_ (input D, C, R, E, output Q);\n\tDFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFP\t\t\t D Flip-Flop with Asynchronous Preset\nmodule\t\\$_DFF_PP1_ (input D, C, R, output Q);\n\tDFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNP\t\t D Flip-Flop with Negative-Edge Clock and Asynchronous Preset\nmodule\t\\$_DFF_NP1_ (input D, C, R, output Q);\n\tDFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFC\t\t\t D Flip-Flop with Asynchronous Clear\nmodule\t\\$_DFF_PP0_ (input D, C, R, output Q);\n\tDFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNC\t\t D Flip-Flop with Negative-Edge Clock and Asynchronous Clear\nmodule\t\\$_DFF_NP0_ (input D, C, R, output Q);\n\tDFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFPE\t\t D Flip-Flop with Clock Enable and Asynchronous Preset\nmodule\t\\$_DFFE_PP1P_ (input D, C, R, E, output Q);\n\tDFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNPE\t\t D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset\nmodule\t\\$_DFFE_NP1P_ (input D, C, R, E, output Q);\n\tDFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFCE\t\t D Flip-Flop with Clock Enable and Asynchronous Clear\nmodule\t\\$_DFFE_PP0P_ (input D, C, R, E, output Q);\n\tDFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\n// DFFNCE\t\t D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear\nmodule\t\\$_DFFE_NP0P_ (input D, C, R, E, output Q);\n\tDFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));\n\twire _TECHMAP_REMOVEINIT_Q_ = 1;\nendmodule\n\nmodule \\$lut (A, Y);\n\tparameter WIDTH = 0;\n\tparameter LUT = 0;\n\n\t(* force_downto *)\n\tinput [WIDTH-1:0] A;\n\toutput Y;\n\n\tgenerate\n\t\tif (WIDTH == 1) begin\n\t\t\tLUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),\n\t\t\t\t.I0(A[0]));\n\t\tend else\n\t\tif (WIDTH == 2) begin\n\t\t\tLUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),\n\t\t\t\t.I0(A[0]), .I1(A[1]));\n\t\tend else\n\t\tif (WIDTH == 3) begin\n\t\t\tLUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),\n\t\t\t\t.I0(A[0]), .I1(A[1]), .I2(A[2]));\n\t\tend else\n\t\tif (WIDTH == 4) begin\n\t\t\tLUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),\n\t\t\t\t.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));\n\t\tend else\n\t\tif (WIDTH == 5) begin\n\t\t\twire f0, f1;\n\t\t\t\\$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0));\n\t\t\t\\$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1));\n\t\t\tMUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[4]), .O(Y));\n\t\tend else\n\t\tif (WIDTH == 6) begin\n\t\t\twire f0, f1;\n\t\t\t\\$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0));\n\t\t\t\\$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1));\n\t\t\tMUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[5]), .O(Y));\n\t\tend else\n\t\tif (WIDTH == 7) begin\n\t\t\twire f0, f1;\n\t\t\t\\$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0));\n\t\t\t\\$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1));\n\t\t\tMUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[6]), .O(Y));\n\t\tend else\n\t\tif (WIDTH == 8) begin\n\t\t\twire f0, f1;\n\t\t\t\\$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));\n\t\t\t\\$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));\n\t\t\tMUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[7]), .O(Y));\n\t\tend else begin\n\t\t\twire _TECHMAP_FAIL_ = 1;\n\t\tend\n\tendgenerate\nendmodule\n",
96
96
  "cells_sim.v": "(* abc9_lut=1 *)\nmodule LUT1(output F, input I0);\n\tparameter [1:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (555, 902);\n\tendspecify\n\tassign F = I0 ? INIT[1] : INIT[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT2(output F, input I0, I1);\n\tparameter [3:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (867, 1184);\n\t\t(I1 => F) = (555, 902);\n\tendspecify\n\twire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT3(output F, input I0, I1, I2);\n\tparameter [7:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (1054, 1486);\n\t\t(I1 => F) = (867, 1184);\n\t\t(I2 => F) = (555, 902);\n\tendspecify\t\n\twire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];\n\twire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=1 *)\nmodule LUT4(output F, input I0, I1, I2, I3);\n\tparameter [15:0] INIT = 0;\n\tspecify\n\t\t(I0 => F) = (1054, 1486);\n\t\t(I1 => F) = (1053, 1583);\n\t\t(I2 => F) = (867, 1184);\n\t\t(I3 => F) = (555, 902);\n\tendspecify\t\n\twire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];\n\twire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];\n\twire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];\n\tassign F = I0 ? s1[1] : s1[0];\nendmodule\n\n(* abc9_lut=2 *)\nmodule __APICULA_LUT5(output F, input I0, I1, I2, I3, M0);\n\tspecify\n\t\t(I0 => F) = (1187, 1638);\n\t\t(I1 => F) = (1184, 1638);\n\t\t(I2 => F) = (995, 1371);\n\t\t(I3 => F) = (808, 1116);\n\t\t(M0 => F) = (486, 680);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=4 *)\nmodule __APICULA_LUT6(output F, input I0, I1, I2, I3, M0, M1);\n\tspecify\n\t\t(I0 => F) = (1187 + 136, 1638 + 255);\n\t\t(I1 => F) = (1184 + 136, 1638 + 255);\n\t\t(I2 => F) = (995 + 136, 1371 + 255);\n\t\t(I3 => F) = (808 + 136, 1116 + 255);\n\t\t(M0 => F) = (486 + 136, 680 + 255);\n\t\t(M1 => F) = (478, 723);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=8 *)\nmodule __APICULA_LUT7(output F, input I0, I1, I2, I3, M0, M1, M2);\n\tspecify\n\t\t(I0 => F) = (1187 + 136 + 136, 1638 + 255 + 255);\n\t\t(I1 => F) = (1184 + 136 + 136, 1638 + 255 + 255);\n\t\t(I2 => F) = (995 + 136 + 136, 1371 + 255 + 255);\n\t\t(I3 => F) = (808 + 136 + 136, 1116 + 255 + 255);\n\t\t(M0 => F) = (486 + 136 + 136, 680 + 255 + 255);\n\t\t(M1 => F) = (478 + 136, 723 + 255);\n\t\t(M2 => F) = (478, 723);\n\tendspecify\t\nendmodule\n\n(* abc9_lut=16 *)\nmodule __APICULA_LUT8(output F, input I0, I1, I2, I3, M0, M1, M2, M3);\n\t\tspecify\n\t\t(I0 => F) = (1187 + 136 + 136 + 136, 1638 + 255 + 255 + 255);\n\t\t(I1 => F) = (1184 + 136 + 136 + 136, 1638 + 255 + 255 + 255);\n\t\t(I2 => F) = (995 + 136 + 136 + 136, 1371 + 255 + 255 + 255);\n\t\t(I3 => F) = (808 + 136 + 136 + 136, 1116 + 255 + 255 + 255);\n\t\t(M0 => F) = (486 + 136 + 136 + 136, 680 + 255 + 255 + 255);\n\t\t(M1 => F) = (478 + 136 + 136, 723 + 255 + 255);\n\t\t(M2 => F) = (478 + 136, 723 + 255);\n\t\t(M3 => F) = (478, 723);\n\t\tendspecify\t\n\tendmodule\n\nmodule MUX2 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (141, 160);\n\t\t(I1 => O) = (141, 160);\n\t\t(S0 => O) = (486, 680);\n\tendspecify\n\n assign O = S0 ? I1 : I0;\nendmodule\n\nmodule MUX2_LUT5 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (141, 160);\n\t\t(I1 => O) = (141, 160);\n\t\t(S0 => O) = (486, 680);\n\tendspecify\n\n MUX2 mux2_lut5 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT6 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n MUX2 mux2_lut6 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT7 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n MUX2 mux2_lut7 (O, I0, I1, S0);\nendmodule\n\nmodule MUX2_LUT8 (O, I0, I1, S0);\n input I0,I1;\n input S0;\n output O;\n\n\tspecify\n\t\t(I0 => O) = (136, 255);\n\t\t(I1 => O) = (136, 255);\n\t\t(S0 => O) = (478, 723);\n\tendspecify\n\n MUX2 mux2_lut8 (O, I0, I1, S0);\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFF (output reg Q, input CLK, D);\n\tparameter [0:0] INIT = 1'b0;\n\tinitial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n\talways @(posedge CLK)\n\t\tQ <= D;\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFE (output reg Q, input D, CLK, CE);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (CE)\n Q <= D;\n end\nendmodule // DFFE (positive clock edge; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFS (output reg Q, input D, CLK, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\t\t$setup(SET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else\n Q <= D;\t\n end\nendmodule // DFFS (positive clock edge; synchronous set)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFSE (output reg Q, input D, CLK, CE, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\t\t$setup(SET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\nend\nendmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFR (output reg Q, input D, CLK, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK, 576);\n\t\t$setup(RESET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFR (positive clock edge; synchronous reset)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFRE (output reg Q, input D, CLK, CE, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\t\t$setup(RESET, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFP (output reg Q, input D, CLK, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n always @(posedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else\n Q <= D;\n end\nendmodule // DFFP (positive clock edge; asynchronous preset)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFPE (output reg Q, input D, CLK, CE, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFPE (positive clock edge; asynchronous preset; clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFC (output reg Q, input D, CLK, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(posedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK, 576);\n\tendspecify\n\n always @(posedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFC (positive clock edge; asynchronous clear)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFCE (output reg Q, input D, CLK, CE, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (posedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, posedge CLK &&& CE, 576);\n\t\t$setup(CE, posedge CLK, 63);\n\tendspecify\n\n always @(posedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFCE (positive clock edge; asynchronous clear; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFN (output reg Q, input CLK, D);\n\tparameter [0:0] INIT = 1'b0;\n\tinitial Q = INIT;\n\n specify\n (negedge CLK => (Q : D)) = (480, 660);\n $setup(D, negedge CLK, 576);\n endspecify\n\n\talways @(negedge CLK)\n\t\tQ <= D;\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNE (output reg Q, input D, CLK, CE);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (CE)\n Q <= D;\n end\nendmodule // DFFNE (negative clock edge; clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNS (output reg Q, input D, CLK, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n \n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK, 576);\n\t\t$setup(SET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else\n Q <= D;\t\n end\nendmodule // DFFNS (negative clock edge; synchronous set)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNSE (output reg Q, input D, CLK, CE, SET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\t\t$setup(SET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (SET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\nend\nendmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNR (output reg Q, input D, CLK, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK, 576);\n\t\t$setup(RESET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFNR (negative clock edge; synchronous reset)\n\n(* abc9_flop, lib_whitebox *)\nmodule DFFNRE (output reg Q, input D, CLK, CE, RESET);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\t\t$setup(RESET, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK) begin\n if (RESET)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNP (output reg Q, input D, CLK, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK, 576);\n\tendspecify\n\n always @(negedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else\n Q <= D;\n end\nendmodule // DFFNP (negative clock edge; asynchronous preset)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNPE (output reg Q, input D, CLK, CE, PRESET);\n parameter [0:0] INIT = 1'b1;\n initial Q = INIT;\n \n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t(PRESET => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK or posedge PRESET) begin\n if(PRESET)\n Q <= 1'b1;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNC (output reg Q, input D, CLK, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\t(negedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK, 576);\n\tendspecify\n\n always @(negedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else\n Q <= D;\n end\nendmodule // DFFNC (negative clock edge; asynchronous clear)\n\n(* abc9_box, lib_whitebox *)\nmodule DFFNCE (output reg Q, input D, CLK, CE, CLEAR);\n parameter [0:0] INIT = 1'b0;\n initial Q = INIT;\n\n\tspecify\n\t\tif (CE) (negedge CLK => (Q : D)) = (480, 660);\n\t\t(CLEAR => Q) = (1800, 2679);\n\t\t$setup(D, negedge CLK &&& CE, 576);\n\t\t$setup(CE, negedge CLK, 63);\n\tendspecify\n\n always @(negedge CLK or posedge CLEAR) begin\n if(CLEAR)\n Q <= 1'b0;\n else if (CE)\n Q <= D;\n end\nendmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)\n\n// TODO add more DFF sim cells\n\nmodule VCC(output V);\n\tassign V = 1;\nendmodule\n\nmodule GND(output G);\n\tassign G = 0;\nendmodule\n\nmodule IBUF(output O, input I);\n\n\tspecify\n\t\t(I => O) = 0;\n\tendspecify\n\n\tassign O = I;\nendmodule\n\nmodule OBUF(output O, input I);\n\n\tspecify\n\t\t(I => O) = 0;\n\tendspecify\n\n\tassign O = I;\nendmodule\n\nmodule TBUF (O, I, OEN);\n input I, OEN;\n output O;\n assign O = OEN ? 1'bz : I;\nendmodule\n\nmodule IOBUF (O, IO, I, OEN);\n input I,OEN;\n output O;\n inout IO;\n assign IO = OEN ? 1'bz : I;\n assign I = IO;\nendmodule\n\nmodule ELVDS_OBUF (I, O, OB);\n input I;\n output O;\n output OB;\n assign O = I;\n assign OB = ~I;\nendmodule\n\nmodule TLVDS_OBUF (I, O, OB);\n input I;\n output O;\n output OB;\n assign O = I;\n assign OB = ~I;\nendmodule\n\nmodule OSER4(D3, D2, D1, D0, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);\n\toutput Q1;\n\toutput Q0;\n\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput TX1;\n\tinput TX0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\n\tparameter TXCLK_POL = 0;\n\tparameter HWL = \"false\";\nendmodule\n\nmodule OSER8(D7, D6, D5, D4, D3, D2, D1, D0, TX3, TX2, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);\n\toutput Q1;\n\toutput Q0;\n\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput TX3;\n\tinput TX2;\n\tinput TX1;\n\tinput TX0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\n\tparameter TXCLK_POL = 0;\n\tparameter HWL = \"false\";\nendmodule\n\nmodule OSER10(D9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q);\n\toutput Q;\n\n\tinput D9;\n\tinput D8;\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule OVIDEO(D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q);\n\toutput Q;\n\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule OSER16(D15, D14, D13, D12, D11, D10, \nD9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK,\nRESET, Q);\n\toutput Q;\n\n\tinput D15;\n\tinput D14;\n\tinput D13;\n\tinput D12;\n\tinput D11;\n\tinput D10;\n\tinput D9;\n\tinput D8;\n\tinput D7;\n\tinput D6;\n\tinput D5;\n\tinput D4;\n\tinput D3;\n\tinput D2;\n\tinput D1;\n\tinput D0;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES4(Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES8(Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES10(Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q9;\n\toutput Q8;\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IVIDEO(Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDES16(Q15, Q14, Q13, Q12, Q11, Q10, \nQ9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,\nRESET, CALIB, D);\n\tinput D;\n\tinput FCLK;\n\tinput PCLK;\n\tinput RESET;\n\tinput CALIB;\n\n\toutput Q15;\n\toutput Q14;\n\toutput Q13;\n\toutput Q12;\n\toutput Q11;\n\toutput Q10;\n\toutput Q9;\n\toutput Q8;\n\toutput Q7;\n\toutput Q6;\n\toutput Q5;\n\toutput Q4;\n\toutput Q3;\n\toutput Q2;\n\toutput Q1;\n\toutput Q0;\n\n\tparameter GSREN = \"false\";\n\tparameter LSREN = \"true\";\nendmodule\n\nmodule IDDR(D, CLK, Q0, Q1);\n\tinput D;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter Q0_INIT = 1'b0;\n\tparameter Q1_INIT = 1'b0;\nendmodule\n\nmodule IDDRC(D, CLK, CLEAR, Q0, Q1);\n\tinput D;\n\tinput CLK;\n\tinput CLEAR;\n\toutput Q0;\n\toutput Q1;\n\tparameter Q0_INIT = 1'b0;\n\tparameter Q1_INIT = 1'b0;\nendmodule\n\n(* blackbox *)\nmodule ODDR(D0, D1, TX, CLK, Q0, Q1);\n\tinput D0;\n\tinput D1;\n\tinput TX;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter TXCLK_POL = 0;\n\tparameter INIT = 0;\nendmodule\n\n(* blackbox *)\nmodule ODDRC(D0, D1, CLEAR, TX, CLK, Q0, Q1);\n\tinput D0;\n\tinput D1;\n\tinput CLEAR;\n\tinput TX;\n\tinput CLK;\n\toutput Q0;\n\toutput Q1;\n\tparameter TXCLK_POL = 0;\n\tparameter INIT = 0;\nendmodule\n\nmodule GSR (input GSRI);\n\twire GSRO = GSRI;\nendmodule\n\n(* abc9_box, lib_whitebox *)\nmodule ALU (SUM, COUT, I0, I1, I3, CIN);\n\ninput I0;\ninput I1;\ninput I3;\n(* abc9_carry *) input CIN;\noutput SUM;\n(* abc9_carry *) output COUT;\n\nlocalparam ADD = 0;\nlocalparam SUB = 1;\nlocalparam ADDSUB = 2;\nlocalparam NE = 3;\nlocalparam GE = 4;\nlocalparam LE = 5;\nlocalparam CUP = 6;\nlocalparam CDN = 7;\nlocalparam CUPCDN = 8;\nlocalparam MULT = 9;\n\nparameter ALU_MODE = 0;\n\nreg S, C;\n\nspecify\n\t(I0 => SUM) = (1043, 1432);\n\t(I1 => SUM) = (775, 1049);\n\t(I3 => SUM) = (751, 1010);\n\t(CIN => SUM) = (694, 811);\n\t(I0 => COUT) = (1010, 1380);\n\t(I1 => COUT) = (1021, 1505);\n\t(I3 => COUT) = (483, 792);\n\t(CIN => COUT) = (49, 82);\nendspecify\n\nassign SUM = S ^ CIN;\nassign COUT = S? CIN : C;\n\nalways @* begin\n\tcase (ALU_MODE)\n\t\tADD: begin\n\t\t\tS = I0 ^ I1;\n\t\t\tC = I0;\n\t\tend\n\t\tSUB: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tADDSUB: begin\n\t\t\tS = I3? I0 ^ I1 : I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tNE: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = 1'b1;\n\t\tend\n\t\tGE: begin\n\t\t\tS = I0 ^ ~I1;\n\t\t\tC = I0;\n\t\tend\n\t\tLE: begin\n\t\t\tS = ~I0 ^ I1;\n\t\t\tC = I1;\n\t\tend\n\t\tCUP: begin\n\t\t\tS = I0;\n\t\t\tC = 1'b0;\n\t\tend\n\t\tCDN: begin\n\t\t\tS = ~I0;\n\t\t\tC = 1'b1;\n\t\tend\n\t\tCUPCDN: begin\n\t\t\tS = I3? I0 : ~I0;\n\t\t\tC = I0;\n\t\tend\n\t\tMULT: begin\n\t\t\tS = I0 & I1;\n\t\t\tC = I0 & I1;\n\t\tend\n\tendcase\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S1 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\n\ninput [3:0] AD;\ninput DI;\noutput DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 1'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem;\n\ninitial begin\n\tmem = INIT_0;\nend\n\nassign DO = mem[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem[AD] <= DI;\n\tend\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S2 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\n\ninput [3:0] AD;\ninput [1:0] DI;\noutput [1:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 2'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\nend\n\nassign DO[0] = mem0[AD];\nassign DO[1] = mem1[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[AD] <= DI[0];\n\t\tmem1[AD] <= DI[1];\n\tend\nend\n\nendmodule\n\n(* abc9_flop, lib_whitebox *)\nmodule RAM16S4 (DO, DI, AD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\nparameter INIT_2 = 16'h0000;\nparameter INIT_3 = 16'h0000;\n\ninput [3:0] AD;\ninput [3:0] DI;\noutput [3:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(AD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(AD, posedge CLK, 62);\n\t(posedge CLK => (DO : 4'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1, mem2, mem3;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\n\tmem2 = INIT_2;\n\tmem3 = INIT_3;\nend\n\nassign DO[0] = mem0[AD];\nassign DO[1] = mem1[AD];\nassign DO[2] = mem2[AD];\nassign DO[3] = mem3[AD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[AD] <= DI[0];\n\t\tmem1[AD] <= DI[1];\n\t\tmem2[AD] <= DI[2];\n\t\tmem3[AD] <= DI[3];\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP1 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput DI;\noutput DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 1'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem;\n\ninitial begin\n\tmem = INIT_0;\nend\n\nassign DO = mem[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem[WAD] <= DI;\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP2 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput [1:0] DI;\noutput [1:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 2'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\nend\n\nassign DO[0] = mem0[RAD];\nassign DO[1] = mem1[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[WAD] <= DI[0];\n\t\tmem1[WAD] <= DI[1];\n\tend\nend\n\nendmodule\n\n\nmodule RAM16SDP4 (DO, DI, WAD, RAD, WRE, CLK);\n\nparameter INIT_0 = 16'h0000;\nparameter INIT_1 = 16'h0000;\nparameter INIT_2 = 16'h0000;\nparameter INIT_3 = 16'h0000;\n\ninput [3:0] WAD;\ninput [3:0] RAD;\ninput [3:0] DI;\noutput [3:0] DO;\ninput CLK;\ninput WRE;\n\nspecify\n\t(RAD *> DO) = (270, 405);\n\t$setup(DI, posedge CLK, 62);\n\t$setup(WRE, posedge CLK, 62);\n\t$setup(WAD, posedge CLK, 62);\n\t(posedge CLK => (DO : 4'bx)) = (474, 565);\nendspecify\n\nreg [15:0] mem0, mem1, mem2, mem3;\n\ninitial begin\n\tmem0 = INIT_0;\n\tmem1 = INIT_1;\n\tmem2 = INIT_2;\n\tmem3 = INIT_3;\nend\n\nassign DO[0] = mem0[RAD];\nassign DO[1] = mem1[RAD];\nassign DO[2] = mem2[RAD];\nassign DO[3] = mem3[RAD];\n\nalways @(posedge CLK) begin\n\tif (WRE) begin\n\t\tmem0[WAD] <= DI[0];\n\t\tmem1[WAD] <= DI[1];\n\t\tmem2[WAD] <= DI[2];\n\t\tmem3[WAD] <= DI[3];\n\tend\nend\n\nendmodule\n\n\n(* blackbox *)\nmodule SP (DO, DI, BLKSEL, AD, WRE, CLK, CE, OCE, RESET);\n\n// 1 Enables output pipeline registers.\nparameter READ_MODE = 1'b0;\n// 0: no read on write, 1: transparent, 2: read-before-write\nparameter WRITE_MODE = 2'b00;\nparameter BIT_WIDTH = 32; // 1, 2, 4, 8, 16, 32\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [31:0] DO;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] AD;\ninput WRE;\ninput CLK;\ninput CE;\ninput OCE;\ninput RESET;\n\nendmodule\n\n(* blackbox *)\nmodule SPX9 (DO, DI, BLKSEL, AD, WRE, CLK, CE, OCE, RESET);\n\n// 1 Enables output pipeline registers.\nparameter READ_MODE = 1'b0;\n// 0: no read on write, 1: transparent, 2: read-before-write\nparameter WRITE_MODE = 2'b00;\nparameter BIT_WIDTH = 36; // 9, 18, 36\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [35:0] DO;\ninput [35:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] AD;\ninput WRE;\ninput CLK;\ninput CE;\ninput OCE;\ninput RESET;\n\nendmodule\n\n\n(* blackbox *)\nmodule SDP (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);\n\nparameter READ_MODE = 1'b0;\nparameter BIT_WIDTH_0 = 32; // 1, 2, 4, 8, 16, 32\nparameter BIT_WIDTH_1 = 32; // 1, 2, 4, 8, 16, 32\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [31:0] DO;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCE;\ninput RESETA, RESETB;\n\nspecify\n\t(posedge CLKB => (DO : DI)) = (419, 493);\n\t$setup(RESETA, posedge CLKA, 62);\n\t$setup(RESETB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(CEA, posedge CLKA, 62);\n\t$setup(CEB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(WREA, posedge CLKA, 62);\n\t$setup(WREB, posedge CLKB, 62);\n\t$setup(DI, posedge CLKA, 62);\n\t$setup(ADA, posedge CLKA, 62);\n\t$setup(ADB, posedge CLKB, 62);\n\t$setup(BLKSEL, posedge CLKA, 62);\nendspecify\n\nendmodule\n\n(* blackbox *)\nmodule SDPX9 (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);\n\nparameter READ_MODE = 1'b0;\nparameter BIT_WIDTH_0 = 36; // 9, 18, 36\nparameter BIT_WIDTH_1 = 36; // 9, 18, 36\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [35:0] DO;\ninput [35:0] DI;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCE;\ninput RESETA, RESETB;\n\nspecify\n\t(posedge CLKB => (DO : DI)) = (419, 493);\n\t$setup(RESETA, posedge CLKA, 62);\n\t$setup(RESETB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(CEA, posedge CLKA, 62);\n\t$setup(CEB, posedge CLKB, 62);\n\t$setup(OCE, posedge CLKB, 62);\n\t$setup(WREA, posedge CLKA, 62);\n\t$setup(WREB, posedge CLKB, 62);\n\t$setup(DI, posedge CLKA, 62);\n\t$setup(ADA, posedge CLKA, 62);\n\t$setup(ADB, posedge CLKB, 62);\n\t$setup(BLKSEL, posedge CLKA, 62);\nendspecify\n\nendmodule\n\n\n(* blackbox *)\nmodule DP (DOA, DOB, DIA, DIB, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCEA, OCEB, RESETA, RESETB);\n\nparameter READ_MODE0 = 1'b0;\nparameter READ_MODE1 = 1'b0;\nparameter WRITE_MODE0 = 2'b00;\nparameter WRITE_MODE1 = 2'b00;\nparameter BIT_WIDTH_0 = 16; // 1, 2, 4, 8, 16\nparameter BIT_WIDTH_1 = 16; // 1, 2, 4, 8, 16\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 256'h0;\nparameter INIT_RAM_01 = 256'h0;\nparameter INIT_RAM_02 = 256'h0;\nparameter INIT_RAM_03 = 256'h0;\nparameter INIT_RAM_04 = 256'h0;\nparameter INIT_RAM_05 = 256'h0;\nparameter INIT_RAM_06 = 256'h0;\nparameter INIT_RAM_07 = 256'h0;\nparameter INIT_RAM_08 = 256'h0;\nparameter INIT_RAM_09 = 256'h0;\nparameter INIT_RAM_0A = 256'h0;\nparameter INIT_RAM_0B = 256'h0;\nparameter INIT_RAM_0C = 256'h0;\nparameter INIT_RAM_0D = 256'h0;\nparameter INIT_RAM_0E = 256'h0;\nparameter INIT_RAM_0F = 256'h0;\nparameter INIT_RAM_10 = 256'h0;\nparameter INIT_RAM_11 = 256'h0;\nparameter INIT_RAM_12 = 256'h0;\nparameter INIT_RAM_13 = 256'h0;\nparameter INIT_RAM_14 = 256'h0;\nparameter INIT_RAM_15 = 256'h0;\nparameter INIT_RAM_16 = 256'h0;\nparameter INIT_RAM_17 = 256'h0;\nparameter INIT_RAM_18 = 256'h0;\nparameter INIT_RAM_19 = 256'h0;\nparameter INIT_RAM_1A = 256'h0;\nparameter INIT_RAM_1B = 256'h0;\nparameter INIT_RAM_1C = 256'h0;\nparameter INIT_RAM_1D = 256'h0;\nparameter INIT_RAM_1E = 256'h0;\nparameter INIT_RAM_1F = 256'h0;\nparameter INIT_RAM_20 = 256'h0;\nparameter INIT_RAM_21 = 256'h0;\nparameter INIT_RAM_22 = 256'h0;\nparameter INIT_RAM_23 = 256'h0;\nparameter INIT_RAM_24 = 256'h0;\nparameter INIT_RAM_25 = 256'h0;\nparameter INIT_RAM_26 = 256'h0;\nparameter INIT_RAM_27 = 256'h0;\nparameter INIT_RAM_28 = 256'h0;\nparameter INIT_RAM_29 = 256'h0;\nparameter INIT_RAM_2A = 256'h0;\nparameter INIT_RAM_2B = 256'h0;\nparameter INIT_RAM_2C = 256'h0;\nparameter INIT_RAM_2D = 256'h0;\nparameter INIT_RAM_2E = 256'h0;\nparameter INIT_RAM_2F = 256'h0;\nparameter INIT_RAM_30 = 256'h0;\nparameter INIT_RAM_31 = 256'h0;\nparameter INIT_RAM_32 = 256'h0;\nparameter INIT_RAM_33 = 256'h0;\nparameter INIT_RAM_34 = 256'h0;\nparameter INIT_RAM_35 = 256'h0;\nparameter INIT_RAM_36 = 256'h0;\nparameter INIT_RAM_37 = 256'h0;\nparameter INIT_RAM_38 = 256'h0;\nparameter INIT_RAM_39 = 256'h0;\nparameter INIT_RAM_3A = 256'h0;\nparameter INIT_RAM_3B = 256'h0;\nparameter INIT_RAM_3C = 256'h0;\nparameter INIT_RAM_3D = 256'h0;\nparameter INIT_RAM_3E = 256'h0;\nparameter INIT_RAM_3F = 256'h0;\n\noutput [15:0] DOA, DOB;\ninput [15:0] DIA, DIB;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCEA, OCEB;\ninput RESETA, RESETB;\n\nendmodule\n\n(* blackbox *)\nmodule DPX9 (DOA, DOB, DIA, DIB, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCEA, OCEB, RESETA, RESETB);\n\nparameter READ_MODE0 = 1'b0;\nparameter READ_MODE1 = 1'b0;\nparameter WRITE_MODE0 = 2'b00;\nparameter WRITE_MODE1 = 2'b00;\nparameter BIT_WIDTH_0 = 18; // 9, 18\nparameter BIT_WIDTH_1 = 18; // 9, 18\nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\";\nparameter INIT_RAM_00 = 288'h0;\nparameter INIT_RAM_01 = 288'h0;\nparameter INIT_RAM_02 = 288'h0;\nparameter INIT_RAM_03 = 288'h0;\nparameter INIT_RAM_04 = 288'h0;\nparameter INIT_RAM_05 = 288'h0;\nparameter INIT_RAM_06 = 288'h0;\nparameter INIT_RAM_07 = 288'h0;\nparameter INIT_RAM_08 = 288'h0;\nparameter INIT_RAM_09 = 288'h0;\nparameter INIT_RAM_0A = 288'h0;\nparameter INIT_RAM_0B = 288'h0;\nparameter INIT_RAM_0C = 288'h0;\nparameter INIT_RAM_0D = 288'h0;\nparameter INIT_RAM_0E = 288'h0;\nparameter INIT_RAM_0F = 288'h0;\nparameter INIT_RAM_10 = 288'h0;\nparameter INIT_RAM_11 = 288'h0;\nparameter INIT_RAM_12 = 288'h0;\nparameter INIT_RAM_13 = 288'h0;\nparameter INIT_RAM_14 = 288'h0;\nparameter INIT_RAM_15 = 288'h0;\nparameter INIT_RAM_16 = 288'h0;\nparameter INIT_RAM_17 = 288'h0;\nparameter INIT_RAM_18 = 288'h0;\nparameter INIT_RAM_19 = 288'h0;\nparameter INIT_RAM_1A = 288'h0;\nparameter INIT_RAM_1B = 288'h0;\nparameter INIT_RAM_1C = 288'h0;\nparameter INIT_RAM_1D = 288'h0;\nparameter INIT_RAM_1E = 288'h0;\nparameter INIT_RAM_1F = 288'h0;\nparameter INIT_RAM_20 = 288'h0;\nparameter INIT_RAM_21 = 288'h0;\nparameter INIT_RAM_22 = 288'h0;\nparameter INIT_RAM_23 = 288'h0;\nparameter INIT_RAM_24 = 288'h0;\nparameter INIT_RAM_25 = 288'h0;\nparameter INIT_RAM_26 = 288'h0;\nparameter INIT_RAM_27 = 288'h0;\nparameter INIT_RAM_28 = 288'h0;\nparameter INIT_RAM_29 = 288'h0;\nparameter INIT_RAM_2A = 288'h0;\nparameter INIT_RAM_2B = 288'h0;\nparameter INIT_RAM_2C = 288'h0;\nparameter INIT_RAM_2D = 288'h0;\nparameter INIT_RAM_2E = 288'h0;\nparameter INIT_RAM_2F = 288'h0;\nparameter INIT_RAM_30 = 288'h0;\nparameter INIT_RAM_31 = 288'h0;\nparameter INIT_RAM_32 = 288'h0;\nparameter INIT_RAM_33 = 288'h0;\nparameter INIT_RAM_34 = 288'h0;\nparameter INIT_RAM_35 = 288'h0;\nparameter INIT_RAM_36 = 288'h0;\nparameter INIT_RAM_37 = 288'h0;\nparameter INIT_RAM_38 = 288'h0;\nparameter INIT_RAM_39 = 288'h0;\nparameter INIT_RAM_3A = 288'h0;\nparameter INIT_RAM_3B = 288'h0;\nparameter INIT_RAM_3C = 288'h0;\nparameter INIT_RAM_3D = 288'h0;\nparameter INIT_RAM_3E = 288'h0;\nparameter INIT_RAM_3F = 288'h0;\n\noutput [17:0] DOA, DOB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSEL;\ninput [13:0] ADA, ADB;\ninput WREA, WREB;\ninput CLKA, CLKB;\ninput CEA, CEB;\ninput OCEA, OCEB;\ninput RESETA, RESETB;\n\nendmodule\n\n\n(* blackbox *)\nmodule rPLL (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY;\ninput [3:0] DUTYDA;\n\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\n\nparameter FCLKIN = \"100.0\"; // frequency of CLKIN\nparameter DYN_IDIV_SEL= \"false\"; // true:IDSEL, false:IDIV_SEL\nparameter IDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_FBDIV_SEL= \"false\"; // true:FBDSEL, false:FBDIV_SEL\nparameter FBDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_ODIV_SEL= \"false\"; // true:ODSEL, false:ODIV_SEL\nparameter ODIV_SEL = 8; // 2/4/8/16/32/48/64/80/96/112/128\n\nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\"; // true:PSDA or DUTYDA or FDA, false: DA_SEL\nparameter DUTYDA_SEL= \"1000\";\n\nparameter CLKOUT_FT_DIR = 1'b1; // CLKOUT fine tuning direction. 1'b1 only\nparameter CLKOUTP_FT_DIR = 1'b1; // 1'b1 only\nparameter CLKOUT_DLY_STEP = 0; // 0, 1, 2, 4\nparameter CLKOUTP_DLY_STEP = 0; // 0, 1, 2\n\nparameter CLKFB_SEL = \"internal\"; // \"internal\", \"external\"\nparameter CLKOUT_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTP_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTD_BYPASS = \"false\"; // \"true\", \"false\"\nparameter DYN_SDIV_SEL = 2; // 2~128, only even numbers\nparameter CLKOUTD_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter CLKOUTD3_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter DEVICE = \"GW1N-1\"; // \"GW1N-1\", \"GW1N-4\", \"GW1N-9\", \"GW1NR-4\", \"GW1NR-9\", \"GW1N-4B\", \"GW1NR-4B\", \"GW1NS-2\", \"GW1NS-2C\", \"GW1NZ-1\", \"GW1NSR-2\", \"GW1NSR-2C\", \"GW1N-1S\", \"GW1NSE-2C\", \"GW1NRF-4B\", \"GW1N-9C\", \"GW1NR-9C\", \"GW1N-4C\", \"GW1NR-4C\"\n\nendmodule\n\n(* blackbox *)\nmodule PLLVR (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P, VREN);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY;\ninput [3:0] DUTYDA;\ninput VREN;\n\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\n\nparameter FCLKIN = \"100.0\"; // frequency of CLKIN\nparameter DYN_IDIV_SEL= \"false\"; // true:IDSEL, false:IDIV_SEL\nparameter IDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_FBDIV_SEL= \"false\"; // true:FBDSEL, false:FBDIV_SEL\nparameter FBDIV_SEL = 0; // 0:1, 1:2 ... 63:64\nparameter DYN_ODIV_SEL= \"false\"; // true:ODSEL, false:ODIV_SEL\nparameter ODIV_SEL = 8; // 2/4/8/16/32/48/64/80/96/112/128\n\nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\"; // true:PSDA or DUTYDA or FDA, false: DA_SEL\nparameter DUTYDA_SEL= \"1000\";\n\nparameter CLKOUT_FT_DIR = 1'b1; // CLKOUT fine tuning direction. 1'b1 only\nparameter CLKOUTP_FT_DIR = 1'b1; // 1'b1 only\nparameter CLKOUT_DLY_STEP = 0; // 0, 1, 2, 4\nparameter CLKOUTP_DLY_STEP = 0; // 0, 1, 2\n\nparameter CLKFB_SEL = \"internal\"; // \"internal\", \"external\"\nparameter CLKOUT_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTP_BYPASS = \"false\"; // \"true\", \"false\"\nparameter CLKOUTD_BYPASS = \"false\"; // \"true\", \"false\"\nparameter DYN_SDIV_SEL = 2; // 2~128, only even numbers\nparameter CLKOUTD_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter CLKOUTD3_SRC = \"CLKOUT\"; // CLKOUT, CLKOUTP\nparameter DEVICE = \"GW1NS-4\"; // \"GW1NS-4\", \"GW1NS-4C\", \"GW1NSR-4\", \"GW1NSR-4C\", \"GW1NSER-4C\"\n\nendmodule\n\n(* blackbox *)\nmodule OSC(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nparameter DEVICE = \"GW1N-4\";\nendmodule\n\n(* blackbox *)\nmodule OSCZ(OSCOUT, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nendmodule\n\n(* blackbox *)\nmodule OSCF(OSCOUT, OSCOUT30M, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\noutput OSCOUT30M;\n\nparameter FREQ_DIV = 100;\nendmodule\n\n(* blackbox *)\nmodule OSCH(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 96;\nendmodule\n\n(* blackbox *)\nmodule OSCW(OSCOUT);\noutput OSCOUT;\n\nparameter FREQ_DIV = 80;\nendmodule\n\n(* blackbox *)\nmodule OSCO(OSCOUT, OSCEN);\ninput OSCEN;\n\noutput OSCOUT;\n\nparameter FREQ_DIV = 100;\nparameter REGULATOR_EN = 1'b0;\nendmodule\n",
97
97
  "cells_xtra.v": "// Created by cells_xtra.py\n\n\nmodule MUX2_MUX8 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX16 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX2_MUX32 (...);\ninput I0,I1;\ninput S0;\noutput O;\nendmodule\n\n\nmodule MUX4 (...);\ninput I0, I1, I2, I3;\ninput S0, S1;\noutput O;\nendmodule\n\n\nmodule MUX8 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7;\ninput S0, S1, S2;\noutput O;\nendmodule\n\n\nmodule MUX16 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;\ninput S0, S1, S2, S3;\noutput O;\nendmodule\n\nmodule MUX32 (...);\ninput I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31;\ninput S0, S1, S2, S3, S4;\noutput O;\nendmodule\n\nmodule LUT5 (...);\nparameter INIT = 32'h00000000;\ninput I0, I1, I2, I3, I4;\noutput F;\nendmodule\n\n\nmodule LUT6 (...);\nparameter INIT = 64'h0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5;\noutput F;\nendmodule\n\n\nmodule LUT7 (...);\nparameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6;\noutput F;\nendmodule\n\n\nmodule LUT8 (...);\nparameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;\ninput I0, I1, I2, I3, I4, I5, I6, I7;\noutput F;\nendmodule\n\n\nmodule DL (...);\ninput D, G;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLE (...);\ninput D, G, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLC (...);\ninput D, G, CLEAR;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLCE (...);\ninput D, G, CLEAR, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLP (...);\ninput D, G, PRESET;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLPE (...);\ninput D, G, PRESET, CE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLN (...);\ninput D, G;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNE (...);\ninput D, G, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNC (...);\ninput D, G, CLEAR;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNCE (...);\ninput D, G, CLEAR, CE;\noutput Q;\nparameter INIT = 1'b0;\nendmodule\n\n\nmodule DLNP (...);\ninput D, G, PRESET;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule DLNPE (...);\ninput D, G, PRESET, CE;\noutput Q;\nparameter INIT = 1'b1;\nendmodule\n\n\nmodule INV (...);\ninput I;\noutput O;\nendmodule\n\n\nmodule IODELAY (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\noutput DF;\noutput DO;\nendmodule\n\n\nmodule IEM (...);\nparameter WINSIZE = \"SMALL\"; \nparameter GSREN = \"false\"; \nparameter LSREN = \"true\"; \ninput D, CLK, RESET, MCLK;\noutput LAG, LEAD;\nendmodule\n\n\nmodule ROM16 (...);\nparameter INIT_0 = 16'h0000;\ninput [3:0] AD;\noutput DO;\nendmodule\n\n\nmodule ROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule ROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput WRE; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule rSDP (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule rSDPX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSEL;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule rROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [31:0] DO;\nendmodule\n\n\nmodule rROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter BLK_SEL = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\ninput [2:0] BLKSEL;\noutput [35:0] DO;\nendmodule\n\n\nmodule pROM (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 32; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [31:0] DO;\nendmodule\n\n\nmodule pROMX9 (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH = 36; \nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLK, CE;\ninput OCE; \ninput RESET; \ninput [13:0] AD;\noutput [35:0] DO;\nendmodule\n\n\nmodule SDPB (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 32; \nparameter BIT_WIDTH_1 = 32; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [31:0] DI;\ninput [2:0] BLKSELA, BLKSELB;\noutput [31:0] DO;\nendmodule\n\n\nmodule SDPX9B (...);\nparameter READ_MODE = 1'b0; \nparameter BIT_WIDTH_0 = 36; \nparameter BIT_WIDTH_1 = 36; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCE; \ninput RESETA, RESETB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [35:0] DI;\noutput [35:0] DO;\nendmodule\n\n\nmodule DPB (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 16; \nparameter BIT_WIDTH_1 = 16; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [2:0] BLKSELA, BLKSELB;\ninput [15:0] DIA, DIB;\noutput [15:0] DOA, DOB;\nendmodule\n\n\nmodule DPX9B (...);\nparameter READ_MODE0 = 1'b0; \nparameter READ_MODE1 = 1'b0; \nparameter WRITE_MODE0 = 2'b00; \nparameter WRITE_MODE1 = 2'b00; \nparameter BIT_WIDTH_0 = 18; \nparameter BIT_WIDTH_1 = 18; \nparameter BLK_SEL_0 = 3'b000;\nparameter BLK_SEL_1 = 3'b000;\nparameter RESET_MODE = \"SYNC\"; \nparameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; \nparameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\nparameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;\ninput CLKA, CEA, CLKB, CEB;\ninput OCEA, OCEB; \ninput RESETA, RESETB; \ninput WREA, WREB; \ninput [13:0] ADA, ADB;\ninput [17:0] DIA, DIB;\ninput [2:0] BLKSELA, BLKSELB;\noutput [17:0] DOA, DOB;\nendmodule\n\n\nmodule PADD18 (...);\ninput [17:0] A;\ninput [17:0] B;\ninput ASEL;\ninput CE,CLK,RESET;\ninput [17:0] SI,SBI;\noutput [17:0] SO,SBO;\noutput [17:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule PADD9 (...);\ninput [8:0] A;\ninput [8:0] B;\ninput ASEL;\ninput CE,CLK,RESET;\ninput [8:0] SI,SBI;\noutput [8:0] SO,SBO;\noutput [8:0] DOUT;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0; \nparameter ADD_SUB = 1'b0; \nparameter PADD_RESET_MODE = \"SYNC\"; \nparameter BSEL_MODE = 1'b1; \nparameter SOREG = 1'b0;\nendmodule\n\nmodule MULT9X9 (...);\ninput [8:0] A,SIA;\ninput [8:0] B,SIB;\ninput ASIGN,BSIGN;\ninput ASEL,BSEL;\ninput CE;\ninput CLK;\ninput RESET;\noutput [17:0] DOUT;\noutput [8:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0; \nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT18X18 (...);\ninput [17:0] A,SIA;\ninput [17:0] B,SIB;\ninput ASIGN,BSIGN;\ninput ASEL,BSEL;\ninput CE;\ninput CLK;\ninput RESET;\noutput [35:0] DOUT;\noutput [17:0] SOA,SOB;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULT36X36 (...);\ninput [35:0] A;\ninput [35:0] B;\ninput ASIGN,BSIGN;\ninput CE;\ninput CLK;\ninput RESET;\noutput [71:0] DOUT;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter OUT0_REG = 1'b0;\nparameter OUT1_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nendmodule\n\nmodule MULTALU36X18 (...);\ninput [17:0] A;\ninput [35:0] B;\ninput [53:0] C;\ninput ASIGN,BSIGN,ACCLOAD;\ninput CE;\ninput CLK;\ninput RESET;\ninput [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter PIPE_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter MULTALU36X18_MODE = 0; \nparameter C_ADD_SUB = 1'b0; \nendmodule\n\nmodule MULTADDALU18X18 (...);\ninput [17:0] A0;\ninput [17:0] B0;\ninput [17:0] A1;\ninput [17:0] B1;\ninput [53:0] C;\ninput [17:0] SIA, SIB;\ninput [1:0] ASIGN, BSIGN;\ninput [1:0] ASEL, BSEL;\ninput [54:0] CASI;\ninput CE;\ninput CLK;\ninput RESET;\ninput ACCLOAD;\noutput [53:0] DOUT;\noutput [54:0] CASO;\noutput [17:0] SOA, SOB;\nparameter A0REG = 1'b0; \nparameter A1REG = 1'b0;\nparameter B0REG = 1'b0;\nparameter B1REG = 1'b0;\nparameter CREG = 1'b0;\nparameter PIPE0_REG = 1'b0;\nparameter PIPE1_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter ASIGN0_REG = 1'b0;\nparameter ASIGN1_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter BSIGN0_REG = 1'b0;\nparameter BSIGN1_REG = 1'b0;\nparameter SOA_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTADDALU18X18_MODE = 0;\nparameter MULT_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule MULTALU18X18 (...);\ninput [17:0] A, B;\ninput CLK,CE,RESET;\ninput ASIGN, BSIGN;\ninput ACCLOAD,DSIGN;\ninput [53:0] C,D;\ninput [54:0] CASI;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0;\nparameter BREG = 1'b0;\nparameter CREG = 1'b0;\nparameter DREG = 1'b0;\nparameter DSIGN_REG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG0 = 1'b0;\nparameter ACCLOAD_REG1 = 1'b0;\nparameter MULT_RESET_MODE = \"SYNC\"; \nparameter PIPE_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter MULTALU18X18_MODE = 0; \nendmodule\n\nmodule ALU54D (...);\ninput [53:0] A, B;\ninput ASIGN,BSIGN;\ninput ACCLOAD;\ninput [54:0] CASI;\ninput CLK, CE, RESET;\noutput [53:0] DOUT;\noutput [54:0] CASO;\nparameter AREG = 1'b0; \nparameter BREG = 1'b0;\nparameter ASIGN_REG = 1'b0;\nparameter BSIGN_REG = 1'b0;\nparameter ACCLOAD_REG = 1'b0;\nparameter OUT_REG = 1'b0;\nparameter B_ADD_SUB = 1'b0; \nparameter C_ADD_SUB = 1'b0;\nparameter ALUD_MODE = 0;\nparameter ALU_RESET_MODE = \"SYNC\";\nendmodule\n\nmodule BUFG (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule BUFS (...);\noutput O;\ninput I;\nendmodule\n\n\nmodule PLL (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET; \ninput RESET_P; \ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL; \ninput [5:0] IDSEL;\ninput [5:0] ODSEL;\ninput [3:0] PSDA,FDLY; \ninput [3:0] DUTYDA;\noutput CLKOUT;\noutput LOCK;\noutput CLKOUTP;\noutput CLKOUTD;\noutput CLKOUTD3;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"false\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"false\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIV_SEL= \"false\";\nparameter ODIV_SEL = 8; \nparameter PSDA_SEL= \"0000\";\nparameter DYN_DA_EN = \"false\";\nparameter DUTYDA_SEL= \"1000\";\nparameter CLKOUT_FT_DIR = 1'b1; \nparameter CLKOUTP_FT_DIR = 1'b1; \nparameter CLKOUT_DLY_STEP = 0; \nparameter CLKOUTP_DLY_STEP = 0; \nparameter CLKFB_SEL = \"internal\"; \nparameter CLKOUT_BYPASS = \"false\"; \nparameter CLKOUTP_BYPASS = \"false\"; \nparameter CLKOUTD_BYPASS = \"false\"; \nparameter DYN_SDIV_SEL = 2; \nparameter CLKOUTD_SRC = \"CLKOUT\"; \nparameter CLKOUTD3_SRC = \"CLKOUT\"; \nparameter DEVICE = \"GW1N-4\";\nendmodule\n\nmodule TLVDS_IBUF (...);\noutput O;\ninput I, IB;\nendmodule\n\nmodule TLVDS_TBUF (...);\noutput O, OB;\ninput I, OEN;\nendmodule\n\nmodule TLVDS_IOBUF (...);\noutput O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_IBUF (...);\noutput O;\ninput I, IB;\nendmodule\n\nmodule ELVDS_TBUF (...);\noutput O, OB;\ninput I, OEN;\nendmodule\n\nmodule ELVDS_IOBUF (...);\noutput O;\ninout IO, IOB;\ninput I, OEN;\nendmodule\n\nmodule MIPI_IBUF (...);\noutput OH, OL, OB;\ninout IO, IOB;\ninput I, IB;\ninput OEN, OENB;\ninput HSREN;\nendmodule\n\nmodule MIPI_IBUF_HS (...);\noutput OH;\ninput I, IB;\nendmodule\n\nmodule MIPI_IBUF_LP (...);\noutput OL;\noutput OB;\ninput I;\ninput IB;\nendmodule\n\nmodule MIPI_OBUF (...);\noutput O, OB;\ninput I, IB, MODESEL;\nendmodule\n\nmodule MIPI_OBUF_A (...);\noutput O, OB;\ninput I, IB, IL, MODESEL;\nendmodule\n\nmodule I3C_IOBUF (...);\noutput O;\ninout IO;\ninput I, MODESEL;\nendmodule\n\nmodule CLKDIV (...);\ninput HCLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n\nmodule DHCEN (...);\ninput CLKIN,CE;\noutput CLKOUT;\nendmodule\n\nmodule DLL (...);\ninput CLKIN;\ninput STOP;\ninput UPDNCNTL;\ninput RESET;\noutput [7:0]STEP;\noutput LOCK;\nparameter DLL_FORCE = 0;\nparameter CODESCAL=\"000\";\nparameter SCAL_EN=\"true\";\nparameter DIV_SEL = 1'b0; \nendmodule\n\nmodule DLLDLY (...);\ninput CLKIN;\ninput [7:0] DLLSTEP;\ninput DIR,LOADN,MOVE;\noutput CLKOUT;\noutput FLAG;\nparameter DLL_INSEL = 1'b1; \nparameter DLY_SIGN = 1'b0; \nparameter DLY_ADJ = 0; \nendmodule\n\nmodule FLASH96K (...);\ninput [5:0] RA,CA,PA;\ninput [3:0] MODE;\ninput [1:0] SEQ;\ninput ACLK,PW,RESET,PE,OE;\ninput [1:0] RMODE,WMODE;\ninput [1:0] RBYTESEL,WBYTESEL;\ninput [31:0] DIN;\noutput [31:0] DOUT;\nendmodule\n\nmodule FLASH256K (...);\ninput[6:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule FLASH608K (...);\ninput[8:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n \t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\nendmodule\n\nmodule DCS (...);\ninput CLK0, CLK1, CLK2, CLK3, SELFORCE;\ninput [3:0] CLKSEL;\noutput CLKOUT;\nendmodule\n\nmodule DQCE (...);\ninput CLKIN;\ninput CE;\noutput CLKOUT;\nendmodule\n\nmodule FLASH128K (...);\ninput [31:0] DIN;\ninput [14:0] ADDR;\ninput CS,AE,OE;\ninput PCLK;\ninput PROG, SERA, MASE;\ninput NVSTR;\ninput IFREN;\ninput RESETN;\noutput [31:0] DOUT;\noutput TBIT;\nparameter IDLE = 4'd0,\n READ_S1 = 4'd1,\n READ_S2 = 4'd2,\n PROG_S1 = 4'd3,\n PROG_S2 = 4'd4,\n PROG_S3 = 4'd5,\n PROG_S4 = 4'd6,\n SERA_S1 = 4'd7,\n SERA_S2 = 4'd8,\n SERA_S3 = 4'd9,\n SERA_S4 = 4'd10,\n MASE_S1 = 4'd11,\n MASE_S2 = 4'd12,\n MASE_S3 = 4'd13,\n MASE_S4 = 4'd14;\nendmodule\n\nmodule MCU (...);\nendmodule\n\nmodule USB20_PHY (...);\nparameter DATABUS16_8 = 1'b0;\nparameter ADP_PRBEN = 1'b0;\nparameter TEST_MODE = 5'b00000;\nparameter HSDRV1 = 1'b0; \nparameter HSDRV0 = 1'b0; \nparameter CLK_SEL = 1'b0;\nparameter M = 4'b0000; \nparameter N = 6'b101000; \nparameter C = 2'b01; \nparameter FOC_LOCK = 1'b0;\ninput [15:0] DATAIN;\ninput TXVLD;\ninput TXVLDH;\ninput RESET;\ninput SUSPENDM;\ninput [1:0] XCVRSEL;\ninput TERMSEL;\ninput [1:0] OPMODE;\noutput [15:0] DATAOUT;\noutput TXREADY;\noutput RXACTIVE;\noutput RXVLD;\noutput RXVLDH;\noutput CLK; \noutput RXERROR;\ninout DP;\ninout DM;\noutput [1:0] LINESTATE;\ninput IDPULLUP;\ninput DPPD;\ninput DMPD;\ninput CHARGVBUS;\ninput DISCHARGVBUS;\ninput TXBITSTUFFEN;\ninput TXBITSTUFFENH;\ninput TXENN;\ninput TXDAT;\ninput TXSE0;\ninput FSLSSERIAL;\noutput HOSTDIS;\noutput IDDIG;\noutput ADPPRB;\noutput ADPSNS;\noutput SESSVLD;\noutput VBUSVLD;\noutput RXDP;\noutput RXDM;\noutput RXRCV;\noutput LBKERR;\noutput CLKRDY;\ninput INTCLK;\ninout ID;\ninout VBUS;\ninout REXT;\ninput XIN;\ninout XOUT;\ninput\tTEST;\noutput\tCLK480PAD;\ninput SCANCLK; \ninput SCANEN; \ninput SCANMODE; \ninput TRESETN; \ninput SCANIN1; \noutput SCANOUT1; \ninput SCANIN2; \noutput SCANOUT2; \ninput SCANIN3; \noutput SCANOUT3; \ninput SCANIN4; \noutput SCANOUT4; \ninput SCANIN5; \noutput SCANOUT5; \ninput SCANIN6; \noutput SCANOUT6; \nendmodule\n\nmodule ADC (...);\nendmodule\n\nmodule BANDGAP (...);\ninput BGEN;\nendmodule\n\nmodule CLKDIV2 (...);\nparameter GSREN = \"false\"; \ninput HCLKIN, RESETN;\noutput CLKOUT;\nendmodule\n\nmodule DCC (...);\noutput CLKOUT;\ninput CLKIN;\nparameter DCC_EN = 1'b1; \nparameter FCLKIN = 50.0;\nendmodule\n\nmodule DHCENC (...);\ninput CLKIN, CE;\noutput CLKOUT, CLKOUTN;\nendmodule\n\nmodule EMCU (...);\nendmodule\n\nmodule FLASH64K (...);\ninput[4:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput SLEEP;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule FLASH64KZ (...);\ninput[4:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule I3C (...);\nparameter ADDRESS = 7'b0000000;\ninput \tLGYS, CMS, ACS, AAS, STOPS, STRTS;\noutput \tLGYO, CMO, ACO, AAO, SIO, STOPO, STRTO;\ninput \tLGYC, CMC, ACC, AAC, SIC, STOPC, STRTC;\ninput\tSTRTHDS, SENDAHS, SENDALS, ACKHS;\ninput\tACKLS, STOPSUS, STOPHDS, SENDDHS;\ninput\tSENDDLS, RECVDHS, RECVDLS, ADDRS;\noutput\tPARITYERROR;\ninput \t[7:0] DI;\noutput \t[7:0] DOBUF;\noutput \t[7:0] DO;\noutput \t[7:0] STATE;\ninput\tSDAI, SCLI;\noutput\tSDAO, SCLO;\noutput\tSDAOEN, SCLOEN;\noutput\tSDAPULLO, SCLPULLO;\noutput\tSDAPULLOEN, SCLPULLOEN;\ninput \tCE, RESET, CLK;\nendmodule\n\nmodule IODELAYA (...);\nparameter C_STATIC_DLY = 0; \ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\noutput DF;\noutput DO;\nendmodule\n\nmodule IODELAYC (...);\nparameter C_STATIC_DLY = 0; \nparameter DYN_DA_SEL = \"false\"; \nparameter DA_SEL = 2'b00;\ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\ninput [1:0] DASEL;\ninput [1:0] DAADJ;\noutput DF;\noutput DO;\noutput DAO;\nendmodule\n\n\nmodule SPMI (...);\nparameter FUNCTION_CTRL = 7'b0000000; \nparameter MSID_CLKSEL = 7'b0000000;\nparameter RESPOND_DELAY = 4'b0000;\nparameter SCLK_NORMAL_PERIOD = 7'b0000000;\nparameter SCLK_LOW_PERIOD = 7'b0000000;\nparameter CLK_FREQ = 7'b0000000;\nparameter SHUTDOWN_BY_ENABLE = 1'b0; \ninput\tCLKEXT, ENEXT;\ninout\tSDATA, \tSCLK;\ninput \tCLK, CE, RESETN, LOCRESET;\ninput \tPA, SA, CA;\ninput\t[3:0] \tADDRI;\ninput\t[7:0] \tDATAI;\noutput \t[3:0] \tADDRO;\noutput \t[7:0] \tDATAO;\noutput \t[15:0] \tSTATE;\noutput\t[3:0]\tCMD;\nendmodule\n\nmodule IODELAYB (...);\nparameter C_STATIC_DLY = 0; \nparameter DELAY_MUX = 2'b00; \nparameter DA_SEL = 2'b00;\ninput DI;\ninput SDTAP;\ninput SETN;\ninput VALUE;\ninput [1:0] DAADJ;\noutput DF;\noutput DO;\noutput DAO;\nendmodule\n\n\nmodule PLLO (...);\ninput CLKIN;\ninput CLKFB;\ninput RESET;\ninput RESET_P;\ninput RESET_I;\ninput RESET_S;\ninput [5:0] FBDSEL;\ninput [5:0] IDSEL;\ninput [6:0] ODSELA;\ninput [6:0] ODSELB;\ninput [6:0] ODSELC;\ninput [6:0] ODSELD;\ninput [3:0] DTA;\ninput [3:0] DTB;\ninput [4:0] ICPSEL;\ninput [2:0] LPFRES;\ninput [1:0] PSSEL;\ninput PSDIR;\ninput PSPULSE;\ninput ENCLKA;\ninput ENCLKB;\ninput ENCLKC;\ninput ENCLKD;\noutput LOCK;\noutput CLKOUTA;\noutput CLKOUTB;\noutput CLKOUTC;\noutput CLKOUTD;\nparameter FCLKIN = \"100.0\"; \nparameter DYN_IDIV_SEL= \"FALSE\";\nparameter IDIV_SEL = 0; \nparameter DYN_FBDIV_SEL= \"FALSE\";\nparameter FBDIV_SEL = 0; \nparameter DYN_ODIVA_SEL= \"FALSE\";\nparameter ODIVA_SEL = 6; \nparameter DYN_ODIVB_SEL= \"FALSE\";\nparameter ODIVB_SEL = 6; \nparameter DYN_ODIVC_SEL= \"FALSE\";\nparameter ODIVC_SEL = 6; \nparameter DYN_ODIVD_SEL= \"FALSE\";\nparameter ODIVD_SEL = 6; \nparameter CLKOUTA_EN = \"TRUE\";\nparameter CLKOUTB_EN = \"TRUE\";\nparameter CLKOUTC_EN = \"TRUE\";\nparameter CLKOUTD_EN = \"TRUE\";\nparameter DYN_DTA_SEL = \"FALSE\"; \nparameter DYN_DTB_SEL = \"FALSE\"; \nparameter CLKOUTA_DT_DIR = 1'b1; \nparameter CLKOUTB_DT_DIR = 1'b1; \nparameter CLKOUTA_DT_STEP = 0; \nparameter CLKOUTB_DT_STEP = 0; \nparameter CLKA_IN_SEL = 2'b00;\nparameter CLKA_OUT_SEL = 1'b0;\nparameter CLKB_IN_SEL = 2'b00;\nparameter CLKB_OUT_SEL = 1'b0;\nparameter CLKC_IN_SEL = 2'b00;\nparameter CLKC_OUT_SEL = 1'b0;\nparameter CLKD_IN_SEL = 2'b00;\nparameter CLKD_OUT_SEL = 1'b0;\nparameter CLKFB_SEL = \"INTERNAL\"; \nparameter DYN_DPA_EN = \"FALSE\";\nparameter DYN_PSB_SEL = \"FALSE\";\nparameter DYN_PSC_SEL = \"FALSE\";\nparameter DYN_PSD_SEL = \"FALSE\";\nparameter PSB_COARSE = 1;\nparameter PSB_FINE = 0;\nparameter PSC_COARSE = 1;\nparameter PSC_FINE = 0;\nparameter PSD_COARSE = 1;\nparameter PSD_FINE = 0;\nparameter DTMS_ENB = \"FALSE\";\nparameter DTMS_ENC = \"FALSE\";\nparameter DTMS_END = \"FALSE\";\nparameter RESET_I_EN = \"FALSE\";\nparameter RESET_S_EN = \"FALSE\";\nparameter DYN_ICP_SEL= \"FALSE\";\nparameter ICP_SEL = 5'bXXXXX;\nparameter DYN_RES_SEL= \"FALSE\";\nparameter LPR_REF = 7'bXXXXXXX;\nendmodule\n\nmodule DCCG (...);\noutput CLKOUT;\ninput CLKIN;\nparameter DCC_MODE = 2'b00; \nparameter FCLKIN = 50.0;\nendmodule\n\nmodule FLASH96KA (...);\ninput[5:0]XADR;\ninput[5:0]YADR;\ninput XE,YE,SE;\ninput ERASE,PROG,NVSTR;\ninput [31:0] DIN;\ninput SLEEP;\noutput reg [31:0] DOUT;\nparameter IDLE = 4'd0,\n ERA_S1 = 4'd1,\n\t\t ERA_S2 = 4'd2,\n\t\t ERA_S3 = 4'd3,\n\t\t ERA_S4 = 4'd4,\n\t\t ERA_S5 = 4'd5,\n\t\t PRO_S1 = 4'd6,\n\t\t PRO_S2 = 4'd7,\n\t\t PRO_S3 = 4'd8,\n\t\t PRO_S4 = 4'd9,\n\t\t PRO_S5 = 4'd10,\n\t\t RD_S1 = 4'd11,\n\t\t RD_S2 = 4'd12;\t\t \nendmodule\n\nmodule MIPI_DPHY_RX (...);\noutput [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;\noutput D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;\noutput DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P;\noutput DI_LPRXCK_N, DI_LPRXCK_P;\noutput RX_CLK_O; \noutput DESKEW_ERROR; \ninout CK_N, CK_P, RX0_N, RX0_P, RX1_N, RX1_P, RX2_N, RX2_P, RX3_N, RX3_P;\ninput LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3;\ninput HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3;\ninput D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN;\ninput HSRX_EN_CK; \ninput HS_8BIT_MODE; \ninput RX_CLK_1X; \ninput RX_INVERT; \ninput LALIGN_EN; \ninput WALIGN_BY; \ninput DO_LPTX0_N, DO_LPTX0_P, DO_LPTX1_N, DO_LPTX1_P, DO_LPTX2_N, DO_LPTX2_P, DO_LPTX3_N, DO_LPTX3_P;\ninput DO_LPTXCK_N, DO_LPTXCK_P;\ninput LPTX_EN_CK, LPTX_EN_D0, LPTX_EN_D1, LPTX_EN_D2, LPTX_EN_D3;\ninput BYTE_LENDIAN; \ninput HSRX_STOP; \ninput LPRX_ULP_LN0, LPRX_ULP_LN1, LPRX_ULP_LN2, LPRX_ULP_LN3, LPRX_ULP_CK;\ninput PWRON; \ninput RESET; \ninput [2:0] DESKEW_LNSEL; \ninput [7:0] DESKEW_MTH; \ninput [6:0] DESKEW_OWVAL; \ninput DESKEW_REQ; \ninput DRST_N; \ninput ONE_BYTE0_MATCH; \ninput WORD_LENDIAN; \ninput [2:0] FIFO_RD_STD; \nparameter ALIGN_BYTE = 8'b10111000;\nparameter MIPI_LANE0_EN = 1'b0;\nparameter MIPI_LANE1_EN = 1'b0;\nparameter MIPI_LANE2_EN = 1'b0;\nparameter MIPI_LANE3_EN = 1'b0;\nparameter MIPI_CK_EN = 1'b1;\nparameter SYNC_CLK_SEL = 1'b1;\nendmodule\n\nmodule CLKDIVG (...);\ninput CLKIN;\ninput RESETN;\ninput CALIB;\noutput CLKOUT;\nparameter DIV_MODE = \"2\"; \nparameter GSREN = \"false\"; \nendmodule\n",
@@ -132,7 +132,7 @@ export const filesystem = {
132
132
  "cxxrtl_capi_vcd.cc": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl/capi/cxxrtl_capi_vcd.h`.\n\n#include <cxxrtl/capi/cxxrtl_capi_vcd.h>\n#include <cxxrtl/cxxrtl_vcd.h>\n\nextern const cxxrtl::debug_items &cxxrtl_debug_items_from_handle(cxxrtl_handle handle);\n\nstruct _cxxrtl_vcd {\n\tcxxrtl::vcd_writer writer;\n\tbool flush = false;\n};\n\ncxxrtl_vcd cxxrtl_vcd_create() {\n\treturn new _cxxrtl_vcd;\n}\n\nvoid cxxrtl_vcd_destroy(cxxrtl_vcd vcd) {\n\tdelete vcd;\n}\n\nvoid cxxrtl_vcd_timescale(cxxrtl_vcd vcd, int number, const char *unit) {\n\tvcd->writer.timescale(number, unit);\n}\n\nvoid cxxrtl_vcd_add(cxxrtl_vcd vcd, const char *name, cxxrtl_object *object) {\n\t// Note the copy. We don't know whether `object` came from a design (in which case it is\n\t// an instance of `debug_item`), or from user code (in which case it is an instance of\n\t// `cxxrtl_object`), so casting the pointer wouldn't be safe.\n\tvcd->writer.add(name, cxxrtl::debug_item(*object));\n}\n\nvoid cxxrtl_vcd_add_from(cxxrtl_vcd vcd, cxxrtl_handle handle) {\n\tvcd->writer.add(cxxrtl_debug_items_from_handle(handle));\n}\n\nvoid cxxrtl_vcd_add_from_if(cxxrtl_vcd vcd, cxxrtl_handle handle, void *data,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tint (*filter)(void *data, const char *name,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t const cxxrtl_object *object)) {\n\tvcd->writer.add(cxxrtl_debug_items_from_handle(handle),\n\t\t[=](const std::string &name, const cxxrtl::debug_item &item) {\n\t\t\treturn filter(data, name.c_str(), static_cast<const cxxrtl_object*>(&item));\n\t\t});\n}\n\nvoid cxxrtl_vcd_add_from_without_memories(cxxrtl_vcd vcd, cxxrtl_handle handle) {\n\tvcd->writer.add_without_memories(cxxrtl_debug_items_from_handle(handle));\n}\n\nvoid cxxrtl_vcd_sample(cxxrtl_vcd vcd, uint64_t time) {\n\tif (vcd->flush) {\n\t\tvcd->writer.buffer.clear();\n\t\tvcd->flush = false;\n\t}\n\tvcd->writer.sample(time);\n}\n\nvoid cxxrtl_vcd_read(cxxrtl_vcd vcd, const char **data, size_t *size) {\n\tif (vcd->flush) {\n\t\tvcd->writer.buffer.clear();\n\t\tvcd->flush = false;\n\t}\n\t*data = vcd->writer.buffer.c_str();\n\t*size = vcd->writer.buffer.size();\n\tvcd->flush = true;\n}\n",
133
133
  "cxxrtl_capi_vcd.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CXXRTL_CAPI_VCD_H\n#define CXXRTL_CAPI_VCD_H\n\n// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_vcd_capi.cc`.\n//\n// The CXXRTL C API for VCD writing makes it possible to insert virtual probes into designs and\n// dump waveforms to Value Change Dump files.\n\n#include <stddef.h>\n#include <stdint.h>\n\n#include <cxxrtl/capi/cxxrtl_capi.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n// Opaque reference to a VCD writer.\ntypedef struct _cxxrtl_vcd *cxxrtl_vcd;\n\n// Create a VCD writer.\ncxxrtl_vcd cxxrtl_vcd_create();\n\n// Release all resources used by a VCD writer.\nvoid cxxrtl_vcd_destroy(cxxrtl_vcd vcd);\n\n// Set VCD timescale.\n//\n// The `number` must be 1, 10, or 100, and the `unit` must be one of `\"s\"`, `\"ms\"`, `\"us\"`, `\"ns\"`,\n// `\"ps\"`, or `\"fs\"`.\n//\n// Timescale can only be set before the first call to `cxxrtl_vcd_sample`.\nvoid cxxrtl_vcd_timescale(cxxrtl_vcd vcd, int number, const char *unit);\n\n// Schedule a specific CXXRTL object to be sampled.\n//\n// The `name` is a full hierarchical name as described for `cxxrtl_get`; it does not need to match\n// the original name of `object`, if any. The `object` must outlive the VCD writer, but there are\n// no other requirements; if desired, it can be provided by user code, rather than come from\n// a design.\n//\n// Objects can only be scheduled before the first call to `cxxrtl_vcd_sample`.\nvoid cxxrtl_vcd_add(cxxrtl_vcd vcd, const char *name, struct cxxrtl_object *object);\n\n// Schedule all CXXRTL objects in a simulation.\n//\n// The design `handle` must outlive the VCD writer.\n//\n// Objects can only be scheduled before the first call to `cxxrtl_vcd_sample`.\nvoid cxxrtl_vcd_add_from(cxxrtl_vcd vcd, cxxrtl_handle handle);\n\n// Schedule CXXRTL objects in a simulation that match a given predicate.\n//\n// For every object in the simulation, `filter` is called with the provided `data`, the full\n// hierarchical name of the object (see `cxxrtl_get` for details), and the object description.\n// The object will be sampled if the predicate returns a non-zero value.\n//\n// Objects can only be scheduled before the first call to `cxxrtl_vcd_sample`.\nvoid cxxrtl_vcd_add_from_if(cxxrtl_vcd vcd, cxxrtl_handle handle, void *data,\n int (*filter)(void *data, const char *name,\n const struct cxxrtl_object *object));\n\n// Schedule all CXXRTL objects in a simulation except for memories.\n//\n// The design `handle` must outlive the VCD writer.\n//\n// Objects can only be scheduled before the first call to `cxxrtl_vcd_sample`.\nvoid cxxrtl_vcd_add_from_without_memories(cxxrtl_vcd vcd, cxxrtl_handle handle);\n\n// Sample all scheduled objects.\n//\n// First, `time` is written to the internal buffer. Second, the values of every signal changed since\n// the previous call to `cxxrtl_vcd_sample` (all values if this is the first call) are written to\n// the internal buffer. The contents of the buffer can be retrieved with `cxxrtl_vcd_read`.\nvoid cxxrtl_vcd_sample(cxxrtl_vcd vcd, uint64_t time);\n\n// Retrieve buffered VCD data.\n//\n// The pointer to the start of the next chunk of VCD data is assigned to `*data`, and the length\n// of that chunk is assigned to `*size`. The pointer to the data is valid until the next call to\n// `cxxrtl_vcd_sample` or `cxxrtl_vcd_read`. Once all of the buffered data has been retrieved,\n// this function will always return zero sized chunks.\nvoid cxxrtl_vcd_read(cxxrtl_vcd vcd, const char **data, size_t *size);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n",
134
134
  },
135
- "cxxrtl.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2019-2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// This file is included by the designs generated with `write_cxxrtl`. It is not used in Yosys itself.\n//\n// The CXXRTL support library implements compile time specialized arbitrary width arithmetics, as well as provides\n// composite lvalues made out of bit slices and concatenations of lvalues. This allows the `write_cxxrtl` pass\n// to perform a straightforward translation of RTLIL structures to readable C++, relying on the C++ compiler\n// to unwrap the abstraction and generate efficient code.\n\n#ifndef CXXRTL_H\n#define CXXRTL_H\n\n#include <cstddef>\n#include <cstdint>\n#include <cstring>\n#include <cassert>\n#include <limits>\n#include <type_traits>\n#include <tuple>\n#include <vector>\n#include <map>\n#include <algorithm>\n#include <memory>\n#include <functional>\n#include <sstream>\n\n// `cxxrtl::debug_item` has to inherit from `cxxrtl_object` to satisfy strict aliasing requirements.\n#include <cxxrtl/capi/cxxrtl_capi.h>\n\n#ifndef __has_attribute\n#\tdefine __has_attribute(x) 0\n#endif\n\n// CXXRTL essentially uses the C++ compiler as a hygienic macro engine that feeds an instruction selector.\n// It generates a lot of specialized template functions with relatively large bodies that, when inlined\n// into the caller and (for those with loops) unrolled, often expose many new optimization opportunities.\n// Because of this, most of the CXXRTL runtime must be always inlined for best performance.\n#if __has_attribute(always_inline)\n#define CXXRTL_ALWAYS_INLINE inline __attribute__((__always_inline__))\n#else\n#define CXXRTL_ALWAYS_INLINE inline\n#endif\n// Conversely, some functions in the generated code are extremely large yet very cold, with both of these\n// properties being extreme enough to confuse C++ compilers into spending pathological amounts of time\n// on a futile (the code becomes worse) attempt to optimize the least important parts of code.\n#if __has_attribute(optnone)\n#define CXXRTL_EXTREMELY_COLD __attribute__((__optnone__))\n#elif __has_attribute(optimize)\n#define CXXRTL_EXTREMELY_COLD __attribute__((__optimize__(0)))\n#else\n#define CXXRTL_EXTREMELY_COLD\n#endif\n\n// CXXRTL uses assert() to check for C++ contract violations (which may result in e.g. undefined behavior\n// of the simulation code itself), and CXXRTL_ASSERT to check for RTL contract violations (which may at\n// most result in undefined simulation results).\n//\n// Though by default, CXXRTL_ASSERT() expands to assert(), it may be overridden e.g. when integrating\n// the simulation into another process that should survive violating RTL contracts.\n#ifndef CXXRTL_ASSERT\n#ifndef CXXRTL_NDEBUG\n#define CXXRTL_ASSERT(x) assert(x)\n#else\n#define CXXRTL_ASSERT(x)\n#endif\n#endif\n\nnamespace cxxrtl {\n\n// All arbitrary-width values in CXXRTL are backed by arrays of unsigned integers called chunks. The chunk size\n// is the same regardless of the value width to simplify manipulating values via FFI interfaces, e.g. driving\n// and introspecting the simulation in Python.\n//\n// It is practical to use chunk sizes between 32 bits and platform register size because when arithmetics on\n// narrower integer types is legalized by the C++ compiler, it inserts code to clear the high bits of the register.\n// However, (a) most of our operations do not change those bits in the first place because of invariants that are\n// invisible to the compiler, (b) we often operate on non-power-of-2 values and have to clear the high bits anyway.\n// Therefore, using relatively wide chunks and clearing the high bits explicitly and only when we know they may be\n// clobbered results in simpler generated code.\ntypedef uint32_t chunk_t;\ntypedef uint64_t wide_chunk_t;\n\ntemplate<typename T>\nstruct chunk_traits {\n\tstatic_assert(std::is_integral<T>::value && std::is_unsigned<T>::value,\n\t \"chunk type must be an unsigned integral type\");\n\tusing type = T;\n\tstatic constexpr size_t bits = std::numeric_limits<T>::digits;\n\tstatic constexpr T mask = std::numeric_limits<T>::max();\n};\n\ntemplate<class T>\nstruct expr_base;\n\ntemplate<size_t Bits>\nstruct value : public expr_base<value<Bits>> {\n\tstatic constexpr size_t bits = Bits;\n\n\tusing chunk = chunk_traits<chunk_t>;\n\tstatic constexpr chunk::type msb_mask = (Bits % chunk::bits == 0) ? chunk::mask\n\t\t: chunk::mask >> (chunk::bits - (Bits % chunk::bits));\n\n\tstatic constexpr size_t chunks = (Bits + chunk::bits - 1) / chunk::bits;\n\tchunk::type data[chunks] = {};\n\n\tvalue() = default;\n\ttemplate<typename... Init>\n\texplicit constexpr value(Init ...init) : data{init...} {}\n\n\tvalue(const value<Bits> &) = default;\n\tvalue<Bits> &operator=(const value<Bits> &) = default;\n\n\tvalue(value<Bits> &&) = default;\n\tvalue<Bits> &operator=(value<Bits> &&) = default;\n\n\t// A (no-op) helper that forces the cast to value<>.\n\tCXXRTL_ALWAYS_INLINE\n\tconst value<Bits> &val() const {\n\t\treturn *this;\n\t}\n\n\tstd::string str() const {\n\t\tstd::stringstream ss;\n\t\tss << *this;\n\t\treturn ss.str();\n\t}\n\n\t// Conversion operations.\n\t//\n\t// These functions ensure that a conversion is never out of range, and should be always used, if at all\n\t// possible, instead of direct manipulation of the `data` member. For very large types, .slice() and\n\t// .concat() can be used to split them into more manageable parts.\n\ttemplate<class IntegerT, typename std::enable_if<!std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tIntegerT get() const {\n\t\tstatic_assert(std::numeric_limits<IntegerT>::is_integer && !std::numeric_limits<IntegerT>::is_signed,\n\t\t \"get<T>() requires T to be an unsigned integral type\");\n\t\tstatic_assert(std::numeric_limits<IntegerT>::digits >= Bits,\n\t\t \"get<T>() requires T to be at least as wide as the value is\");\n\t\tIntegerT result = 0;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult |= IntegerT(data[n]) << (n * chunk::bits);\n\t\treturn result;\n\t}\n\n\ttemplate<class IntegerT, typename std::enable_if<std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tIntegerT get() const {\n\t\tauto unsigned_result = get<typename std::make_unsigned<IntegerT>::type>();\n\t\tIntegerT result;\n\t\tmemcpy(&result, &unsigned_result, sizeof(IntegerT));\n\t\treturn result;\n\t}\n\n\ttemplate<class IntegerT, typename std::enable_if<!std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tvoid set(IntegerT value) {\n\t\tstatic_assert(std::numeric_limits<IntegerT>::is_integer && !std::numeric_limits<IntegerT>::is_signed,\n\t\t \"set<T>() requires T to be an unsigned integral type\");\n\t\tstatic_assert(std::numeric_limits<IntegerT>::digits >= Bits,\n\t\t \"set<T>() requires the value to be at least as wide as T is\");\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tdata[n] = (value >> (n * chunk::bits)) & chunk::mask;\n\t}\n\n\ttemplate<class IntegerT, typename std::enable_if<std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tvoid set(IntegerT value) {\n\t\ttypename std::make_unsigned<IntegerT>::type unsigned_value;\n\t\tmemcpy(&unsigned_value, &value, sizeof(IntegerT));\n\t\tset(unsigned_value);\n\t}\n\n\t// Operations with compile-time parameters.\n\t//\n\t// These operations are used to implement slicing, concatenation, and blitting.\n\t// The trunc, zext and sext operations add or remove most significant bits (i.e. on the left);\n\t// the rtrunc and rzext operations add or remove least significant bits (i.e. on the right).\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> trunc() const {\n\t\tstatic_assert(NewBits <= Bits, \"trunc() may not increase width\");\n\t\tvalue<NewBits> result;\n\t\tfor (size_t n = 0; n < result.chunks; n++)\n\t\t\tresult.data[n] = data[n];\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> zext() const {\n\t\tstatic_assert(NewBits >= Bits, \"zext() may not decrease width\");\n\t\tvalue<NewBits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n];\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> sext() const {\n\t\tstatic_assert(NewBits >= Bits, \"sext() may not decrease width\");\n\t\tvalue<NewBits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n];\n\t\tif (is_neg()) {\n\t\t\tresult.data[chunks - 1] |= ~msb_mask;\n\t\t\tfor (size_t n = chunks; n < result.chunks; n++)\n\t\t\t\tresult.data[n] = chunk::mask;\n\t\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\t}\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> rtrunc() const {\n\t\tstatic_assert(NewBits <= Bits, \"rtrunc() may not increase width\");\n\t\tvalue<NewBits> result;\n\t\tconstexpr size_t shift_chunks = (Bits - NewBits) / chunk::bits;\n\t\tconstexpr size_t shift_bits = (Bits - NewBits) % chunk::bits;\n\t\tchunk::type carry = 0;\n\t\tif (shift_chunks + result.chunks < chunks) {\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[shift_chunks + result.chunks] << (chunk::bits - shift_bits);\n\t\t}\n\t\tfor (size_t n = result.chunks; n > 0; n--) {\n\t\t\tresult.data[n - 1] = carry | (data[shift_chunks + n - 1] >> shift_bits);\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[shift_chunks + n - 1] << (chunk::bits - shift_bits);\n\t\t}\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> rzext() const {\n\t\tstatic_assert(NewBits >= Bits, \"rzext() may not decrease width\");\n\t\tvalue<NewBits> result;\n\t\tconstexpr size_t shift_chunks = (NewBits - Bits) / chunk::bits;\n\t\tconstexpr size_t shift_bits = (NewBits - Bits) % chunk::bits;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tresult.data[shift_chunks + n] = (data[n] << shift_bits) | carry;\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[n] >> (chunk::bits - shift_bits);\n\t\t}\n\t\tif (shift_chunks + chunks < result.chunks)\n\t\t\tresult.data[shift_chunks + chunks] = carry;\n\t\treturn result;\n\t}\n\n\t// Bit blit operation, i.e. a partial read-modify-write.\n\ttemplate<size_t Stop, size_t Start>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<Bits> blit(const value<Stop - Start + 1> &source) const {\n\t\tstatic_assert(Stop >= Start, \"blit() may not reverse bit order\");\n\t\tconstexpr chunk::type start_mask = ~(chunk::mask << (Start % chunk::bits));\n\t\tconstexpr chunk::type stop_mask = (Stop % chunk::bits + 1 == chunk::bits) ? 0\n\t\t\t: (chunk::mask << (Stop % chunk::bits + 1));\n\t\tvalue<Bits> masked = *this;\n\t\tif (Start / chunk::bits == Stop / chunk::bits) {\n\t\t\tmasked.data[Start / chunk::bits] &= stop_mask | start_mask;\n\t\t} else {\n\t\t\tmasked.data[Start / chunk::bits] &= start_mask;\n\t\t\tfor (size_t n = Start / chunk::bits + 1; n < Stop / chunk::bits; n++)\n\t\t\t\tmasked.data[n] = 0;\n\t\t\tmasked.data[Stop / chunk::bits] &= stop_mask;\n\t\t}\n\t\tvalue<Bits> shifted = source\n\t\t\t.template rzext<Stop + 1>()\n\t\t\t.template zext<Bits>();\n\t\treturn masked.bit_or(shifted);\n\t}\n\n\t// Helpers for selecting extending or truncating operation depending on whether the result is wider or narrower\n\t// than the operand. In C++17 these can be replaced with `if constexpr`.\n\ttemplate<size_t NewBits, typename = void>\n\tstruct zext_cast {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template zext<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits>\n\tstruct zext_cast<NewBits, typename std::enable_if<(NewBits < Bits)>::type> {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template trunc<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits, typename = void>\n\tstruct sext_cast {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template sext<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits>\n\tstruct sext_cast<NewBits, typename std::enable_if<(NewBits < Bits)>::type> {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template trunc<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> zcast() const {\n\t\treturn zext_cast<NewBits>()(*this);\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> scast() const {\n\t\treturn sext_cast<NewBits>()(*this);\n\t}\n\n\t// Bit replication is far more efficient than the equivalent concatenation.\n\ttemplate<size_t Count>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<Bits * Count> repeat() const {\n\t\tstatic_assert(Bits == 1, \"repeat() is implemented only for 1-bit values\");\n\t\treturn *this ? value<Bits * Count>().bit_not() : value<Bits * Count>();\n\t}\n\n\t// Operations with run-time parameters (offsets, amounts, etc).\n\t//\n\t// These operations are used for computations.\n\tbool bit(size_t offset) const {\n\t\treturn data[offset / chunk::bits] & (1 << (offset % chunk::bits));\n\t}\n\n\tvoid set_bit(size_t offset, bool value = true) {\n\t\tsize_t offset_chunks = offset / chunk::bits;\n\t\tsize_t offset_bits = offset % chunk::bits;\n\t\tdata[offset_chunks] &= ~(1 << offset_bits);\n\t\tdata[offset_chunks] |= value ? 1 << offset_bits : 0;\n\t}\n\n\texplicit operator bool() const {\n\t\treturn !is_zero();\n\t}\n\n\tbool is_zero() const {\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tif (data[n] != 0)\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool is_neg() const {\n\t\treturn data[chunks - 1] & (1 << ((Bits - 1) % chunk::bits));\n\t}\n\n\tbool operator ==(const value<Bits> &other) const {\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tif (data[n] != other.data[n])\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool operator !=(const value<Bits> &other) const {\n\t\treturn !(*this == other);\n\t}\n\n\tvalue<Bits> bit_not() const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = ~data[n];\n\t\tresult.data[chunks - 1] &= msb_mask;\n\t\treturn result;\n\t}\n\n\tvalue<Bits> bit_and(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n] & other.data[n];\n\t\treturn result;\n\t}\n\n\tvalue<Bits> bit_or(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n] | other.data[n];\n\t\treturn result;\n\t}\n\n\tvalue<Bits> bit_xor(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n] ^ other.data[n];\n\t\treturn result;\n\t}\n\n\tvalue<Bits> update(const value<Bits> &val, const value<Bits> &mask) const {\n\t\treturn bit_and(mask.bit_not()).bit_or(val.bit_and(mask));\n\t}\n\n\ttemplate<size_t AmountBits>\n\tvalue<Bits> shl(const value<AmountBits> &amount) const {\n\t\t// Ensure our early return is correct by prohibiting values larger than 4 Gbit.\n\t\tstatic_assert(Bits <= chunk::mask, \"shl() of unreasonably large values is not supported\");\n\t\t// Detect shifts definitely large than Bits early.\n\t\tfor (size_t n = 1; n < amount.chunks; n++)\n\t\t\tif (amount.data[n] != 0)\n\t\t\t\treturn {};\n\t\t// Past this point we can use the least significant chunk as the shift size.\n\t\tsize_t shift_chunks = amount.data[0] / chunk::bits;\n\t\tsize_t shift_bits = amount.data[0] % chunk::bits;\n\t\tif (shift_chunks >= chunks)\n\t\t\treturn {};\n\t\tvalue<Bits> result;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks - shift_chunks; n++) {\n\t\t\tresult.data[shift_chunks + n] = (data[n] << shift_bits) | carry;\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[n] >> (chunk::bits - shift_bits);\n\t\t}\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\ttemplate<size_t AmountBits, bool Signed = false>\n\tvalue<Bits> shr(const value<AmountBits> &amount) const {\n\t\t// Ensure our early return is correct by prohibiting values larger than 4 Gbit.\n\t\tstatic_assert(Bits <= chunk::mask, \"shr() of unreasonably large values is not supported\");\n\t\t// Detect shifts definitely large than Bits early.\n\t\tfor (size_t n = 1; n < amount.chunks; n++)\n\t\t\tif (amount.data[n] != 0)\n\t\t\t\treturn (Signed && is_neg()) ? value<Bits>().bit_not() : value<Bits>();\n\t\t// Past this point we can use the least significant chunk as the shift size.\n\t\tsize_t shift_chunks = amount.data[0] / chunk::bits;\n\t\tsize_t shift_bits = amount.data[0] % chunk::bits;\n\t\tif (shift_chunks >= chunks)\n\t\t\treturn (Signed && is_neg()) ? value<Bits>().bit_not() : value<Bits>();\n\t\tvalue<Bits> result;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks - shift_chunks; n++) {\n\t\t\tresult.data[chunks - shift_chunks - 1 - n] = carry | (data[chunks - 1 - n] >> shift_bits);\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[chunks - 1 - n] << (chunk::bits - shift_bits);\n\t\t}\n\t\tif (Signed && is_neg()) {\n\t\t\tsize_t top_chunk_idx = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) / chunk::bits;\n\t\t\tsize_t top_chunk_bits = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) % chunk::bits;\n\t\t\tfor (size_t n = top_chunk_idx + 1; n < chunks; n++)\n\t\t\t\tresult.data[n] = chunk::mask;\n\t\t\tif (amount.data[0] != 0)\n\t\t\t\tresult.data[top_chunk_idx] |= chunk::mask << top_chunk_bits;\n\t\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\t}\n\t\treturn result;\n\t}\n\n\ttemplate<size_t AmountBits>\n\tvalue<Bits> sshr(const value<AmountBits> &amount) const {\n\t\treturn shr<AmountBits, /*Signed=*/true>(amount);\n\t}\n\n\ttemplate<size_t ResultBits, size_t SelBits>\n\tvalue<ResultBits> bmux(const value<SelBits> &sel) const {\n\t\tstatic_assert(ResultBits << SelBits == Bits, \"invalid sizes used in bmux()\");\n\t\tsize_t amount = sel.data[0] * ResultBits;\n\t\tsize_t shift_chunks = amount / chunk::bits;\n\t\tsize_t shift_bits = amount % chunk::bits;\n\t\tvalue<ResultBits> result;\n\t\tchunk::type carry = 0;\n\t\tif (ResultBits % chunk::bits + shift_bits > chunk::bits)\n\t\t\tcarry = data[result.chunks + shift_chunks] << (chunk::bits - shift_bits);\n\t\tfor (size_t n = 0; n < result.chunks; n++) {\n\t\t\tresult.data[result.chunks - 1 - n] = carry | (data[result.chunks + shift_chunks - 1 - n] >> shift_bits);\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[result.chunks + shift_chunks - 1 - n] << (chunk::bits - shift_bits);\n\t\t}\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\ttemplate<size_t ResultBits, size_t SelBits>\n\tvalue<ResultBits> demux(const value<SelBits> &sel) const {\n\t\tstatic_assert(Bits << SelBits == ResultBits, \"invalid sizes used in demux()\");\n\t\tsize_t amount = sel.data[0] * Bits;\n\t\tsize_t shift_chunks = amount / chunk::bits;\n\t\tsize_t shift_bits = amount % chunk::bits;\n\t\tvalue<ResultBits> result;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tresult.data[shift_chunks + n] = (data[n] << shift_bits) | carry;\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[n] >> (chunk::bits - shift_bits);\n\t\t}\n\t\tif (Bits % chunk::bits + shift_bits > chunk::bits)\n\t\t\tresult.data[shift_chunks + chunks] = carry;\n\t\treturn result;\n\t}\n\n\tsize_t ctpop() const {\n\t\tsize_t count = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\t// This loop implements the population count idiom as recognized by LLVM and GCC.\n\t\t\tfor (chunk::type x = data[n]; x != 0; count++)\n\t\t\t\tx = x & (x - 1);\n\t\t}\n\t\treturn count;\n\t}\n\n\tsize_t ctlz() const {\n\t\tsize_t count = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tchunk::type x = data[chunks - 1 - n];\n\t\t\t// First add to `count` as if the chunk is zero\n\t\t\tconstexpr size_t msb_chunk_bits = Bits % chunk::bits != 0 ? Bits % chunk::bits : chunk::bits;\n\t\t\tcount += (n == 0 ? msb_chunk_bits : chunk::bits);\n\t\t\t// If the chunk isn't zero, correct the `count` value and return\n\t\t\tif (x != 0) {\n\t\t\t\tfor (; x != 0; count--)\n\t\t\t\t\tx >>= 1;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\treturn count;\n\t}\n\n\ttemplate<bool Invert, bool CarryIn>\n\tstd::pair<value<Bits>, bool /*CarryOut*/> alu(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tbool carry = CarryIn;\n\t\tfor (size_t n = 0; n < result.chunks; n++) {\n\t\t\tresult.data[n] = data[n] + (Invert ? ~other.data[n] : other.data[n]) + carry;\n\t\t\tif (result.chunks - 1 == n)\n\t\t\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\t\tcarry = (result.data[n] < data[n]) ||\n\t\t\t (result.data[n] == data[n] && carry);\n\t\t}\n\t\treturn {result, carry};\n\t}\n\n\tvalue<Bits> add(const value<Bits> &other) const {\n\t\treturn alu</*Invert=*/false, /*CarryIn=*/false>(other).first;\n\t}\n\n\tvalue<Bits> sub(const value<Bits> &other) const {\n\t\treturn alu</*Invert=*/true, /*CarryIn=*/true>(other).first;\n\t}\n\n\tvalue<Bits> neg() const {\n\t\treturn value<Bits> { 0u }.sub(*this);\n\t}\n\n\tbool ucmp(const value<Bits> &other) const {\n\t\tbool carry;\n\t\tstd::tie(std::ignore, carry) = alu</*Invert=*/true, /*CarryIn=*/true>(other);\n\t\treturn !carry; // a.ucmp(b) ≡ a u< b\n\t}\n\n\tbool scmp(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tbool carry;\n\t\tstd::tie(result, carry) = alu</*Invert=*/true, /*CarryIn=*/true>(other);\n\t\tbool overflow = (is_neg() == !other.is_neg()) && (is_neg() != result.is_neg());\n\t\treturn result.is_neg() ^ overflow; // a.scmp(b) ≡ a s< b\n\t}\n\n\ttemplate<size_t ResultBits>\n\tvalue<ResultBits> mul(const value<Bits> &other) const {\n\t\tvalue<ResultBits> result;\n\t\twide_chunk_t wide_result[result.chunks + 1] = {};\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tfor (size_t m = 0; m < chunks && n + m < result.chunks; m++) {\n\t\t\t\twide_result[n + m] += wide_chunk_t(data[n]) * wide_chunk_t(other.data[m]);\n\t\t\t\twide_result[n + m + 1] += wide_result[n + m] >> chunk::bits;\n\t\t\t\twide_result[n + m] &= chunk::mask;\n\t\t\t}\n\t\t}\n\t\tfor (size_t n = 0; n < result.chunks; n++) {\n\t\t\tresult.data[n] = wide_result[n];\n\t\t}\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\tstd::pair<value<Bits>, value<Bits>> udivmod(value<Bits> divisor) const {\n\t\tvalue<Bits> quotient;\n\t\tvalue<Bits> dividend = *this;\n\t\tif (dividend.ucmp(divisor))\n\t\t\treturn {/*quotient=*/value<Bits>{0u}, /*remainder=*/dividend};\n\t\tint64_t divisor_shift = divisor.ctlz() - dividend.ctlz();\n\t\tassert(divisor_shift >= 0);\n\t\tdivisor = divisor.shl(value<Bits>{(chunk::type) divisor_shift});\n\t\tfor (size_t step = 0; step <= divisor_shift; step++) {\n\t\t\tquotient = quotient.shl(value<Bits>{1u});\n\t\t\tif (!dividend.ucmp(divisor)) {\n\t\t\t\tdividend = dividend.sub(divisor);\n\t\t\t\tquotient.set_bit(0, true);\n\t\t\t}\n\t\t\tdivisor = divisor.shr(value<Bits>{1u});\n\t\t}\n\t\treturn {quotient, /*remainder=*/dividend};\n\t}\n\n\tstd::pair<value<Bits>, value<Bits>> sdivmod(const value<Bits> &other) const {\n\t\tvalue<Bits + 1> quotient;\n\t\tvalue<Bits + 1> remainder;\n\t\tvalue<Bits + 1> dividend = sext<Bits + 1>();\n\t\tvalue<Bits + 1> divisor = other.template sext<Bits + 1>();\n\t\tif (dividend.is_neg()) dividend = dividend.neg();\n\t\tif (divisor.is_neg()) divisor = divisor.neg();\n\t\tstd::tie(quotient, remainder) = dividend.udivmod(divisor);\n\t\tif (dividend.is_neg() != divisor.is_neg()) quotient = quotient.neg();\n\t\tif (dividend.is_neg()) remainder = remainder.neg();\n\t\treturn {quotient.template trunc<Bits>(), remainder.template trunc<Bits>()};\n\t}\n};\n\n// Expression template for a slice, usable as lvalue or rvalue, and composable with other expression templates here.\ntemplate<class T, size_t Stop, size_t Start>\nstruct slice_expr : public expr_base<slice_expr<T, Stop, Start>> {\n\tstatic_assert(Stop >= Start, \"slice_expr() may not reverse bit order\");\n\tstatic_assert(Start < T::bits && Stop < T::bits, \"slice_expr() must be within bounds\");\n\tstatic constexpr size_t bits = Stop - Start + 1;\n\n\tT &expr;\n\n\tslice_expr(T &expr) : expr(expr) {}\n\tslice_expr(const slice_expr<T, Stop, Start> &) = delete;\n\n\tCXXRTL_ALWAYS_INLINE\n\toperator value<bits>() const {\n\t\treturn static_cast<const value<T::bits> &>(expr)\n\t\t\t.template rtrunc<T::bits - Start>()\n\t\t\t.template trunc<bits>();\n\t}\n\n\tCXXRTL_ALWAYS_INLINE\n\tslice_expr<T, Stop, Start> &operator=(const value<bits> &rhs) {\n\t\t// Generic partial assignment implemented using a read-modify-write operation on the sliced expression.\n\t\texpr = static_cast<const value<T::bits> &>(expr)\n\t\t\t.template blit<Stop, Start>(rhs);\n\t\treturn *this;\n\t}\n\n\t// A helper that forces the cast to value<>, which allows deduction to work.\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<bits> val() const {\n\t\treturn static_cast<const value<bits> &>(*this);\n\t}\n};\n\n// Expression template for a concatenation, usable as lvalue or rvalue, and composable with other expression templates here.\ntemplate<class T, class U>\nstruct concat_expr : public expr_base<concat_expr<T, U>> {\n\tstatic constexpr size_t bits = T::bits + U::bits;\n\n\tT &ms_expr;\n\tU &ls_expr;\n\n\tconcat_expr(T &ms_expr, U &ls_expr) : ms_expr(ms_expr), ls_expr(ls_expr) {}\n\tconcat_expr(const concat_expr<T, U> &) = delete;\n\n\tCXXRTL_ALWAYS_INLINE\n\toperator value<bits>() const {\n\t\tvalue<bits> ms_shifted = static_cast<const value<T::bits> &>(ms_expr)\n\t\t\t.template rzext<bits>();\n\t\tvalue<bits> ls_extended = static_cast<const value<U::bits> &>(ls_expr)\n\t\t\t.template zext<bits>();\n\t\treturn ms_shifted.bit_or(ls_extended);\n\t}\n\n\tCXXRTL_ALWAYS_INLINE\n\tconcat_expr<T, U> &operator=(const value<bits> &rhs) {\n\t\tms_expr = rhs.template rtrunc<T::bits>();\n\t\tls_expr = rhs.template trunc<U::bits>();\n\t\treturn *this;\n\t}\n\n\t// A helper that forces the cast to value<>, which allows deduction to work.\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<bits> val() const {\n\t\treturn static_cast<const value<bits> &>(*this);\n\t}\n};\n\n// Base class for expression templates, providing helper methods for operations that are valid on both rvalues and lvalues.\n//\n// Note that expression objects (slices and concatenations) constructed in this way should NEVER be captured because\n// they refer to temporaries that will, in general, only live until the end of the statement. For example, both of\n// these snippets perform use-after-free:\n//\n// const auto &a = val.slice<7,0>().slice<1>();\n// value<1> b = a;\n//\n// auto &&c = val.slice<7,0>().slice<1>();\n// c = value<1>{1u};\n//\n// An easy way to write code using slices and concatenations safely is to follow two simple rules:\n// * Never explicitly name any type except `value<W>` or `const value<W> &`.\n// * Never use a `const auto &` or `auto &&` in any such expression.\n// Then, any code that compiles will be well-defined.\ntemplate<class T>\nstruct expr_base {\n\ttemplate<size_t Stop, size_t Start = Stop>\n\tCXXRTL_ALWAYS_INLINE\n\tslice_expr<const T, Stop, Start> slice() const {\n\t\treturn {*static_cast<const T *>(this)};\n\t}\n\n\ttemplate<size_t Stop, size_t Start = Stop>\n\tCXXRTL_ALWAYS_INLINE\n\tslice_expr<T, Stop, Start> slice() {\n\t\treturn {*static_cast<T *>(this)};\n\t}\n\n\ttemplate<class U>\n\tCXXRTL_ALWAYS_INLINE\n\tconcat_expr<const T, typename std::remove_reference<const U>::type> concat(const U &other) const {\n\t\treturn {*static_cast<const T *>(this), other};\n\t}\n\n\ttemplate<class U>\n\tCXXRTL_ALWAYS_INLINE\n\tconcat_expr<T, typename std::remove_reference<U>::type> concat(U &&other) {\n\t\treturn {*static_cast<T *>(this), other};\n\t}\n};\n\ntemplate<size_t Bits>\nstd::ostream &operator<<(std::ostream &os, const value<Bits> &val) {\n\tauto old_flags = os.flags(std::ios::right);\n\tauto old_width = os.width(0);\n\tauto old_fill = os.fill('0');\n\tos << val.bits << '\\'' << std::hex;\n\tfor (size_t n = val.chunks - 1; n != (size_t)-1; n--) {\n\t\tif (n == val.chunks - 1 && Bits % value<Bits>::chunk::bits != 0)\n\t\t\tos.width((Bits % value<Bits>::chunk::bits + 3) / 4);\n\t\telse\n\t\t\tos.width((value<Bits>::chunk::bits + 3) / 4);\n\t\tos << val.data[n];\n\t}\n\tos.fill(old_fill);\n\tos.width(old_width);\n\tos.flags(old_flags);\n\treturn os;\n}\n\ntemplate<size_t Bits>\nstruct value_formatted {\n\tconst value<Bits> &val;\n\tbool character;\n\tbool justify_left;\n\tchar padding;\n\tint width;\n\tint base;\n\tbool signed_;\n\tbool plus;\n\n\tvalue_formatted(const value<Bits> &val, bool character, bool justify_left, char padding, int width, int base, bool signed_, bool plus) :\n\t\tval(val), character(character), justify_left(justify_left), padding(padding), width(width), base(base), signed_(signed_), plus(plus) {}\n\tvalue_formatted(const value_formatted<Bits> &) = delete;\n\tvalue_formatted<Bits> &operator=(const value_formatted<Bits> &rhs) = delete;\n};\n\ntemplate<size_t Bits>\nstd::ostream &operator<<(std::ostream &os, const value_formatted<Bits> &vf)\n{\n\tvalue<Bits> val = vf.val;\n\n\tstd::string buf;\n\n\t// We might want to replace some of these bit() calls with direct\n\t// chunk access if it turns out to be slow enough to matter.\n\n\tif (!vf.character) {\n\t\tsize_t width = Bits;\n\t\tif (vf.base != 10) {\n\t\t\twidth = 0;\n\t\t\tfor (size_t index = 0; index < Bits; index++)\n\t\t\t\tif (val.bit(index))\n\t\t\t\t\twidth = index + 1;\n\t\t}\n\n\t\tif (vf.base == 2) {\n\t\t\tfor (size_t i = width; i > 0; i--)\n\t\t\t\tbuf += (val.bit(i - 1) ? '1' : '0');\n\t\t} else if (vf.base == 8 || vf.base == 16) {\n\t\t\tsize_t step = (vf.base == 16) ? 4 : 3;\n\t\t\tfor (size_t index = 0; index < width; index += step) {\n\t\t\t\tuint8_t value = val.bit(index) | (val.bit(index + 1) << 1) | (val.bit(index + 2) << 2);\n\t\t\t\tif (step == 4)\n\t\t\t\t\tvalue |= val.bit(index + 3) << 3;\n\t\t\t\tbuf += \"0123456789abcdef\"[value];\n\t\t\t}\n\t\t\tstd::reverse(buf.begin(), buf.end());\n\t\t} else if (vf.base == 10) {\n\t\t\tbool negative = vf.signed_ && val.is_neg();\n\t\t\tif (negative)\n\t\t\t\tval = val.neg();\n\t\t\tif (val.is_zero())\n\t\t\t\tbuf += '0';\n\t\t\twhile (!val.is_zero()) {\n\t\t\t\tvalue<Bits> quotient, remainder;\n\t\t\t\tif (Bits >= 4)\n\t\t\t\t\tstd::tie(quotient, remainder) = val.udivmod(value<Bits>{10u});\n\t\t\t\telse\n\t\t\t\t\tstd::tie(quotient, remainder) = std::make_pair(value<Bits>{0u}, val);\n\t\t\t\tbuf += '0' + remainder.template trunc<(Bits > 4 ? 4 : Bits)>().val().template get<uint8_t>();\n\t\t\t\tval = quotient;\n\t\t\t}\n\t\t\tif (negative || vf.plus)\n\t\t\t\tbuf += negative ? '-' : '+';\n\t\t\tstd::reverse(buf.begin(), buf.end());\n\t\t} else assert(false);\n\t} else {\n\t\tbuf.reserve(Bits/8);\n\t\tfor (int i = 0; i < Bits; i += 8) {\n\t\t\tchar ch = 0;\n\t\t\tfor (int j = 0; j < 8 && i + j < int(Bits); j++)\n\t\t\t\tif (val.bit(i + j))\n\t\t\t\t\tch |= 1 << j;\n\t\t\tif (ch != 0)\n\t\t\t\tbuf.append({ch});\n\t\t}\n\t\tstd::reverse(buf.begin(), buf.end());\n\t}\n\n\tassert(vf.width == 0 || vf.padding != '\\0');\n\tif (!vf.justify_left && buf.size() < vf.width) {\n\t\tsize_t pad_width = vf.width - buf.size();\n\t\tif (vf.padding == '0' && (buf.front() == '+' || buf.front() == '-')) {\n\t\t\tos << buf.front();\n\t\t\tbuf.erase(0, 1);\n\t\t}\n\t\tos << std::string(pad_width, vf.padding);\n\t}\n\tos << buf;\n\tif (vf.justify_left && buf.size() < vf.width)\n\t\tos << std::string(vf.width - buf.size(), vf.padding);\n\n\treturn os;\n}\n\n// An object that can be passed to a `commit()` method in order to produce a replay log of every state change in\n// the simulation.\nstruct observer {\n\t// Called when the `commit()` method for a wire is about to update the `chunks` chunks at `base` with `chunks` chunks\n\t// at `value` that have a different bit pattern. It is guaranteed that `chunks` is equal to the wire chunk count and\n\t// `base` points to the first chunk.\n\tvirtual void on_commit(size_t chunks, const chunk_t *base, const chunk_t *value) = 0;\n\n\t// Called when the `commit()` method for a memory is about to update the `chunks` chunks at `&base[chunks * index]`\n\t// with `chunks` chunks at `value` that have a different bit pattern. It is guaranteed that `chunks` is equal to\n\t// the memory element chunk count and `base` points to the first chunk of the first element of the memory.\n\tvirtual void on_commit(size_t chunks, const chunk_t *base, const chunk_t *value, size_t index) = 0;\n};\n\n// The `null_observer` class has the same interface as `observer`, but has no invocation overhead, since its methods\n// are final and have no implementation. This allows the observer feature to be zero-cost when not in use.\nstruct null_observer final: observer {\n\tvoid on_commit(size_t chunks, const chunk_t *base, const chunk_t *value) override {}\n\tvoid on_commit(size_t chunks, const chunk_t *base, const chunk_t *value, size_t index) override {}\n};\n\ntemplate<size_t Bits>\nstruct wire {\n\tstatic constexpr size_t bits = Bits;\n\n\tvalue<Bits> curr;\n\tvalue<Bits> next;\n\n\twire() = default;\n\texplicit constexpr wire(const value<Bits> &init) : curr(init), next(init) {}\n\ttemplate<typename... Init>\n\texplicit constexpr wire(Init ...init) : curr{init...}, next{init...} {}\n\n\t// Copying and copy-assigning values is natural. If, however, a value is replaced with a wire,\n\t// e.g. because a module is built with a different optimization level, then existing code could\n\t// unintentionally copy a wire instead, which would create a subtle but serious bug. To make sure\n\t// this doesn't happen, prohibit copying and copy-assigning wires.\n\twire(const wire<Bits> &) = delete;\n\twire<Bits> &operator=(const wire<Bits> &) = delete;\n\n\twire(wire<Bits> &&) = default;\n\twire<Bits> &operator=(wire<Bits> &&) = default;\n\n\ttemplate<class IntegerT>\n\tCXXRTL_ALWAYS_INLINE\n\tIntegerT get() const {\n\t\treturn curr.template get<IntegerT>();\n\t}\n\n\ttemplate<class IntegerT>\n\tCXXRTL_ALWAYS_INLINE\n\tvoid set(IntegerT other) {\n\t\tnext.template set<IntegerT>(other);\n\t}\n\n\t// This method intentionally takes a mandatory argument (to make it more difficult to misuse in\n\t// black box implementations, leading to missed observer events). It is generic over its argument\n\t// to make sure the `on_commit` call is devirtualized. This is somewhat awkward but lets us keep\n\t// a single implementation for both this method and the one in `memory`.\n\ttemplate<class ObserverT>\n\tbool commit(ObserverT &observer) {\n\t\tif (curr != next) {\n\t\t\tobserver.on_commit(curr.chunks, curr.data, next.data);\n\t\t\tcurr = next;\n\t\t\treturn true;\n\t\t}\n\t\treturn false;\n\t}\n};\n\ntemplate<size_t Bits>\nstd::ostream &operator<<(std::ostream &os, const wire<Bits> &val) {\n\tos << val.curr;\n\treturn os;\n}\n\ntemplate<size_t Width>\nstruct memory {\n\tconst size_t depth;\n\tstd::unique_ptr<value<Width>[]> data;\n\n\texplicit memory(size_t depth) : depth(depth), data(new value<Width>[depth]) {}\n\n\tmemory(const memory<Width> &) = delete;\n\tmemory<Width> &operator=(const memory<Width> &) = delete;\n\n\tmemory(memory<Width> &&) = default;\n\tmemory<Width> &operator=(memory<Width> &&other) {\n\t\tassert(depth == other.depth);\n\t\tdata = std::move(other.data);\n\t\twrite_queue = std::move(other.write_queue);\n\t\treturn *this;\n\t}\n\n\t// An operator for direct memory reads. May be used at any time during the simulation.\n\tconst value<Width> &operator [](size_t index) const {\n\t\tassert(index < depth);\n\t\treturn data[index];\n\t}\n\n\t// An operator for direct memory writes. May only be used before the simulation is started. If used\n\t// after the simulation is started, the design may malfunction.\n\tvalue<Width> &operator [](size_t index) {\n\t\tassert(index < depth);\n\t\treturn data[index];\n\t}\n\n\t// A simple way to make a writable memory would be to use an array of wires instead of an array of values.\n\t// However, there are two significant downsides to this approach: first, it has large overhead (2× space\n\t// overhead, and O(depth) time overhead during commit); second, it does not simplify handling write port\n\t// priorities. Although in principle write ports could be ordered or conditionally enabled in generated\n\t// code based on their priorities and selected addresses, the feedback arc set problem is computationally\n\t// expensive, and the heuristic based algorithms are not easily modified to guarantee (rather than prefer)\n\t// a particular write port evaluation order.\n\t//\n\t// The approach used here instead is to queue writes into a buffer during the eval phase, then perform\n\t// the writes during the commit phase in the priority order. This approach has low overhead, with both space\n\t// and time proportional to the amount of write ports. Because virtually every memory in a practical design\n\t// has at most two write ports, linear search is used on every write, being the fastest and simplest approach.\n\tstruct write {\n\t\tsize_t index;\n\t\tvalue<Width> val;\n\t\tvalue<Width> mask;\n\t\tint priority;\n\t};\n\tstd::vector<write> write_queue;\n\n\tvoid update(size_t index, const value<Width> &val, const value<Width> &mask, int priority = 0) {\n\t\tassert(index < depth);\n\t\t// Queue up the write while keeping the queue sorted by priority.\n\t\twrite_queue.insert(\n\t\t\tstd::upper_bound(write_queue.begin(), write_queue.end(), priority,\n\t\t\t\t[](const int a, const write& b) { return a < b.priority; }),\n\t\t\twrite { index, val, mask, priority });\n\t}\n\n\t// See the note for `wire::commit()`.\n\ttemplate<class ObserverT>\n\tbool commit(ObserverT &observer) {\n\t\tbool changed = false;\n\t\tfor (const write &entry : write_queue) {\n\t\t\tvalue<Width> elem = data[entry.index];\n\t\t\telem = elem.update(entry.val, entry.mask);\n\t\t\tif (data[entry.index] != elem) {\n\t\t\t\tobserver.on_commit(value<Width>::chunks, data[0].data, elem.data, entry.index);\n\t\t\t\tchanged |= true;\n\t\t\t}\n\t\t\tdata[entry.index] = elem;\n\t\t}\n\t\twrite_queue.clear();\n\t\treturn changed;\n\t}\n};\n\nstruct metadata {\n\tconst enum {\n\t\tMISSING = 0,\n\t\tUINT \t= 1,\n\t\tSINT \t= 2,\n\t\tSTRING \t= 3,\n\t\tDOUBLE \t= 4,\n\t} value_type;\n\n\t// In debug mode, using the wrong .as_*() function will assert.\n\t// In release mode, using the wrong .as_*() function will safely return a default value.\n\tconst uint64_t uint_value = 0;\n\tconst int64_t sint_value = 0;\n\tconst std::string string_value = \"\";\n\tconst double double_value = 0.0;\n\n\tmetadata() : value_type(MISSING) {}\n\tmetadata(uint64_t value) : value_type(UINT), uint_value(value) {}\n\tmetadata(int64_t value) : value_type(SINT), sint_value(value) {}\n\tmetadata(const std::string &value) : value_type(STRING), string_value(value) {}\n\tmetadata(const char *value) : value_type(STRING), string_value(value) {}\n\tmetadata(double value) : value_type(DOUBLE), double_value(value) {}\n\n\tmetadata(const metadata &) = default;\n\tmetadata &operator=(const metadata &) = delete;\n\n\tuint64_t as_uint() const {\n\t\tassert(value_type == UINT);\n\t\treturn uint_value;\n\t}\n\n\tint64_t as_sint() const {\n\t\tassert(value_type == SINT);\n\t\treturn sint_value;\n\t}\n\n\tconst std::string &as_string() const {\n\t\tassert(value_type == STRING);\n\t\treturn string_value;\n\t}\n\n\tdouble as_double() const {\n\t\tassert(value_type == DOUBLE);\n\t\treturn double_value;\n\t}\n};\n\ntypedef std::map<std::string, metadata> metadata_map;\n\n// Tag class to disambiguate values/wires and their aliases.\nstruct debug_alias {};\n\n// Tag declaration to disambiguate values and debug outlines.\nusing debug_outline = ::_cxxrtl_outline;\n\n// This structure is intended for consumption via foreign function interfaces, like Python's ctypes.\n// Because of this it uses a C-style layout that is easy to parse rather than more idiomatic C++.\n//\n// To avoid violating strict aliasing rules, this structure has to be a subclass of the one used\n// in the C API, or it would not be possible to cast between the pointers to these.\n//\n// The `attrs` member cannot be owned by this structure because a `cxxrtl_object` can be created\n// from external C code.\nstruct debug_item : ::cxxrtl_object {\n\t// Object types.\n\tenum : uint32_t {\n\t\tVALUE = CXXRTL_VALUE,\n\t\tWIRE = CXXRTL_WIRE,\n\t\tMEMORY = CXXRTL_MEMORY,\n\t\tALIAS = CXXRTL_ALIAS,\n\t\tOUTLINE = CXXRTL_OUTLINE,\n\t};\n\n\t// Object flags.\n\tenum : uint32_t {\n\t\tINPUT = CXXRTL_INPUT,\n\t\tOUTPUT = CXXRTL_OUTPUT,\n\t\tINOUT = CXXRTL_INOUT,\n\t\tDRIVEN_SYNC = CXXRTL_DRIVEN_SYNC,\n\t\tDRIVEN_COMB = CXXRTL_DRIVEN_COMB,\n\t\tUNDRIVEN = CXXRTL_UNDRIVEN,\n\t};\n\n\tdebug_item(const ::cxxrtl_object &object) : cxxrtl_object(object) {}\n\n\ttemplate<size_t Bits>\n\tdebug_item(value<Bits> &item, size_t lsb_offset = 0, uint32_t flags_ = 0) {\n\t\tstatic_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = VALUE;\n\t\tflags = flags_;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = item.data;\n\t\tnext = item.data;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(const value<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = VALUE;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.data);\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(wire<Bits> &item, size_t lsb_offset = 0, uint32_t flags_ = 0) {\n\t\tstatic_assert(sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&\n\t\t sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"wire<Bits> is not compatible with C layout\");\n\t\ttype = WIRE;\n\t\tflags = flags_;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = item.curr.data;\n\t\tnext = item.next.data;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Width>\n\tdebug_item(memory<Width> &item, size_t zero_offset = 0) {\n\t\tstatic_assert(sizeof(item.data[0]) == value<Width>::chunks * sizeof(chunk_t),\n\t\t \"memory<Width> is not compatible with C layout\");\n\t\ttype = MEMORY;\n\t\tflags = 0;\n\t\twidth = Width;\n\t\tlsb_at = 0;\n\t\tdepth = item.depth;\n\t\tzero_at = zero_offset;\n\t\tcurr = item.data ? item.data[0].data : nullptr;\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(debug_alias, const value<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = ALIAS;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.data);\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(debug_alias, const wire<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&\n\t\t sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"wire<Bits> is not compatible with C layout\");\n\t\ttype = ALIAS;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.curr.data);\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(debug_outline &group, const value<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = OUTLINE;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.data);\n\t\tnext = nullptr;\n\t\toutline = &group;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits, class IntegerT>\n\tIntegerT get() const {\n\t\tassert(width == Bits && depth == 1);\n\t\tvalue<Bits> item;\n\t\tstd::copy(curr, curr + value<Bits>::chunks, item.data);\n\t\treturn item.template get<IntegerT>();\n\t}\n\n\ttemplate<size_t Bits, class IntegerT>\n\tvoid set(IntegerT other) const {\n\t\tassert(width == Bits && depth == 1);\n\t\tvalue<Bits> item;\n\t\titem.template set<IntegerT>(other);\n\t\tstd::copy(item.data, item.data + value<Bits>::chunks, next);\n\t}\n};\nstatic_assert(std::is_standard_layout<debug_item>::value, \"debug_item is not compatible with C layout\");\n\n} // namespace cxxrtl\n\ntypedef struct _cxxrtl_attr_set {\n\tcxxrtl::metadata_map map;\n} *cxxrtl_attr_set;\n\nnamespace cxxrtl {\n\n// Representation of an attribute set in the C++ interface.\nusing debug_attrs = ::_cxxrtl_attr_set;\n\nstruct debug_items {\n\tstd::map<std::string, std::vector<debug_item>> table;\n\tstd::map<std::string, std::unique_ptr<debug_attrs>> attrs_table;\n\n\tvoid add(const std::string &name, debug_item &&item, metadata_map &&item_attrs = {}) {\n\t\tstd::unique_ptr<debug_attrs> &attrs = attrs_table[name];\n\t\tif (attrs.get() == nullptr)\n\t\t\tattrs = std::unique_ptr<debug_attrs>(new debug_attrs);\n\t\tfor (auto attr : item_attrs)\n\t\t\tattrs->map.insert(attr);\n\t\titem.attrs = attrs.get();\n\t\tstd::vector<debug_item> &parts = table[name];\n\t\tparts.emplace_back(item);\n\t\tstd::sort(parts.begin(), parts.end(),\n\t\t\t[](const debug_item &a, const debug_item &b) {\n\t\t\t\treturn a.lsb_at < b.lsb_at;\n\t\t\t});\n\t}\n\n\tsize_t count(const std::string &name) const {\n\t\tif (table.count(name) == 0)\n\t\t\treturn 0;\n\t\treturn table.at(name).size();\n\t}\n\n\tconst std::vector<debug_item> &parts_at(const std::string &name) const {\n\t\treturn table.at(name);\n\t}\n\n\tconst debug_item &at(const std::string &name) const {\n\t\tconst std::vector<debug_item> &parts = table.at(name);\n\t\tassert(parts.size() == 1);\n\t\treturn parts.at(0);\n\t}\n\n\tconst debug_item &operator [](const std::string &name) const {\n\t\treturn at(name);\n\t}\n\n\tconst metadata_map &attrs(const std::string &name) const {\n\t\treturn attrs_table.at(name)->map;\n\t}\n};\n\n// Tag class to disambiguate the default constructor used by the toplevel module that calls reset(),\n// and the constructor of interior modules that should not call it.\nstruct interior {};\n\nstruct module {\n\tmodule() {}\n\tvirtual ~module() {}\n\n\t// Modules with black boxes cannot be copied. Although not all designs include black boxes,\n\t// delete the copy constructor and copy assignment operator to make sure that any downstream\n\t// code that manipulates modules doesn't accidentally depend on their availability.\n\tmodule(const module &) = delete;\n\tmodule &operator=(const module &) = delete;\n\n\tmodule(module &&) = default;\n\tmodule &operator=(module &&) = default;\n\n\tvirtual void reset() = 0;\n\n\tvirtual bool eval() = 0;\n\tvirtual bool commit() = 0;\n\n\tunsigned int steps = 0;\n\n\tsize_t step() {\n\t\t++steps;\n\t\tsize_t deltas = 0;\n\t\tbool converged = false;\n\t\tdo {\n\t\t\tconverged = eval();\n\t\t\tdeltas++;\n\t\t} while (commit() && !converged);\n\t\treturn deltas;\n\t}\n\n\tvirtual void debug_info(debug_items &items, std::string path = \"\") {\n\t\t(void)items, (void)path;\n\t}\n};\n\n} // namespace cxxrtl\n\n// Internal structures used to communicate with the implementation of the C interface.\n\ntypedef struct _cxxrtl_toplevel {\n\tstd::unique_ptr<cxxrtl::module> module;\n} *cxxrtl_toplevel;\n\ntypedef struct _cxxrtl_outline {\n\tstd::function<void()> eval;\n} *cxxrtl_outline;\n\n// Definitions of internal Yosys cells. Other than the functions in this namespace, CXXRTL is fully generic\n// and indepenent of Yosys implementation details.\n//\n// The `write_cxxrtl` pass translates internal cells (cells with names that start with `$`) to calls of these\n// functions. All of Yosys arithmetic and logical cells perform sign or zero extension on their operands,\n// whereas basic operations on arbitrary width values require operands to be of the same width. These functions\n// bridge the gap by performing the necessary casts. They are named similar to `cell_A[B]`, where A and B are `u`\n// if the corresponding operand is unsigned, and `s` if it is signed.\nnamespace cxxrtl_yosys {\n\nusing namespace cxxrtl;\n\n// std::max isn't constexpr until C++14 for no particular reason (it's an oversight), so we define our own.\ntemplate<class T>\nCXXRTL_ALWAYS_INLINE\nconstexpr T max(const T &a, const T &b) {\n\treturn a > b ? a : b;\n}\n\n// Logic operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> logic_not(const value<BitsA> &a) {\n\treturn value<BitsY> { a ? 0u : 1u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> logic_and(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn value<BitsY> { (bool(a) && bool(b)) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> logic_or(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn value<BitsY> { (bool(a) || bool(b)) ? 1u : 0u };\n}\n\n// Reduction operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_and(const value<BitsA> &a) {\n\treturn value<BitsY> { a.bit_not().is_zero() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_or(const value<BitsA> &a) {\n\treturn value<BitsY> { a ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_xor(const value<BitsA> &a) {\n\treturn value<BitsY> { (a.ctpop() % 2) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_xnor(const value<BitsA> &a) {\n\treturn value<BitsY> { (a.ctpop() % 2) ? 0u : 1u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_bool(const value<BitsA> &a) {\n\treturn value<BitsY> { a ? 1u : 0u };\n}\n\n// Bitwise operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> not_u(const value<BitsA> &a) {\n\treturn a.template zcast<BitsY>().bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> not_s(const value<BitsA> &a) {\n\treturn a.template scast<BitsY>().bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> and_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_and(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> and_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_and(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> or_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_or(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> or_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_or(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_xor(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_xor(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xnor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_xor(b.template zcast<BitsY>()).bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xnor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_xor(b.template scast<BitsY>()).bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shl_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shl_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshl_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshl_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shr_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.shr(b).template zcast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shr_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.shr(b).template scast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshr_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.shr(b).template zcast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshr_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.sshr(b).template scast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shr_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shr_su<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_us(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn b.is_neg() ? shl_uu<BitsY>(a, b.template sext<BitsB + 1>().neg()) : shr_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn b.is_neg() ? shl_su<BitsY>(a, b.template sext<BitsB + 1>().neg()) : shr_su<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_su<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_us(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_us<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_ss<BitsY>(a, b);\n}\n\n// Comparison operations\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eq_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template zext<BitsExt>() == b.template zext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eq_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template sext<BitsExt>() == b.template sext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ne_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template zext<BitsExt>() != b.template zext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ne_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template sext<BitsExt>() != b.template sext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eqx_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn eq_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eqx_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn eq_ss<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> nex_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn ne_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> nex_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn ne_ss<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> gt_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { b.template zext<BitsExt>().ucmp(a.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> gt_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { b.template sext<BitsExt>().scmp(a.template sext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ge_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !a.template zext<BitsExt>().ucmp(b.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ge_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !a.template sext<BitsExt>().scmp(b.template sext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> lt_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { a.template zext<BitsExt>().ucmp(b.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> lt_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { a.template sext<BitsExt>().scmp(b.template sext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> le_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !b.template zext<BitsExt>().ucmp(a.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> le_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !b.template sext<BitsExt>().scmp(a.template sext<BitsExt>()) ? 1u : 0u };\n}\n\n// Arithmetic operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> pos_u(const value<BitsA> &a) {\n\treturn a.template zcast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> pos_s(const value<BitsA> &a) {\n\treturn a.template scast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> neg_u(const value<BitsA> &a) {\n\treturn a.template zcast<BitsY>().neg();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> neg_s(const value<BitsA> &a) {\n\treturn a.template scast<BitsY>().neg();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> add_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().add(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> add_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().add(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sub_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().sub(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sub_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().sub(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mul_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsM = BitsA >= BitsB ? BitsA : BitsB;\n\treturn a.template zcast<BitsM>().template mul<BitsY>(b.template zcast<BitsM>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mul_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().template mul<BitsY>(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nstd::pair<value<BitsY>, value<BitsY>> divmod_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t Bits = max(BitsY, max(BitsA, BitsB));\n\tvalue<Bits> quotient;\n\tvalue<Bits> remainder;\n\tvalue<Bits> dividend = a.template zext<Bits>();\n\tvalue<Bits> divisor = b.template zext<Bits>();\n\tstd::tie(quotient, remainder) = dividend.udivmod(divisor);\n\treturn {quotient.template trunc<BitsY>(), remainder.template trunc<BitsY>()};\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nstd::pair<value<BitsY>, value<BitsY>> divmod_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t Bits = max(BitsY, max(BitsA, BitsB));\n\tvalue<Bits> quotient;\n\tvalue<Bits> remainder;\n\tvalue<Bits> dividend = a.template sext<Bits>();\n\tvalue<Bits> divisor = b.template sext<Bits>();\n\tstd::tie(quotient, remainder) = dividend.sdivmod(divisor);\n\treturn {quotient.template trunc<BitsY>(), remainder.template trunc<BitsY>()};\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> div_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).first;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> div_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_ss<BitsY>(a, b).first;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mod_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).second;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mod_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_ss<BitsY>(a, b).second;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> modfloor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).second;\n}\n\n// GHDL Modfloor operator. Returns r=a mod b, such that r has the same sign as b and\n// a=b*N+r where N is some integer\n// In practical terms, when a and b have different signs and the remainder returned by divmod_ss is not 0\n// then return the remainder + b\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> modfloor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tvalue<BitsY> r;\n\tr = divmod_ss<BitsY>(a, b).second;\n\tif((b.is_neg() != a.is_neg()) && !r.is_zero())\n\t\treturn add_ss<BitsY>(b, r);\n\treturn r;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> divfloor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).first;\n}\n\n// Divfloor. Similar to above: returns q=a//b, where q has the sign of a*b and a=b*q+N.\n// In other words, returns (truncating) a/b, except if a and b have different signs\n// and there's non-zero remainder, subtract one more towards floor.\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> divfloor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tvalue<BitsY> q, r;\n\tstd::tie(q, r) = divmod_ss<BitsY>(a, b);\n\tif ((b.is_neg() != a.is_neg()) && !r.is_zero())\n\t\treturn sub_uu<BitsY>(q, value<1> { 1u });\n\treturn q;\n\n}\n\n// Memory helper\nstruct memory_index {\n\tbool valid;\n\tsize_t index;\n\n\ttemplate<size_t BitsAddr>\n\tmemory_index(const value<BitsAddr> &addr, size_t offset, size_t depth) {\n\t\tstatic_assert(value<BitsAddr>::chunks <= 1, \"memory address is too wide\");\n\t\tsize_t offset_index = addr.data[0];\n\n\t\tvalid = (offset_index >= offset && offset_index < offset + depth);\n\t\tindex = offset_index - offset;\n\t}\n};\n\n} // namespace cxxrtl_yosys\n\n#endif\n",
135
+ "cxxrtl.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2019-2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n// This file is included by the designs generated with `write_cxxrtl`. It is not used in Yosys itself.\n//\n// The CXXRTL support library implements compile time specialized arbitrary width arithmetics, as well as provides\n// composite lvalues made out of bit slices and concatenations of lvalues. This allows the `write_cxxrtl` pass\n// to perform a straightforward translation of RTLIL structures to readable C++, relying on the C++ compiler\n// to unwrap the abstraction and generate efficient code.\n\n#ifndef CXXRTL_H\n#define CXXRTL_H\n\n#include <cstddef>\n#include <cstdint>\n#include <cstring>\n#include <cassert>\n#include <limits>\n#include <type_traits>\n#include <tuple>\n#include <vector>\n#include <map>\n#include <algorithm>\n#include <memory>\n#include <functional>\n#include <sstream>\n#include <iostream>\n\n// `cxxrtl::debug_item` has to inherit from `cxxrtl_object` to satisfy strict aliasing requirements.\n#include <cxxrtl/capi/cxxrtl_capi.h>\n\n#ifndef __has_attribute\n#\tdefine __has_attribute(x) 0\n#endif\n\n// CXXRTL essentially uses the C++ compiler as a hygienic macro engine that feeds an instruction selector.\n// It generates a lot of specialized template functions with relatively large bodies that, when inlined\n// into the caller and (for those with loops) unrolled, often expose many new optimization opportunities.\n// Because of this, most of the CXXRTL runtime must be always inlined for best performance.\n#if __has_attribute(always_inline)\n#define CXXRTL_ALWAYS_INLINE inline __attribute__((__always_inline__))\n#else\n#define CXXRTL_ALWAYS_INLINE inline\n#endif\n// Conversely, some functions in the generated code are extremely large yet very cold, with both of these\n// properties being extreme enough to confuse C++ compilers into spending pathological amounts of time\n// on a futile (the code becomes worse) attempt to optimize the least important parts of code.\n#if __has_attribute(optnone)\n#define CXXRTL_EXTREMELY_COLD __attribute__((__optnone__))\n#elif __has_attribute(optimize)\n#define CXXRTL_EXTREMELY_COLD __attribute__((__optimize__(0)))\n#else\n#define CXXRTL_EXTREMELY_COLD\n#endif\n\n// CXXRTL uses assert() to check for C++ contract violations (which may result in e.g. undefined behavior\n// of the simulation code itself), and CXXRTL_ASSERT to check for RTL contract violations (which may at\n// most result in undefined simulation results).\n//\n// Though by default, CXXRTL_ASSERT() expands to assert(), it may be overridden e.g. when integrating\n// the simulation into another process that should survive violating RTL contracts.\n#ifndef CXXRTL_ASSERT\n#ifndef CXXRTL_NDEBUG\n#define CXXRTL_ASSERT(x) assert(x)\n#else\n#define CXXRTL_ASSERT(x)\n#endif\n#endif\n\nnamespace cxxrtl {\n\n// All arbitrary-width values in CXXRTL are backed by arrays of unsigned integers called chunks. The chunk size\n// is the same regardless of the value width to simplify manipulating values via FFI interfaces, e.g. driving\n// and introspecting the simulation in Python.\n//\n// It is practical to use chunk sizes between 32 bits and platform register size because when arithmetics on\n// narrower integer types is legalized by the C++ compiler, it inserts code to clear the high bits of the register.\n// However, (a) most of our operations do not change those bits in the first place because of invariants that are\n// invisible to the compiler, (b) we often operate on non-power-of-2 values and have to clear the high bits anyway.\n// Therefore, using relatively wide chunks and clearing the high bits explicitly and only when we know they may be\n// clobbered results in simpler generated code.\ntypedef uint32_t chunk_t;\ntypedef uint64_t wide_chunk_t;\n\ntemplate<typename T>\nstruct chunk_traits {\n\tstatic_assert(std::is_integral<T>::value && std::is_unsigned<T>::value,\n\t \"chunk type must be an unsigned integral type\");\n\tusing type = T;\n\tstatic constexpr size_t bits = std::numeric_limits<T>::digits;\n\tstatic constexpr T mask = std::numeric_limits<T>::max();\n};\n\ntemplate<class T>\nstruct expr_base;\n\ntemplate<size_t Bits>\nstruct value : public expr_base<value<Bits>> {\n\tstatic constexpr size_t bits = Bits;\n\n\tusing chunk = chunk_traits<chunk_t>;\n\tstatic constexpr chunk::type msb_mask = (Bits % chunk::bits == 0) ? chunk::mask\n\t\t: chunk::mask >> (chunk::bits - (Bits % chunk::bits));\n\n\tstatic constexpr size_t chunks = (Bits + chunk::bits - 1) / chunk::bits;\n\tchunk::type data[chunks] = {};\n\n\tvalue() = default;\n\ttemplate<typename... Init>\n\texplicit constexpr value(Init ...init) : data{init...} {}\n\n\tvalue(const value<Bits> &) = default;\n\tvalue<Bits> &operator=(const value<Bits> &) = default;\n\n\tvalue(value<Bits> &&) = default;\n\tvalue<Bits> &operator=(value<Bits> &&) = default;\n\n\t// A (no-op) helper that forces the cast to value<>.\n\tCXXRTL_ALWAYS_INLINE\n\tconst value<Bits> &val() const {\n\t\treturn *this;\n\t}\n\n\tstd::string str() const {\n\t\tstd::stringstream ss;\n\t\tss << *this;\n\t\treturn ss.str();\n\t}\n\n\t// Conversion operations.\n\t//\n\t// These functions ensure that a conversion is never out of range, and should be always used, if at all\n\t// possible, instead of direct manipulation of the `data` member. For very large types, .slice() and\n\t// .concat() can be used to split them into more manageable parts.\n\ttemplate<class IntegerT, typename std::enable_if<!std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tIntegerT get() const {\n\t\tstatic_assert(std::numeric_limits<IntegerT>::is_integer && !std::numeric_limits<IntegerT>::is_signed,\n\t\t \"get<T>() requires T to be an unsigned integral type\");\n\t\tstatic_assert(std::numeric_limits<IntegerT>::digits >= Bits,\n\t\t \"get<T>() requires T to be at least as wide as the value is\");\n\t\tIntegerT result = 0;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult |= IntegerT(data[n]) << (n * chunk::bits);\n\t\treturn result;\n\t}\n\n\ttemplate<class IntegerT, typename std::enable_if<std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tIntegerT get() const {\n\t\tauto unsigned_result = get<typename std::make_unsigned<IntegerT>::type>();\n\t\tIntegerT result;\n\t\tmemcpy(&result, &unsigned_result, sizeof(IntegerT));\n\t\treturn result;\n\t}\n\n\ttemplate<class IntegerT, typename std::enable_if<!std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tvoid set(IntegerT value) {\n\t\tstatic_assert(std::numeric_limits<IntegerT>::is_integer && !std::numeric_limits<IntegerT>::is_signed,\n\t\t \"set<T>() requires T to be an unsigned integral type\");\n\t\tstatic_assert(std::numeric_limits<IntegerT>::digits >= Bits,\n\t\t \"set<T>() requires the value to be at least as wide as T is\");\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tdata[n] = (value >> (n * chunk::bits)) & chunk::mask;\n\t}\n\n\ttemplate<class IntegerT, typename std::enable_if<std::is_signed<IntegerT>::value, int>::type = 0>\n\tCXXRTL_ALWAYS_INLINE\n\tvoid set(IntegerT value) {\n\t\ttypename std::make_unsigned<IntegerT>::type unsigned_value;\n\t\tmemcpy(&unsigned_value, &value, sizeof(IntegerT));\n\t\tset(unsigned_value);\n\t}\n\n\t// Operations with compile-time parameters.\n\t//\n\t// These operations are used to implement slicing, concatenation, and blitting.\n\t// The trunc, zext and sext operations add or remove most significant bits (i.e. on the left);\n\t// the rtrunc and rzext operations add or remove least significant bits (i.e. on the right).\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> trunc() const {\n\t\tstatic_assert(NewBits <= Bits, \"trunc() may not increase width\");\n\t\tvalue<NewBits> result;\n\t\tfor (size_t n = 0; n < result.chunks; n++)\n\t\t\tresult.data[n] = data[n];\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> zext() const {\n\t\tstatic_assert(NewBits >= Bits, \"zext() may not decrease width\");\n\t\tvalue<NewBits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n];\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> sext() const {\n\t\tstatic_assert(NewBits >= Bits, \"sext() may not decrease width\");\n\t\tvalue<NewBits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n];\n\t\tif (is_neg()) {\n\t\t\tresult.data[chunks - 1] |= ~msb_mask;\n\t\t\tfor (size_t n = chunks; n < result.chunks; n++)\n\t\t\t\tresult.data[n] = chunk::mask;\n\t\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\t}\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> rtrunc() const {\n\t\tstatic_assert(NewBits <= Bits, \"rtrunc() may not increase width\");\n\t\tvalue<NewBits> result;\n\t\tconstexpr size_t shift_chunks = (Bits - NewBits) / chunk::bits;\n\t\tconstexpr size_t shift_bits = (Bits - NewBits) % chunk::bits;\n\t\tchunk::type carry = 0;\n\t\tif (shift_chunks + result.chunks < chunks) {\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[shift_chunks + result.chunks] << (chunk::bits - shift_bits);\n\t\t}\n\t\tfor (size_t n = result.chunks; n > 0; n--) {\n\t\t\tresult.data[n - 1] = carry | (data[shift_chunks + n - 1] >> shift_bits);\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[shift_chunks + n - 1] << (chunk::bits - shift_bits);\n\t\t}\n\t\treturn result;\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> rzext() const {\n\t\tstatic_assert(NewBits >= Bits, \"rzext() may not decrease width\");\n\t\tvalue<NewBits> result;\n\t\tconstexpr size_t shift_chunks = (NewBits - Bits) / chunk::bits;\n\t\tconstexpr size_t shift_bits = (NewBits - Bits) % chunk::bits;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tresult.data[shift_chunks + n] = (data[n] << shift_bits) | carry;\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[n] >> (chunk::bits - shift_bits);\n\t\t}\n\t\tif (shift_chunks + chunks < result.chunks)\n\t\t\tresult.data[shift_chunks + chunks] = carry;\n\t\treturn result;\n\t}\n\n\t// Bit blit operation, i.e. a partial read-modify-write.\n\ttemplate<size_t Stop, size_t Start>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<Bits> blit(const value<Stop - Start + 1> &source) const {\n\t\tstatic_assert(Stop >= Start, \"blit() may not reverse bit order\");\n\t\tconstexpr chunk::type start_mask = ~(chunk::mask << (Start % chunk::bits));\n\t\tconstexpr chunk::type stop_mask = (Stop % chunk::bits + 1 == chunk::bits) ? 0\n\t\t\t: (chunk::mask << (Stop % chunk::bits + 1));\n\t\tvalue<Bits> masked = *this;\n\t\tif (Start / chunk::bits == Stop / chunk::bits) {\n\t\t\tmasked.data[Start / chunk::bits] &= stop_mask | start_mask;\n\t\t} else {\n\t\t\tmasked.data[Start / chunk::bits] &= start_mask;\n\t\t\tfor (size_t n = Start / chunk::bits + 1; n < Stop / chunk::bits; n++)\n\t\t\t\tmasked.data[n] = 0;\n\t\t\tmasked.data[Stop / chunk::bits] &= stop_mask;\n\t\t}\n\t\tvalue<Bits> shifted = source\n\t\t\t.template rzext<Stop + 1>()\n\t\t\t.template zext<Bits>();\n\t\treturn masked.bit_or(shifted);\n\t}\n\n\t// Helpers for selecting extending or truncating operation depending on whether the result is wider or narrower\n\t// than the operand. In C++17 these can be replaced with `if constexpr`.\n\ttemplate<size_t NewBits, typename = void>\n\tstruct zext_cast {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template zext<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits>\n\tstruct zext_cast<NewBits, typename std::enable_if<(NewBits < Bits)>::type> {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template trunc<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits, typename = void>\n\tstruct sext_cast {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template sext<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits>\n\tstruct sext_cast<NewBits, typename std::enable_if<(NewBits < Bits)>::type> {\n\t\tCXXRTL_ALWAYS_INLINE\n\t\tvalue<NewBits> operator()(const value<Bits> &val) {\n\t\t\treturn val.template trunc<NewBits>();\n\t\t}\n\t};\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> zcast() const {\n\t\treturn zext_cast<NewBits>()(*this);\n\t}\n\n\ttemplate<size_t NewBits>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<NewBits> scast() const {\n\t\treturn sext_cast<NewBits>()(*this);\n\t}\n\n\t// Bit replication is far more efficient than the equivalent concatenation.\n\ttemplate<size_t Count>\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<Bits * Count> repeat() const {\n\t\tstatic_assert(Bits == 1, \"repeat() is implemented only for 1-bit values\");\n\t\treturn *this ? value<Bits * Count>().bit_not() : value<Bits * Count>();\n\t}\n\n\t// Operations with run-time parameters (offsets, amounts, etc).\n\t//\n\t// These operations are used for computations.\n\tbool bit(size_t offset) const {\n\t\treturn data[offset / chunk::bits] & (1 << (offset % chunk::bits));\n\t}\n\n\tvoid set_bit(size_t offset, bool value = true) {\n\t\tsize_t offset_chunks = offset / chunk::bits;\n\t\tsize_t offset_bits = offset % chunk::bits;\n\t\tdata[offset_chunks] &= ~(1 << offset_bits);\n\t\tdata[offset_chunks] |= value ? 1 << offset_bits : 0;\n\t}\n\n\texplicit operator bool() const {\n\t\treturn !is_zero();\n\t}\n\n\tbool is_zero() const {\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tif (data[n] != 0)\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool is_neg() const {\n\t\treturn data[chunks - 1] & (1 << ((Bits - 1) % chunk::bits));\n\t}\n\n\tbool operator ==(const value<Bits> &other) const {\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tif (data[n] != other.data[n])\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool operator !=(const value<Bits> &other) const {\n\t\treturn !(*this == other);\n\t}\n\n\tvalue<Bits> bit_not() const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = ~data[n];\n\t\tresult.data[chunks - 1] &= msb_mask;\n\t\treturn result;\n\t}\n\n\tvalue<Bits> bit_and(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n] & other.data[n];\n\t\treturn result;\n\t}\n\n\tvalue<Bits> bit_or(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n] | other.data[n];\n\t\treturn result;\n\t}\n\n\tvalue<Bits> bit_xor(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tfor (size_t n = 0; n < chunks; n++)\n\t\t\tresult.data[n] = data[n] ^ other.data[n];\n\t\treturn result;\n\t}\n\n\tvalue<Bits> update(const value<Bits> &val, const value<Bits> &mask) const {\n\t\treturn bit_and(mask.bit_not()).bit_or(val.bit_and(mask));\n\t}\n\n\ttemplate<size_t AmountBits>\n\tvalue<Bits> shl(const value<AmountBits> &amount) const {\n\t\t// Ensure our early return is correct by prohibiting values larger than 4 Gbit.\n\t\tstatic_assert(Bits <= chunk::mask, \"shl() of unreasonably large values is not supported\");\n\t\t// Detect shifts definitely large than Bits early.\n\t\tfor (size_t n = 1; n < amount.chunks; n++)\n\t\t\tif (amount.data[n] != 0)\n\t\t\t\treturn {};\n\t\t// Past this point we can use the least significant chunk as the shift size.\n\t\tsize_t shift_chunks = amount.data[0] / chunk::bits;\n\t\tsize_t shift_bits = amount.data[0] % chunk::bits;\n\t\tif (shift_chunks >= chunks)\n\t\t\treturn {};\n\t\tvalue<Bits> result;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks - shift_chunks; n++) {\n\t\t\tresult.data[shift_chunks + n] = (data[n] << shift_bits) | carry;\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[n] >> (chunk::bits - shift_bits);\n\t\t}\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\ttemplate<size_t AmountBits, bool Signed = false>\n\tvalue<Bits> shr(const value<AmountBits> &amount) const {\n\t\t// Ensure our early return is correct by prohibiting values larger than 4 Gbit.\n\t\tstatic_assert(Bits <= chunk::mask, \"shr() of unreasonably large values is not supported\");\n\t\t// Detect shifts definitely large than Bits early.\n\t\tfor (size_t n = 1; n < amount.chunks; n++)\n\t\t\tif (amount.data[n] != 0)\n\t\t\t\treturn (Signed && is_neg()) ? value<Bits>().bit_not() : value<Bits>();\n\t\t// Past this point we can use the least significant chunk as the shift size.\n\t\tsize_t shift_chunks = amount.data[0] / chunk::bits;\n\t\tsize_t shift_bits = amount.data[0] % chunk::bits;\n\t\tif (shift_chunks >= chunks)\n\t\t\treturn (Signed && is_neg()) ? value<Bits>().bit_not() : value<Bits>();\n\t\tvalue<Bits> result;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks - shift_chunks; n++) {\n\t\t\tresult.data[chunks - shift_chunks - 1 - n] = carry | (data[chunks - 1 - n] >> shift_bits);\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[chunks - 1 - n] << (chunk::bits - shift_bits);\n\t\t}\n\t\tif (Signed && is_neg()) {\n\t\t\tsize_t top_chunk_idx = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) / chunk::bits;\n\t\t\tsize_t top_chunk_bits = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) % chunk::bits;\n\t\t\tfor (size_t n = top_chunk_idx + 1; n < chunks; n++)\n\t\t\t\tresult.data[n] = chunk::mask;\n\t\t\tif (amount.data[0] != 0)\n\t\t\t\tresult.data[top_chunk_idx] |= chunk::mask << top_chunk_bits;\n\t\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\t}\n\t\treturn result;\n\t}\n\n\ttemplate<size_t AmountBits>\n\tvalue<Bits> sshr(const value<AmountBits> &amount) const {\n\t\treturn shr<AmountBits, /*Signed=*/true>(amount);\n\t}\n\n\ttemplate<size_t ResultBits, size_t SelBits>\n\tvalue<ResultBits> bmux(const value<SelBits> &sel) const {\n\t\tstatic_assert(ResultBits << SelBits == Bits, \"invalid sizes used in bmux()\");\n\t\tsize_t amount = sel.data[0] * ResultBits;\n\t\tsize_t shift_chunks = amount / chunk::bits;\n\t\tsize_t shift_bits = amount % chunk::bits;\n\t\tvalue<ResultBits> result;\n\t\tchunk::type carry = 0;\n\t\tif (ResultBits % chunk::bits + shift_bits > chunk::bits)\n\t\t\tcarry = data[result.chunks + shift_chunks] << (chunk::bits - shift_bits);\n\t\tfor (size_t n = 0; n < result.chunks; n++) {\n\t\t\tresult.data[result.chunks - 1 - n] = carry | (data[result.chunks + shift_chunks - 1 - n] >> shift_bits);\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[result.chunks + shift_chunks - 1 - n] << (chunk::bits - shift_bits);\n\t\t}\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\ttemplate<size_t ResultBits, size_t SelBits>\n\tvalue<ResultBits> demux(const value<SelBits> &sel) const {\n\t\tstatic_assert(Bits << SelBits == ResultBits, \"invalid sizes used in demux()\");\n\t\tsize_t amount = sel.data[0] * Bits;\n\t\tsize_t shift_chunks = amount / chunk::bits;\n\t\tsize_t shift_bits = amount % chunk::bits;\n\t\tvalue<ResultBits> result;\n\t\tchunk::type carry = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tresult.data[shift_chunks + n] = (data[n] << shift_bits) | carry;\n\t\t\tcarry = (shift_bits == 0) ? 0\n\t\t\t\t: data[n] >> (chunk::bits - shift_bits);\n\t\t}\n\t\tif (Bits % chunk::bits + shift_bits > chunk::bits)\n\t\t\tresult.data[shift_chunks + chunks] = carry;\n\t\treturn result;\n\t}\n\n\tsize_t ctpop() const {\n\t\tsize_t count = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\t// This loop implements the population count idiom as recognized by LLVM and GCC.\n\t\t\tfor (chunk::type x = data[n]; x != 0; count++)\n\t\t\t\tx = x & (x - 1);\n\t\t}\n\t\treturn count;\n\t}\n\n\tsize_t ctlz() const {\n\t\tsize_t count = 0;\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tchunk::type x = data[chunks - 1 - n];\n\t\t\t// First add to `count` as if the chunk is zero\n\t\t\tconstexpr size_t msb_chunk_bits = Bits % chunk::bits != 0 ? Bits % chunk::bits : chunk::bits;\n\t\t\tcount += (n == 0 ? msb_chunk_bits : chunk::bits);\n\t\t\t// If the chunk isn't zero, correct the `count` value and return\n\t\t\tif (x != 0) {\n\t\t\t\tfor (; x != 0; count--)\n\t\t\t\t\tx >>= 1;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\treturn count;\n\t}\n\n\ttemplate<bool Invert, bool CarryIn>\n\tstd::pair<value<Bits>, bool /*CarryOut*/> alu(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tbool carry = CarryIn;\n\t\tfor (size_t n = 0; n < result.chunks; n++) {\n\t\t\tresult.data[n] = data[n] + (Invert ? ~other.data[n] : other.data[n]) + carry;\n\t\t\tif (result.chunks - 1 == n)\n\t\t\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\t\tcarry = (result.data[n] < data[n]) ||\n\t\t\t (result.data[n] == data[n] && carry);\n\t\t}\n\t\treturn {result, carry};\n\t}\n\n\tvalue<Bits> add(const value<Bits> &other) const {\n\t\treturn alu</*Invert=*/false, /*CarryIn=*/false>(other).first;\n\t}\n\n\tvalue<Bits> sub(const value<Bits> &other) const {\n\t\treturn alu</*Invert=*/true, /*CarryIn=*/true>(other).first;\n\t}\n\n\tvalue<Bits> neg() const {\n\t\treturn value<Bits>().sub(*this);\n\t}\n\n\tbool ucmp(const value<Bits> &other) const {\n\t\tbool carry;\n\t\tstd::tie(std::ignore, carry) = alu</*Invert=*/true, /*CarryIn=*/true>(other);\n\t\treturn !carry; // a.ucmp(b) ≡ a u< b\n\t}\n\n\tbool scmp(const value<Bits> &other) const {\n\t\tvalue<Bits> result;\n\t\tbool carry;\n\t\tstd::tie(result, carry) = alu</*Invert=*/true, /*CarryIn=*/true>(other);\n\t\tbool overflow = (is_neg() == !other.is_neg()) && (is_neg() != result.is_neg());\n\t\treturn result.is_neg() ^ overflow; // a.scmp(b) ≡ a s< b\n\t}\n\n\ttemplate<size_t ResultBits>\n\tvalue<ResultBits> mul(const value<Bits> &other) const {\n\t\tvalue<ResultBits> result;\n\t\twide_chunk_t wide_result[result.chunks + 1] = {};\n\t\tfor (size_t n = 0; n < chunks; n++) {\n\t\t\tfor (size_t m = 0; m < chunks && n + m < result.chunks; m++) {\n\t\t\t\twide_result[n + m] += wide_chunk_t(data[n]) * wide_chunk_t(other.data[m]);\n\t\t\t\twide_result[n + m + 1] += wide_result[n + m] >> chunk::bits;\n\t\t\t\twide_result[n + m] &= chunk::mask;\n\t\t\t}\n\t\t}\n\t\tfor (size_t n = 0; n < result.chunks; n++) {\n\t\t\tresult.data[n] = wide_result[n];\n\t\t}\n\t\tresult.data[result.chunks - 1] &= result.msb_mask;\n\t\treturn result;\n\t}\n\n\tstd::pair<value<Bits>, value<Bits>> udivmod(value<Bits> divisor) const {\n\t\tvalue<Bits> quotient;\n\t\tvalue<Bits> dividend = *this;\n\t\tif (dividend.ucmp(divisor))\n\t\t\treturn {/*quotient=*/value<Bits>{0u}, /*remainder=*/dividend};\n\t\tint64_t divisor_shift = divisor.ctlz() - dividend.ctlz();\n\t\tassert(divisor_shift >= 0);\n\t\tdivisor = divisor.shl(value<Bits>{(chunk::type) divisor_shift});\n\t\tfor (size_t step = 0; step <= divisor_shift; step++) {\n\t\t\tquotient = quotient.shl(value<Bits>{1u});\n\t\t\tif (!dividend.ucmp(divisor)) {\n\t\t\t\tdividend = dividend.sub(divisor);\n\t\t\t\tquotient.set_bit(0, true);\n\t\t\t}\n\t\t\tdivisor = divisor.shr(value<Bits>{1u});\n\t\t}\n\t\treturn {quotient, /*remainder=*/dividend};\n\t}\n\n\tstd::pair<value<Bits>, value<Bits>> sdivmod(const value<Bits> &other) const {\n\t\tvalue<Bits + 1> quotient;\n\t\tvalue<Bits + 1> remainder;\n\t\tvalue<Bits + 1> dividend = sext<Bits + 1>();\n\t\tvalue<Bits + 1> divisor = other.template sext<Bits + 1>();\n\t\tif (dividend.is_neg()) dividend = dividend.neg();\n\t\tif (divisor.is_neg()) divisor = divisor.neg();\n\t\tstd::tie(quotient, remainder) = dividend.udivmod(divisor);\n\t\tif (dividend.is_neg() != divisor.is_neg()) quotient = quotient.neg();\n\t\tif (dividend.is_neg()) remainder = remainder.neg();\n\t\treturn {quotient.template trunc<Bits>(), remainder.template trunc<Bits>()};\n\t}\n};\n\n// Expression template for a slice, usable as lvalue or rvalue, and composable with other expression templates here.\ntemplate<class T, size_t Stop, size_t Start>\nstruct slice_expr : public expr_base<slice_expr<T, Stop, Start>> {\n\tstatic_assert(Stop >= Start, \"slice_expr() may not reverse bit order\");\n\tstatic_assert(Start < T::bits && Stop < T::bits, \"slice_expr() must be within bounds\");\n\tstatic constexpr size_t bits = Stop - Start + 1;\n\n\tT &expr;\n\n\tslice_expr(T &expr) : expr(expr) {}\n\tslice_expr(const slice_expr<T, Stop, Start> &) = delete;\n\n\tCXXRTL_ALWAYS_INLINE\n\toperator value<bits>() const {\n\t\treturn static_cast<const value<T::bits> &>(expr)\n\t\t\t.template rtrunc<T::bits - Start>()\n\t\t\t.template trunc<bits>();\n\t}\n\n\tCXXRTL_ALWAYS_INLINE\n\tslice_expr<T, Stop, Start> &operator=(const value<bits> &rhs) {\n\t\t// Generic partial assignment implemented using a read-modify-write operation on the sliced expression.\n\t\texpr = static_cast<const value<T::bits> &>(expr)\n\t\t\t.template blit<Stop, Start>(rhs);\n\t\treturn *this;\n\t}\n\n\t// A helper that forces the cast to value<>, which allows deduction to work.\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<bits> val() const {\n\t\treturn static_cast<const value<bits> &>(*this);\n\t}\n};\n\n// Expression template for a concatenation, usable as lvalue or rvalue, and composable with other expression templates here.\ntemplate<class T, class U>\nstruct concat_expr : public expr_base<concat_expr<T, U>> {\n\tstatic constexpr size_t bits = T::bits + U::bits;\n\n\tT &ms_expr;\n\tU &ls_expr;\n\n\tconcat_expr(T &ms_expr, U &ls_expr) : ms_expr(ms_expr), ls_expr(ls_expr) {}\n\tconcat_expr(const concat_expr<T, U> &) = delete;\n\n\tCXXRTL_ALWAYS_INLINE\n\toperator value<bits>() const {\n\t\tvalue<bits> ms_shifted = static_cast<const value<T::bits> &>(ms_expr)\n\t\t\t.template rzext<bits>();\n\t\tvalue<bits> ls_extended = static_cast<const value<U::bits> &>(ls_expr)\n\t\t\t.template zext<bits>();\n\t\treturn ms_shifted.bit_or(ls_extended);\n\t}\n\n\tCXXRTL_ALWAYS_INLINE\n\tconcat_expr<T, U> &operator=(const value<bits> &rhs) {\n\t\tms_expr = rhs.template rtrunc<T::bits>();\n\t\tls_expr = rhs.template trunc<U::bits>();\n\t\treturn *this;\n\t}\n\n\t// A helper that forces the cast to value<>, which allows deduction to work.\n\tCXXRTL_ALWAYS_INLINE\n\tvalue<bits> val() const {\n\t\treturn static_cast<const value<bits> &>(*this);\n\t}\n};\n\n// Base class for expression templates, providing helper methods for operations that are valid on both rvalues and lvalues.\n//\n// Note that expression objects (slices and concatenations) constructed in this way should NEVER be captured because\n// they refer to temporaries that will, in general, only live until the end of the statement. For example, both of\n// these snippets perform use-after-free:\n//\n// const auto &a = val.slice<7,0>().slice<1>();\n// value<1> b = a;\n//\n// auto &&c = val.slice<7,0>().slice<1>();\n// c = value<1>{1u};\n//\n// An easy way to write code using slices and concatenations safely is to follow two simple rules:\n// * Never explicitly name any type except `value<W>` or `const value<W> &`.\n// * Never use a `const auto &` or `auto &&` in any such expression.\n// Then, any code that compiles will be well-defined.\ntemplate<class T>\nstruct expr_base {\n\ttemplate<size_t Stop, size_t Start = Stop>\n\tCXXRTL_ALWAYS_INLINE\n\tslice_expr<const T, Stop, Start> slice() const {\n\t\treturn {*static_cast<const T *>(this)};\n\t}\n\n\ttemplate<size_t Stop, size_t Start = Stop>\n\tCXXRTL_ALWAYS_INLINE\n\tslice_expr<T, Stop, Start> slice() {\n\t\treturn {*static_cast<T *>(this)};\n\t}\n\n\ttemplate<class U>\n\tCXXRTL_ALWAYS_INLINE\n\tconcat_expr<const T, typename std::remove_reference<const U>::type> concat(const U &other) const {\n\t\treturn {*static_cast<const T *>(this), other};\n\t}\n\n\ttemplate<class U>\n\tCXXRTL_ALWAYS_INLINE\n\tconcat_expr<T, typename std::remove_reference<U>::type> concat(U &&other) {\n\t\treturn {*static_cast<T *>(this), other};\n\t}\n};\n\ntemplate<size_t Bits>\nstd::ostream &operator<<(std::ostream &os, const value<Bits> &val) {\n\tauto old_flags = os.flags(std::ios::right);\n\tauto old_width = os.width(0);\n\tauto old_fill = os.fill('0');\n\tos << val.bits << '\\'' << std::hex;\n\tfor (size_t n = val.chunks - 1; n != (size_t)-1; n--) {\n\t\tif (n == val.chunks - 1 && Bits % value<Bits>::chunk::bits != 0)\n\t\t\tos.width((Bits % value<Bits>::chunk::bits + 3) / 4);\n\t\telse\n\t\t\tos.width((value<Bits>::chunk::bits + 3) / 4);\n\t\tos << val.data[n];\n\t}\n\tos.fill(old_fill);\n\tos.width(old_width);\n\tos.flags(old_flags);\n\treturn os;\n}\n\ntemplate<size_t Bits>\nstruct wire {\n\tstatic constexpr size_t bits = Bits;\n\n\tvalue<Bits> curr;\n\tvalue<Bits> next;\n\n\twire() = default;\n\texplicit constexpr wire(const value<Bits> &init) : curr(init), next(init) {}\n\ttemplate<typename... Init>\n\texplicit constexpr wire(Init ...init) : curr{init...}, next{init...} {}\n\n\t// Copying and copy-assigning values is natural. If, however, a value is replaced with a wire,\n\t// e.g. because a module is built with a different optimization level, then existing code could\n\t// unintentionally copy a wire instead, which would create a subtle but serious bug. To make sure\n\t// this doesn't happen, prohibit copying and copy-assigning wires.\n\twire(const wire<Bits> &) = delete;\n\twire<Bits> &operator=(const wire<Bits> &) = delete;\n\n\twire(wire<Bits> &&) = default;\n\twire<Bits> &operator=(wire<Bits> &&) = default;\n\n\ttemplate<class IntegerT>\n\tCXXRTL_ALWAYS_INLINE\n\tIntegerT get() const {\n\t\treturn curr.template get<IntegerT>();\n\t}\n\n\ttemplate<class IntegerT>\n\tCXXRTL_ALWAYS_INLINE\n\tvoid set(IntegerT other) {\n\t\tnext.template set<IntegerT>(other);\n\t}\n\n\t// This method intentionally takes a mandatory argument (to make it more difficult to misuse in\n\t// black box implementations, leading to missed observer events). It is generic over its argument\n\t// to allow the `on_update` method to be non-virtual.\n\ttemplate<class ObserverT>\n\tbool commit(ObserverT &observer) {\n\t\tif (curr != next) {\n\t\t\tobserver.on_update(curr.chunks, curr.data, next.data);\n\t\t\tcurr = next;\n\t\t\treturn true;\n\t\t}\n\t\treturn false;\n\t}\n};\n\ntemplate<size_t Bits>\nstd::ostream &operator<<(std::ostream &os, const wire<Bits> &val) {\n\tos << val.curr;\n\treturn os;\n}\n\ntemplate<size_t Width>\nstruct memory {\n\tconst size_t depth;\n\tstd::unique_ptr<value<Width>[]> data;\n\n\texplicit memory(size_t depth) : depth(depth), data(new value<Width>[depth]) {}\n\n\tmemory(const memory<Width> &) = delete;\n\tmemory<Width> &operator=(const memory<Width> &) = delete;\n\n\tmemory(memory<Width> &&) = default;\n\tmemory<Width> &operator=(memory<Width> &&other) {\n\t\tassert(depth == other.depth);\n\t\tdata = std::move(other.data);\n\t\twrite_queue = std::move(other.write_queue);\n\t\treturn *this;\n\t}\n\n\t// An operator for direct memory reads. May be used at any time during the simulation.\n\tconst value<Width> &operator [](size_t index) const {\n\t\tassert(index < depth);\n\t\treturn data[index];\n\t}\n\n\t// An operator for direct memory writes. May only be used before the simulation is started. If used\n\t// after the simulation is started, the design may malfunction.\n\tvalue<Width> &operator [](size_t index) {\n\t\tassert(index < depth);\n\t\treturn data[index];\n\t}\n\n\t// A simple way to make a writable memory would be to use an array of wires instead of an array of values.\n\t// However, there are two significant downsides to this approach: first, it has large overhead (2× space\n\t// overhead, and O(depth) time overhead during commit); second, it does not simplify handling write port\n\t// priorities. Although in principle write ports could be ordered or conditionally enabled in generated\n\t// code based on their priorities and selected addresses, the feedback arc set problem is computationally\n\t// expensive, and the heuristic based algorithms are not easily modified to guarantee (rather than prefer)\n\t// a particular write port evaluation order.\n\t//\n\t// The approach used here instead is to queue writes into a buffer during the eval phase, then perform\n\t// the writes during the commit phase in the priority order. This approach has low overhead, with both space\n\t// and time proportional to the amount of write ports. Because virtually every memory in a practical design\n\t// has at most two write ports, linear search is used on every write, being the fastest and simplest approach.\n\tstruct write {\n\t\tsize_t index;\n\t\tvalue<Width> val;\n\t\tvalue<Width> mask;\n\t\tint priority;\n\t};\n\tstd::vector<write> write_queue;\n\n\tvoid update(size_t index, const value<Width> &val, const value<Width> &mask, int priority = 0) {\n\t\tassert(index < depth);\n\t\t// Queue up the write while keeping the queue sorted by priority.\n\t\twrite_queue.insert(\n\t\t\tstd::upper_bound(write_queue.begin(), write_queue.end(), priority,\n\t\t\t\t[](const int a, const write& b) { return a < b.priority; }),\n\t\t\twrite { index, val, mask, priority });\n\t}\n\n\t// See the note for `wire::commit()`.\n\ttemplate<class ObserverT>\n\tbool commit(ObserverT &observer) {\n\t\tbool changed = false;\n\t\tfor (const write &entry : write_queue) {\n\t\t\tvalue<Width> elem = data[entry.index];\n\t\t\telem = elem.update(entry.val, entry.mask);\n\t\t\tif (data[entry.index] != elem) {\n\t\t\t\tobserver.on_update(value<Width>::chunks, data[0].data, elem.data, entry.index);\n\t\t\t\tchanged |= true;\n\t\t\t}\n\t\t\tdata[entry.index] = elem;\n\t\t}\n\t\twrite_queue.clear();\n\t\treturn changed;\n\t}\n};\n\nstruct metadata {\n\tconst enum {\n\t\tMISSING = 0,\n\t\tUINT \t= 1,\n\t\tSINT \t= 2,\n\t\tSTRING \t= 3,\n\t\tDOUBLE \t= 4,\n\t} value_type;\n\n\t// In debug mode, using the wrong .as_*() function will assert.\n\t// In release mode, using the wrong .as_*() function will safely return a default value.\n\tconst uint64_t uint_value = 0;\n\tconst int64_t sint_value = 0;\n\tconst std::string string_value = \"\";\n\tconst double double_value = 0.0;\n\n\tmetadata() : value_type(MISSING) {}\n\tmetadata(uint64_t value) : value_type(UINT), uint_value(value) {}\n\tmetadata(int64_t value) : value_type(SINT), sint_value(value) {}\n\tmetadata(const std::string &value) : value_type(STRING), string_value(value) {}\n\tmetadata(const char *value) : value_type(STRING), string_value(value) {}\n\tmetadata(double value) : value_type(DOUBLE), double_value(value) {}\n\n\tmetadata(const metadata &) = default;\n\tmetadata &operator=(const metadata &) = delete;\n\n\tuint64_t as_uint() const {\n\t\tassert(value_type == UINT);\n\t\treturn uint_value;\n\t}\n\n\tint64_t as_sint() const {\n\t\tassert(value_type == SINT);\n\t\treturn sint_value;\n\t}\n\n\tconst std::string &as_string() const {\n\t\tassert(value_type == STRING);\n\t\treturn string_value;\n\t}\n\n\tdouble as_double() const {\n\t\tassert(value_type == DOUBLE);\n\t\treturn double_value;\n\t}\n};\n\ntypedef std::map<std::string, metadata> metadata_map;\n\nstruct performer;\n\n// An object that allows formatting a string lazily.\nstruct lazy_fmt {\n\tvirtual std::string operator() () const = 0;\n};\n\n// An object that can be passed to a `eval()` method in order to act on side effects.\nstruct performer {\n\t// Called by generated formatting code to evaluate a Verilog `$time` expression.\n\tvirtual int64_t vlog_time() const { return 0; }\n\n\t// Called by generated formatting code to evaluate a Verilog `$realtime` expression.\n\tvirtual double vlog_realtime() const { return vlog_time(); }\n\n\t// Called when a `$print` cell is triggered.\n\tvirtual void on_print(const lazy_fmt &formatter, const metadata_map &attributes) {\n\t\tstd::cout << formatter();\n\t}\n};\n\n// An object that can be passed to a `commit()` method in order to produce a replay log of every state change in\n// the simulation. Unlike `performer`, `observer` does not use virtual calls as their overhead is unacceptable, and\n// a comparatively heavyweight template-based solution is justified.\nstruct observer {\n\t// Called when the `commit()` method for a wire is about to update the `chunks` chunks at `base` with `chunks` chunks\n\t// at `value` that have a different bit pattern. It is guaranteed that `chunks` is equal to the wire chunk count and\n\t// `base` points to the first chunk.\n\tvoid on_update(size_t chunks, const chunk_t *base, const chunk_t *value) {}\n\n\t// Called when the `commit()` method for a memory is about to update the `chunks` chunks at `&base[chunks * index]`\n\t// with `chunks` chunks at `value` that have a different bit pattern. It is guaranteed that `chunks` is equal to\n\t// the memory element chunk count and `base` points to the first chunk of the first element of the memory.\n\tvoid on_update(size_t chunks, const chunk_t *base, const chunk_t *value, size_t index) {}\n};\n\n// Must be kept in sync with `struct FmtPart` in kernel/fmt.h!\n// Default member initializers would make this a non-aggregate-type in C++11, so they are commented out.\nstruct fmt_part {\n\tenum {\n\t\tSTRING = 0,\n\t\tINTEGER = 1,\n\t\tCHARACTER = 2,\n\t\tVLOG_TIME = 3,\n\t} type;\n\n\t// STRING type\n\tstd::string str;\n\n\t// INTEGER/CHARACTER types\n\t// + value<Bits> val;\n\n\t// INTEGER/CHARACTER/VLOG_TIME types\n\tenum {\n\t\tRIGHT\t= 0,\n\t\tLEFT\t= 1,\n\t} justify; // = RIGHT;\n\tchar padding; // = '\\0';\n\tsize_t width; // = 0;\n\n\t// INTEGER type\n\tunsigned base; // = 10;\n\tbool signed_; // = false;\n\tbool plus; // = false;\n\n\t// VLOG_TIME type\n\tbool realtime; // = false;\n\t// + int64_t itime;\n\t// + double ftime;\n\n\t// Format the part as a string.\n\t//\n\t// The values of `vlog_time` and `vlog_realtime` are used for Verilog `$time` and `$realtime`, correspondingly.\n\ttemplate<size_t Bits>\n\tstd::string render(value<Bits> val, performer *performer = nullptr)\n\t{\n\t\t// We might want to replace some of these bit() calls with direct\n\t\t// chunk access if it turns out to be slow enough to matter.\n\t\tstd::string buf;\n\t\tswitch (type) {\n\t\t\tcase STRING:\n\t\t\t\treturn str;\n\n\t\t\tcase CHARACTER: {\n\t\t\t\tbuf.reserve(Bits/8);\n\t\t\t\tfor (int i = 0; i < Bits; i += 8) {\n\t\t\t\t\tchar ch = 0;\n\t\t\t\t\tfor (int j = 0; j < 8 && i + j < int(Bits); j++)\n\t\t\t\t\t\tif (val.bit(i + j))\n\t\t\t\t\t\t\tch |= 1 << j;\n\t\t\t\t\tif (ch != 0)\n\t\t\t\t\t\tbuf.append({ch});\n\t\t\t\t}\n\t\t\t\tstd::reverse(buf.begin(), buf.end());\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tcase INTEGER: {\n\t\t\t\tsize_t width = Bits;\n\t\t\t\tif (base != 10) {\n\t\t\t\t\twidth = 0;\n\t\t\t\t\tfor (size_t index = 0; index < Bits; index++)\n\t\t\t\t\t\tif (val.bit(index))\n\t\t\t\t\t\t\twidth = index + 1;\n\t\t\t\t}\n\n\t\t\t\tif (base == 2) {\n\t\t\t\t\tfor (size_t i = width; i > 0; i--)\n\t\t\t\t\t\tbuf += (val.bit(i - 1) ? '1' : '0');\n\t\t\t\t} else if (base == 8 || base == 16) {\n\t\t\t\t\tsize_t step = (base == 16) ? 4 : 3;\n\t\t\t\t\tfor (size_t index = 0; index < width; index += step) {\n\t\t\t\t\t\tuint8_t value = val.bit(index) | (val.bit(index + 1) << 1) | (val.bit(index + 2) << 2);\n\t\t\t\t\t\tif (step == 4)\n\t\t\t\t\t\t\tvalue |= val.bit(index + 3) << 3;\n\t\t\t\t\t\tbuf += \"0123456789abcdef\"[value];\n\t\t\t\t\t}\n\t\t\t\t\tstd::reverse(buf.begin(), buf.end());\n\t\t\t\t} else if (base == 10) {\n\t\t\t\t\tbool negative = signed_ && val.is_neg();\n\t\t\t\t\tif (negative)\n\t\t\t\t\t\tval = val.neg();\n\t\t\t\t\tif (val.is_zero())\n\t\t\t\t\t\tbuf += '0';\n\t\t\t\t\tvalue<(Bits > 4 ? Bits : 4)> xval = val.template zext<(Bits > 4 ? Bits : 4)>();\n\t\t\t\t\twhile (!xval.is_zero()) {\n\t\t\t\t\t\tvalue<(Bits > 4 ? Bits : 4)> quotient, remainder;\n\t\t\t\t\t\tif (Bits >= 4)\n\t\t\t\t\t\t\tstd::tie(quotient, remainder) = xval.udivmod(value<(Bits > 4 ? Bits : 4)>{10u});\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tstd::tie(quotient, remainder) = std::make_pair(value<(Bits > 4 ? Bits : 4)>{0u}, xval);\n\t\t\t\t\t\tbuf += '0' + remainder.template trunc<4>().template get<uint8_t>();\n\t\t\t\t\t\txval = quotient;\n\t\t\t\t\t}\n\t\t\t\t\tif (negative || plus)\n\t\t\t\t\t\tbuf += negative ? '-' : '+';\n\t\t\t\t\tstd::reverse(buf.begin(), buf.end());\n\t\t\t\t} else assert(false && \"Unsupported base for fmt_part\");\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tcase VLOG_TIME: {\n\t\t\t\tif (performer) {\n\t\t\t\t\tbuf = realtime ? std::to_string(performer->vlog_realtime()) : std::to_string(performer->vlog_time());\n\t\t\t\t} else {\n\t\t\t\t\tbuf = realtime ? std::to_string(0.0) : std::to_string(0);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tstd::string str;\n\t\tassert(width == 0 || padding != '\\0');\n\t\tif (justify == RIGHT && buf.size() < width) {\n\t\t\tsize_t pad_width = width - buf.size();\n\t\t\tif (padding == '0' && (buf.front() == '+' || buf.front() == '-')) {\n\t\t\t\tstr += buf.front();\n\t\t\t\tbuf.erase(0, 1);\n\t\t\t}\n\t\t\tstr += std::string(pad_width, padding);\n\t\t}\n\t\tstr += buf;\n\t\tif (justify == LEFT && buf.size() < width)\n\t\t\tstr += std::string(width - buf.size(), padding);\n\t\treturn str;\n\t}\n};\n\n// Tag class to disambiguate values/wires and their aliases.\nstruct debug_alias {};\n\n// Tag declaration to disambiguate values and debug outlines.\nusing debug_outline = ::_cxxrtl_outline;\n\n// This structure is intended for consumption via foreign function interfaces, like Python's ctypes.\n// Because of this it uses a C-style layout that is easy to parse rather than more idiomatic C++.\n//\n// To avoid violating strict aliasing rules, this structure has to be a subclass of the one used\n// in the C API, or it would not be possible to cast between the pointers to these.\n//\n// The `attrs` member cannot be owned by this structure because a `cxxrtl_object` can be created\n// from external C code.\nstruct debug_item : ::cxxrtl_object {\n\t// Object types.\n\tenum : uint32_t {\n\t\tVALUE = CXXRTL_VALUE,\n\t\tWIRE = CXXRTL_WIRE,\n\t\tMEMORY = CXXRTL_MEMORY,\n\t\tALIAS = CXXRTL_ALIAS,\n\t\tOUTLINE = CXXRTL_OUTLINE,\n\t};\n\n\t// Object flags.\n\tenum : uint32_t {\n\t\tINPUT = CXXRTL_INPUT,\n\t\tOUTPUT = CXXRTL_OUTPUT,\n\t\tINOUT = CXXRTL_INOUT,\n\t\tDRIVEN_SYNC = CXXRTL_DRIVEN_SYNC,\n\t\tDRIVEN_COMB = CXXRTL_DRIVEN_COMB,\n\t\tUNDRIVEN = CXXRTL_UNDRIVEN,\n\t};\n\n\tdebug_item(const ::cxxrtl_object &object) : cxxrtl_object(object) {}\n\n\ttemplate<size_t Bits>\n\tdebug_item(value<Bits> &item, size_t lsb_offset = 0, uint32_t flags_ = 0) {\n\t\tstatic_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = VALUE;\n\t\tflags = flags_;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = item.data;\n\t\tnext = item.data;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(const value<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = VALUE;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.data);\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(wire<Bits> &item, size_t lsb_offset = 0, uint32_t flags_ = 0) {\n\t\tstatic_assert(sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&\n\t\t sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"wire<Bits> is not compatible with C layout\");\n\t\ttype = WIRE;\n\t\tflags = flags_;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = item.curr.data;\n\t\tnext = item.next.data;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Width>\n\tdebug_item(memory<Width> &item, size_t zero_offset = 0) {\n\t\tstatic_assert(sizeof(item.data[0]) == value<Width>::chunks * sizeof(chunk_t),\n\t\t \"memory<Width> is not compatible with C layout\");\n\t\ttype = MEMORY;\n\t\tflags = 0;\n\t\twidth = Width;\n\t\tlsb_at = 0;\n\t\tdepth = item.depth;\n\t\tzero_at = zero_offset;\n\t\tcurr = item.data ? item.data[0].data : nullptr;\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(debug_alias, const value<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = ALIAS;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.data);\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(debug_alias, const wire<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&\n\t\t sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"wire<Bits> is not compatible with C layout\");\n\t\ttype = ALIAS;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.curr.data);\n\t\tnext = nullptr;\n\t\toutline = nullptr;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits>\n\tdebug_item(debug_outline &group, const value<Bits> &item, size_t lsb_offset = 0) {\n\t\tstatic_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),\n\t\t \"value<Bits> is not compatible with C layout\");\n\t\ttype = OUTLINE;\n\t\tflags = DRIVEN_COMB;\n\t\twidth = Bits;\n\t\tlsb_at = lsb_offset;\n\t\tdepth = 1;\n\t\tzero_at = 0;\n\t\tcurr = const_cast<chunk_t*>(item.data);\n\t\tnext = nullptr;\n\t\toutline = &group;\n\t\tattrs = nullptr;\n\t}\n\n\ttemplate<size_t Bits, class IntegerT>\n\tIntegerT get() const {\n\t\tassert(width == Bits && depth == 1);\n\t\tvalue<Bits> item;\n\t\tstd::copy(curr, curr + value<Bits>::chunks, item.data);\n\t\treturn item.template get<IntegerT>();\n\t}\n\n\ttemplate<size_t Bits, class IntegerT>\n\tvoid set(IntegerT other) const {\n\t\tassert(width == Bits && depth == 1);\n\t\tvalue<Bits> item;\n\t\titem.template set<IntegerT>(other);\n\t\tstd::copy(item.data, item.data + value<Bits>::chunks, next);\n\t}\n};\nstatic_assert(std::is_standard_layout<debug_item>::value, \"debug_item is not compatible with C layout\");\n\n} // namespace cxxrtl\n\ntypedef struct _cxxrtl_attr_set {\n\tcxxrtl::metadata_map map;\n} *cxxrtl_attr_set;\n\nnamespace cxxrtl {\n\n// Representation of an attribute set in the C++ interface.\nusing debug_attrs = ::_cxxrtl_attr_set;\n\nstruct debug_items {\n\tstd::map<std::string, std::vector<debug_item>> table;\n\tstd::map<std::string, std::unique_ptr<debug_attrs>> attrs_table;\n\n\tvoid add(const std::string &name, debug_item &&item, metadata_map &&item_attrs = {}) {\n\t\tstd::unique_ptr<debug_attrs> &attrs = attrs_table[name];\n\t\tif (attrs.get() == nullptr)\n\t\t\tattrs = std::unique_ptr<debug_attrs>(new debug_attrs);\n\t\tfor (auto attr : item_attrs)\n\t\t\tattrs->map.insert(attr);\n\t\titem.attrs = attrs.get();\n\t\tstd::vector<debug_item> &parts = table[name];\n\t\tparts.emplace_back(item);\n\t\tstd::sort(parts.begin(), parts.end(),\n\t\t\t[](const debug_item &a, const debug_item &b) {\n\t\t\t\treturn a.lsb_at < b.lsb_at;\n\t\t\t});\n\t}\n\n\tsize_t count(const std::string &name) const {\n\t\tif (table.count(name) == 0)\n\t\t\treturn 0;\n\t\treturn table.at(name).size();\n\t}\n\n\tconst std::vector<debug_item> &parts_at(const std::string &name) const {\n\t\treturn table.at(name);\n\t}\n\n\tconst debug_item &at(const std::string &name) const {\n\t\tconst std::vector<debug_item> &parts = table.at(name);\n\t\tassert(parts.size() == 1);\n\t\treturn parts.at(0);\n\t}\n\n\tconst debug_item &operator [](const std::string &name) const {\n\t\treturn at(name);\n\t}\n\n\tconst metadata_map &attrs(const std::string &name) const {\n\t\treturn attrs_table.at(name)->map;\n\t}\n};\n\n// Tag class to disambiguate the default constructor used by the toplevel module that calls reset(),\n// and the constructor of interior modules that should not call it.\nstruct interior {};\n\nstruct module {\n\tmodule() {}\n\tvirtual ~module() {}\n\n\t// Modules with black boxes cannot be copied. Although not all designs include black boxes,\n\t// delete the copy constructor and copy assignment operator to make sure that any downstream\n\t// code that manipulates modules doesn't accidentally depend on their availability.\n\tmodule(const module &) = delete;\n\tmodule &operator=(const module &) = delete;\n\n\tmodule(module &&) = default;\n\tmodule &operator=(module &&) = default;\n\n\tvirtual void reset() = 0;\n\n\tvirtual bool eval(performer *performer = nullptr) = 0;\n\tvirtual bool commit() = 0; // commit observer isn't available since it avoids virtual calls\n\n\tsize_t step(performer *performer = nullptr) {\n\t\tsize_t deltas = 0;\n\t\tbool converged = false;\n\t\tdo {\n\t\t\tconverged = eval(performer);\n\t\t\tdeltas++;\n\t\t} while (commit() && !converged);\n\t\treturn deltas;\n\t}\n\n\tvirtual void debug_info(debug_items &items, std::string path = \"\") {\n\t\t(void)items, (void)path;\n\t}\n};\n\n} // namespace cxxrtl\n\n// Internal structures used to communicate with the implementation of the C interface.\n\ntypedef struct _cxxrtl_toplevel {\n\tstd::unique_ptr<cxxrtl::module> module;\n} *cxxrtl_toplevel;\n\ntypedef struct _cxxrtl_outline {\n\tstd::function<void()> eval;\n} *cxxrtl_outline;\n\n// Definitions of internal Yosys cells. Other than the functions in this namespace, CXXRTL is fully generic\n// and indepenent of Yosys implementation details.\n//\n// The `write_cxxrtl` pass translates internal cells (cells with names that start with `$`) to calls of these\n// functions. All of Yosys arithmetic and logical cells perform sign or zero extension on their operands,\n// whereas basic operations on arbitrary width values require operands to be of the same width. These functions\n// bridge the gap by performing the necessary casts. They are named similar to `cell_A[B]`, where A and B are `u`\n// if the corresponding operand is unsigned, and `s` if it is signed.\nnamespace cxxrtl_yosys {\n\nusing namespace cxxrtl;\n\n// std::max isn't constexpr until C++14 for no particular reason (it's an oversight), so we define our own.\ntemplate<class T>\nCXXRTL_ALWAYS_INLINE\nconstexpr T max(const T &a, const T &b) {\n\treturn a > b ? a : b;\n}\n\n// Logic operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> logic_not(const value<BitsA> &a) {\n\treturn value<BitsY> { a ? 0u : 1u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> logic_and(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn value<BitsY> { (bool(a) && bool(b)) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> logic_or(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn value<BitsY> { (bool(a) || bool(b)) ? 1u : 0u };\n}\n\n// Reduction operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_and(const value<BitsA> &a) {\n\treturn value<BitsY> { a.bit_not().is_zero() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_or(const value<BitsA> &a) {\n\treturn value<BitsY> { a ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_xor(const value<BitsA> &a) {\n\treturn value<BitsY> { (a.ctpop() % 2) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_xnor(const value<BitsA> &a) {\n\treturn value<BitsY> { (a.ctpop() % 2) ? 0u : 1u };\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> reduce_bool(const value<BitsA> &a) {\n\treturn value<BitsY> { a ? 1u : 0u };\n}\n\n// Bitwise operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> not_u(const value<BitsA> &a) {\n\treturn a.template zcast<BitsY>().bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> not_s(const value<BitsA> &a) {\n\treturn a.template scast<BitsY>().bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> and_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_and(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> and_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_and(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> or_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_or(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> or_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_or(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_xor(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_xor(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xnor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().bit_xor(b.template zcast<BitsY>()).bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> xnor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().bit_xor(b.template scast<BitsY>()).bit_not();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shl_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shl_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshl_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshl_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().shl(b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shr_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.shr(b).template zcast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shr_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.shr(b).template scast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshr_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.shr(b).template zcast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sshr_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.sshr(b).template scast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shr_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shr_su<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_us(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn b.is_neg() ? shl_uu<BitsY>(a, b.template sext<BitsB + 1>().neg()) : shr_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shift_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn b.is_neg() ? shl_su<BitsY>(a, b.template sext<BitsB + 1>().neg()) : shr_su<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_su(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_su<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_us(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_us<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> shiftx_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn shift_ss<BitsY>(a, b);\n}\n\n// Comparison operations\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eq_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template zext<BitsExt>() == b.template zext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eq_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template sext<BitsExt>() == b.template sext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ne_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template zext<BitsExt>() != b.template zext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ne_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY>{ a.template sext<BitsExt>() != b.template sext<BitsExt>() ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eqx_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn eq_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> eqx_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn eq_ss<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> nex_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn ne_uu<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> nex_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn ne_ss<BitsY>(a, b);\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> gt_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { b.template zext<BitsExt>().ucmp(a.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> gt_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { b.template sext<BitsExt>().scmp(a.template sext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ge_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !a.template zext<BitsExt>().ucmp(b.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> ge_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !a.template sext<BitsExt>().scmp(b.template sext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> lt_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { a.template zext<BitsExt>().ucmp(b.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> lt_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { a.template sext<BitsExt>().scmp(b.template sext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> le_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !b.template zext<BitsExt>().ucmp(a.template zext<BitsExt>()) ? 1u : 0u };\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> le_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsExt = max(BitsA, BitsB);\n\treturn value<BitsY> { !b.template sext<BitsExt>().scmp(a.template sext<BitsExt>()) ? 1u : 0u };\n}\n\n// Arithmetic operations\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> pos_u(const value<BitsA> &a) {\n\treturn a.template zcast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> pos_s(const value<BitsA> &a) {\n\treturn a.template scast<BitsY>();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> neg_u(const value<BitsA> &a) {\n\treturn a.template zcast<BitsY>().neg();\n}\n\ntemplate<size_t BitsY, size_t BitsA>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> neg_s(const value<BitsA> &a) {\n\treturn a.template scast<BitsY>().neg();\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> add_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().add(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> add_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().add(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sub_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template zcast<BitsY>().sub(b.template zcast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> sub_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().sub(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mul_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t BitsM = BitsA >= BitsB ? BitsA : BitsB;\n\treturn a.template zcast<BitsM>().template mul<BitsY>(b.template zcast<BitsM>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mul_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn a.template scast<BitsY>().template mul<BitsY>(b.template scast<BitsY>());\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nstd::pair<value<BitsY>, value<BitsY>> divmod_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t Bits = max(BitsY, max(BitsA, BitsB));\n\tvalue<Bits> quotient;\n\tvalue<Bits> remainder;\n\tvalue<Bits> dividend = a.template zext<Bits>();\n\tvalue<Bits> divisor = b.template zext<Bits>();\n\tstd::tie(quotient, remainder) = dividend.udivmod(divisor);\n\treturn {quotient.template trunc<BitsY>(), remainder.template trunc<BitsY>()};\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nstd::pair<value<BitsY>, value<BitsY>> divmod_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tconstexpr size_t Bits = max(BitsY, max(BitsA, BitsB));\n\tvalue<Bits> quotient;\n\tvalue<Bits> remainder;\n\tvalue<Bits> dividend = a.template sext<Bits>();\n\tvalue<Bits> divisor = b.template sext<Bits>();\n\tstd::tie(quotient, remainder) = dividend.sdivmod(divisor);\n\treturn {quotient.template trunc<BitsY>(), remainder.template trunc<BitsY>()};\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> div_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).first;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> div_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_ss<BitsY>(a, b).first;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mod_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).second;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> mod_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_ss<BitsY>(a, b).second;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> modfloor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).second;\n}\n\n// GHDL Modfloor operator. Returns r=a mod b, such that r has the same sign as b and\n// a=b*N+r where N is some integer\n// In practical terms, when a and b have different signs and the remainder returned by divmod_ss is not 0\n// then return the remainder + b\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> modfloor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tvalue<BitsY> r;\n\tr = divmod_ss<BitsY>(a, b).second;\n\tif((b.is_neg() != a.is_neg()) && !r.is_zero())\n\t\treturn add_ss<BitsY>(b, r);\n\treturn r;\n}\n\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> divfloor_uu(const value<BitsA> &a, const value<BitsB> &b) {\n\treturn divmod_uu<BitsY>(a, b).first;\n}\n\n// Divfloor. Similar to above: returns q=a//b, where q has the sign of a*b and a=b*q+N.\n// In other words, returns (truncating) a/b, except if a and b have different signs\n// and there's non-zero remainder, subtract one more towards floor.\ntemplate<size_t BitsY, size_t BitsA, size_t BitsB>\nCXXRTL_ALWAYS_INLINE\nvalue<BitsY> divfloor_ss(const value<BitsA> &a, const value<BitsB> &b) {\n\tvalue<BitsY> q, r;\n\tstd::tie(q, r) = divmod_ss<BitsY>(a, b);\n\tif ((b.is_neg() != a.is_neg()) && !r.is_zero())\n\t\treturn sub_uu<BitsY>(q, value<1> { 1u });\n\treturn q;\n\n}\n\n// Memory helper\nstruct memory_index {\n\tbool valid;\n\tsize_t index;\n\n\ttemplate<size_t BitsAddr>\n\tmemory_index(const value<BitsAddr> &addr, size_t offset, size_t depth) {\n\t\tstatic_assert(value<BitsAddr>::chunks <= 1, \"memory address is too wide\");\n\t\tsize_t offset_index = addr.data[0];\n\n\t\tvalid = (offset_index >= offset && offset_index < offset + depth);\n\t\tindex = offset_index - offset;\n\t}\n};\n\n} // namespace cxxrtl_yosys\n\n#endif\n",
136
136
  "cxxrtl_vcd.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef CXXRTL_VCD_H\n#define CXXRTL_VCD_H\n\n#include <cxxrtl/cxxrtl.h>\n\nnamespace cxxrtl {\n\nclass vcd_writer {\n\tstruct variable {\n\t\tsize_t ident;\n\t\tsize_t width;\n\t\tchunk_t *curr;\n\t\tsize_t cache_offset;\n\t\tdebug_outline *outline;\n\t\tbool *outline_warm;\n\t};\n\n\tstd::vector<std::string> current_scope;\n\tstd::map<debug_outline*, bool> outlines;\n\tstd::vector<variable> variables;\n\tstd::vector<chunk_t> cache;\n\tstd::map<chunk_t*, size_t> aliases;\n\tbool streaming = false;\n\n\tvoid emit_timescale(unsigned number, const std::string &unit) {\n\t\tassert(!streaming);\n\t\tassert(number == 1 || number == 10 || number == 100);\n\t\tassert(unit == \"s\" || unit == \"ms\" || unit == \"us\" ||\n\t\t unit == \"ns\" || unit == \"ps\" || unit == \"fs\");\n\t\tbuffer += \"$timescale \" + std::to_string(number) + \" \" + unit + \" $end\\n\";\n\t}\n\n\tvoid emit_scope(const std::vector<std::string> &scope) {\n\t\tassert(!streaming);\n\t\twhile (current_scope.size() > scope.size() ||\n\t\t (current_scope.size() > 0 &&\n\t\t\tcurrent_scope[current_scope.size() - 1] != scope[current_scope.size() - 1])) {\n\t\t\tbuffer += \"$upscope $end\\n\";\n\t\t\tcurrent_scope.pop_back();\n\t\t}\n\t\twhile (current_scope.size() < scope.size()) {\n\t\t\tbuffer += \"$scope module \" + scope[current_scope.size()] + \" $end\\n\";\n\t\t\tcurrent_scope.push_back(scope[current_scope.size()]);\n\t\t}\n\t}\n\n\tvoid emit_ident(size_t ident) {\n\t\tdo {\n\t\t\tbuffer += '!' + ident % 94; // \"base94\"\n\t\t\tident /= 94;\n\t\t} while (ident != 0);\n\t}\n\n\tvoid emit_name(const std::string &name) {\n\t\tfor (char c : name) {\n\t\t\tif (c == ':') {\n\t\t\t\t// Due to a bug, GTKWave cannot parse a colon in the variable name, causing the VCD file\n\t\t\t\t// to be unreadable. It cannot be escaped either, so replace it with the sideways colon.\n\t\t\t\tbuffer += \"..\";\n\t\t\t} else {\n\t\t\t\tbuffer += c;\n\t\t\t}\n\t\t}\n\t}\n\n\tvoid emit_var(const variable &var, const std::string &type, const std::string &name,\n\t size_t lsb_at, bool multipart) {\n\t\tassert(!streaming);\n\t\tbuffer += \"$var \" + type + \" \" + std::to_string(var.width) + \" \";\n\t\temit_ident(var.ident);\n\t\tbuffer += \" \";\n\t\temit_name(name);\n\t\tif (multipart || name.back() == ']' || lsb_at != 0) {\n\t\t\tif (var.width == 1)\n\t\t\t\tbuffer += \" [\" + std::to_string(lsb_at) + \"]\";\n\t\t\telse\n\t\t\t\tbuffer += \" [\" + std::to_string(lsb_at + var.width - 1) + \":\" + std::to_string(lsb_at) + \"]\";\n\t\t}\n\t\tbuffer += \" $end\\n\";\n\t}\n\n\tvoid emit_enddefinitions() {\n\t\tassert(!streaming);\n\t\tbuffer += \"$enddefinitions $end\\n\";\n\t\tstreaming = true;\n\t}\n\n\tvoid emit_time(uint64_t timestamp) {\n\t\tassert(streaming);\n\t\tbuffer += \"#\" + std::to_string(timestamp) + \"\\n\";\n\t}\n\n\tvoid emit_scalar(const variable &var) {\n\t\tassert(streaming);\n\t\tassert(var.width == 1);\n\t\tbuffer += (*var.curr ? '1' : '0');\n\t\temit_ident(var.ident);\n\t\tbuffer += '\\n';\n\t}\n\n\tvoid emit_vector(const variable &var) {\n\t\tassert(streaming);\n\t\tbuffer += 'b';\n\t\tfor (size_t bit = var.width - 1; bit != (size_t)-1; bit--) {\n\t\t\tbool bit_curr = var.curr[bit / (8 * sizeof(chunk_t))] & (1 << (bit % (8 * sizeof(chunk_t))));\n\t\t\tbuffer += (bit_curr ? '1' : '0');\n\t\t}\n\t\tbuffer += ' ';\n\t\temit_ident(var.ident);\n\t\tbuffer += '\\n';\n\t}\n\n\tvoid reset_outlines() {\n\t\tfor (auto &outline_it : outlines)\n\t\t\toutline_it.second = /*warm=*/(outline_it.first == nullptr);\n\t}\n\n\tvariable &register_variable(size_t width, chunk_t *curr, bool constant = false, debug_outline *outline = nullptr) {\n\t\tif (aliases.count(curr)) {\n\t\t\treturn variables[aliases[curr]];\n\t\t} else {\n\t\t\tauto outline_it = outlines.emplace(outline, /*warm=*/(outline == nullptr)).first;\n\t\t\tconst size_t chunks = (width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);\n\t\t\taliases[curr] = variables.size();\n\t\t\tif (constant) {\n\t\t\t\tvariables.emplace_back(variable { variables.size(), width, curr, (size_t)-1, outline_it->first, &outline_it->second });\n\t\t\t} else {\n\t\t\t\tvariables.emplace_back(variable { variables.size(), width, curr, cache.size(), outline_it->first, &outline_it->second });\n\t\t\t\tcache.insert(cache.end(), &curr[0], &curr[chunks]);\n\t\t\t}\n\t\t\treturn variables.back();\n\t\t}\n\t}\n\n\tbool test_variable(const variable &var) {\n\t\tif (var.cache_offset == (size_t)-1)\n\t\t\treturn false; // constant\n\t\tif (!*var.outline_warm) {\n\t\t\tvar.outline->eval();\n\t\t\t*var.outline_warm = true;\n\t\t}\n\t\tconst size_t chunks = (var.width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);\n\t\tif (std::equal(&var.curr[0], &var.curr[chunks], &cache[var.cache_offset])) {\n\t\t\treturn false;\n\t\t} else {\n\t\t\tstd::copy(&var.curr[0], &var.curr[chunks], &cache[var.cache_offset]);\n\t\t\treturn true;\n\t\t}\n\t}\n\n\tstatic std::vector<std::string> split_hierarchy(const std::string &hier_name) {\n\t\tstd::vector<std::string> hierarchy;\n\t\tsize_t prev = 0;\n\t\twhile (true) {\n\t\t\tsize_t curr = hier_name.find_first_of(' ', prev);\n\t\t\tif (curr == std::string::npos) {\n\t\t\t\thierarchy.push_back(hier_name.substr(prev));\n\t\t\t\tbreak;\n\t\t\t} else {\n\t\t\t\thierarchy.push_back(hier_name.substr(prev, curr - prev));\n\t\t\t\tprev = curr + 1;\n\t\t\t}\n\t\t}\n\t\treturn hierarchy;\n\t}\n\npublic:\n\tstd::string buffer;\n\n\tvoid timescale(unsigned number, const std::string &unit) {\n\t\temit_timescale(number, unit);\n\t}\n\n\tvoid add(const std::string &hier_name, const debug_item &item, bool multipart = false) {\n\t\tstd::vector<std::string> scope = split_hierarchy(hier_name);\n\t\tstd::string name = scope.back();\n\t\tscope.pop_back();\n\n\t\temit_scope(scope);\n\t\tswitch (item.type) {\n\t\t\t// Not the best naming but oh well...\n\t\t\tcase debug_item::VALUE:\n\t\t\t\temit_var(register_variable(item.width, item.curr, /*constant=*/item.next == nullptr),\n\t\t\t\t \"wire\", name, item.lsb_at, multipart);\n\t\t\t\tbreak;\n\t\t\tcase debug_item::WIRE:\n\t\t\t\temit_var(register_variable(item.width, item.curr),\n\t\t\t\t \"reg\", name, item.lsb_at, multipart);\n\t\t\t\tbreak;\n\t\t\tcase debug_item::MEMORY: {\n\t\t\t\tconst size_t stride = (item.width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);\n\t\t\t\tfor (size_t index = 0; index < item.depth; index++) {\n\t\t\t\t\tchunk_t *nth_curr = &item.curr[stride * index];\n\t\t\t\t\tstd::string nth_name = name + '[' + std::to_string(index) + ']';\n\t\t\t\t\temit_var(register_variable(item.width, nth_curr),\n\t\t\t\t\t \"reg\", nth_name, item.lsb_at, multipart);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tcase debug_item::ALIAS:\n\t\t\t\t// Like VALUE, but, even though `item.next == nullptr` always holds, the underlying value\n\t\t\t\t// can actually change, and must be tracked. In most cases the VCD identifier will be\n\t\t\t\t// unified with the aliased reg, but we should handle the case where only the alias is\n\t\t\t\t// added to the VCD writer, too.\n\t\t\t\temit_var(register_variable(item.width, item.curr),\n\t\t\t\t \"wire\", name, item.lsb_at, multipart);\n\t\t\t\tbreak;\n\t\t\tcase debug_item::OUTLINE:\n\t\t\t\temit_var(register_variable(item.width, item.curr, /*constant=*/false, item.outline),\n\t\t\t\t \"wire\", name, item.lsb_at, multipart);\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\ttemplate<class Filter>\n\tvoid add(const debug_items &items, const Filter &filter) {\n\t\t// `debug_items` is a map, so the items are already sorted in an order optimal for emitting\n\t\t// VCD scope sections.\n\t\tfor (auto &it : items.table)\n\t\t\tfor (auto &part : it.second)\n\t\t\t\tif (filter(it.first, part))\n\t\t\t\t\tadd(it.first, part, it.second.size() > 1);\n\t}\n\n\tvoid add(const debug_items &items) {\n\t\tthis->add(items, [](const std::string &, const debug_item &) {\n\t\t\treturn true;\n\t\t});\n\t}\n\n\tvoid add_without_memories(const debug_items &items) {\n\t\tthis->add(items, [](const std::string &, const debug_item &item) {\n\t\t\treturn item.type != debug_item::MEMORY;\n\t\t});\n\t}\n\n\tvoid sample(uint64_t timestamp) {\n\t\tbool first_sample = !streaming;\n\t\tif (first_sample) {\n\t\t\temit_scope({});\n\t\t\temit_enddefinitions();\n\t\t}\n\t\treset_outlines();\n\t\temit_time(timestamp);\n\t\tfor (auto var : variables)\n\t\t\tif (test_variable(var) || first_sample) {\n\t\t\t\tif (var.width == 1)\n\t\t\t\t\temit_scalar(var);\n\t\t\t\telse\n\t\t\t\t\temit_vector(var);\n\t\t\t}\n\t}\n};\n\n}\n\n#endif\n",
137
137
  },
138
138
  },
@@ -161,7 +161,7 @@ export const filesystem = {
161
161
  "ff.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FF_H\n#define FF_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/ffinit.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// Describes a flip-flop or a latch.\n//\n// If has_gclk, this is a formal verification FF with implicit global clock:\n// Q is simply previous cycle's D. Additionally if is_anyinit is true, this is\n// an $anyinit cell which always has an undefined initialization value. Note\n// that $anyinit is not considered to be among the FF celltypes, so a pass has\n// to explicitly opt-in to process $anyinit cells with FfData.\n//\n// Otherwise, the FF/latch can have any number of features selected by has_*\n// attributes that determine Q's value (in order of decreasing priority):\n//\n// - on start, register is initialized to val_init\n// - if has_sr is present:\n// - sig_clr is per-bit async clear, and sets the corresponding bit to 0\n// if active\n// - sig_set is per-bit async set, and sets the corresponding bit to 1\n// if active\n// - if has_arst is present:\n// - sig_arst is whole-reg async reset, and sets the whole register to val_arst\n// - if has_aload is present:\n// - sig_aload is whole-reg async load (aka latch gate enable), and sets the whole\n// register to sig_ad\n// - if has_clk is present, and we're currently on a clock edge:\n// - if has_ce is present and ce_over_srst is true:\n// - ignore clock edge (don't change value) unless sig_ce is active\n// - if has_srst is present:\n// - sig_srst is whole-reg sync reset and sets the register to val_srst\n// - if has_ce is present and ce_over_srst is false:\n// - ignore clock edge (don't change value) unless sig_ce is active\n// - set whole reg to sig_d\n// - if nothing of the above applies, the reg value remains unchanged\n//\n// Since the yosys FF cell library isn't fully generic, not all combinations\n// of the features above can be supported:\n//\n// - only one of has_srst, has_arst, has_sr can be used\n// - if has_clk is used together with has_aload, then has_srst, has_arst,\n// has_sr cannot be used\n//\n// The valid feature combinations are thus:\n//\n// - has_clk + optional has_ce [dff/dffe]\n// - has_clk + optional has_ce + has_arst [adff/adffe]\n// - has_clk + optional has_ce + has_aload [aldff/aldffe]\n// - has_clk + optional has_ce + has_sr [dffsr/dffsre]\n// - has_clk + optional has_ce + has_srst [sdff/sdffe/sdffce]\n// - has_aload [dlatch]\n// - has_aload + has_arst [adlatch]\n// - has_aload + has_sr [dlatchsr]\n// - has_sr [sr]\n// - has_arst [does not correspond to a native cell, represented as dlatch with const D input]\n// - empty set [not a cell — will be emitted as a simple direct connection]\n\nstruct FfData {\n\tModule *module;\n\tFfInitVals *initvals;\n\tCell *cell;\n\tIdString name;\n\t// The FF output.\n\tSigSpec sig_q;\n\t// The sync data input, present if has_clk or has_gclk.\n\tSigSpec sig_d;\n\t// The async data input, present if has_aload.\n\tSigSpec sig_ad;\n\t// The sync clock, present if has_clk.\n\tSigSpec sig_clk;\n\t// The clock enable, present if has_ce.\n\tSigSpec sig_ce;\n\t// The async load enable, present if has_aload.\n\tSigSpec sig_aload;\n\t// The async reset, preset if has_arst.\n\tSigSpec sig_arst;\n\t// The sync reset, preset if has_srst.\n\tSigSpec sig_srst;\n\t// The async clear (per-lane), present if has_sr.\n\tSigSpec sig_clr;\n\t// The async set (per-lane), present if has_sr.\n\tSigSpec sig_set;\n\t// True if this is a clocked (edge-sensitive) flip-flop.\n\tbool has_clk;\n\t// True if this is a $ff, exclusive with every other has_*.\n\tbool has_gclk;\n\t// True if this FF has a clock enable. Depends on has_clk.\n\tbool has_ce;\n\t// True if this FF has async load function — this includes D latches.\n\t// If this and has_clk are both set, has_arst and has_sr cannot be set.\n\tbool has_aload;\n\t// True if this FF has sync set/reset. Depends on has_clk, exclusive\n\t// with has_arst, has_sr, has_aload.\n\tbool has_srst;\n\t// True if this FF has async set/reset. Exclusive with has_srst,\n\t// has_sr. If this and has_clk are both set, has_aload cannot be set.\n\tbool has_arst;\n\t// True if this FF has per-bit async set + clear. Exclusive with\n\t// has_srst, has_arst. If this and has_clk are both set, has_aload\n\t// cannot be set.\n\tbool has_sr;\n\t// If has_ce and has_srst are both set, determines their relative\n\t// priorities: if true, inactive ce disables srst; if false, srst\n\t// operates independent of ce.\n\tbool ce_over_srst;\n\t// True if this FF is a fine cell, false if it is a coarse cell.\n\t// If true, width must be 1.\n\tbool is_fine;\n\t// True if this FF is an $anyinit cell. Depends on has_gclk.\n\tbool is_anyinit;\n\t// Polarities, corresponding to sig_*. True means active-high, false\n\t// means active-low.\n\tbool pol_clk;\n\tbool pol_ce;\n\tbool pol_aload;\n\tbool pol_arst;\n\tbool pol_srst;\n\tbool pol_clr;\n\tbool pol_set;\n\t// The value loaded by sig_arst.\n\tConst val_arst;\n\t// The value loaded by sig_srst.\n\tConst val_srst;\n\t// The initial value at power-up.\n\tConst val_init;\n\t// The FF data width in bits.\n\tint width;\n\tdict<IdString, Const> attributes;\n\n\tFfData(Module *module = nullptr, FfInitVals *initvals = nullptr, IdString name = IdString()) : module(module), initvals(initvals), cell(nullptr), name(name) {\n\t\twidth = 0;\n\t\thas_clk = false;\n\t\thas_gclk = false;\n\t\thas_ce = false;\n\t\thas_aload = false;\n\t\thas_srst = false;\n\t\thas_arst = false;\n\t\thas_sr = false;\n\t\tce_over_srst = false;\n\t\tis_fine = false;\n\t\tis_anyinit = false;\n\t\tpol_clk = false;\n\t\tpol_aload = false;\n\t\tpol_ce = false;\n\t\tpol_arst = false;\n\t\tpol_srst = false;\n\t\tpol_clr = false;\n\t\tpol_set = false;\n\t}\n\n\tFfData(FfInitVals *initvals, Cell *cell_);\n\n\t// Returns a FF identical to this one, but only keeping bit indices from the argument.\n\tFfData slice(const std::vector<int> &bits);\n\n\tvoid add_dummy_ce();\n\tvoid add_dummy_srst();\n\tvoid add_dummy_arst();\n\tvoid add_dummy_aload();\n\tvoid add_dummy_sr();\n\tvoid add_dummy_clk();\n\n\tvoid arst_to_aload();\n\tvoid arst_to_sr();\n\n\tvoid aload_to_sr();\n\n\t// Given a FF with both has_ce and has_srst, sets ce_over_srst to the given value and\n\t// fixes up control signals appropriately to preserve semantics.\n\tvoid convert_ce_over_srst(bool val);\n\n\tvoid unmap_ce();\n\tvoid unmap_srst();\n\n\tvoid unmap_ce_srst() {\n\t\tunmap_ce();\n\t\tunmap_srst();\n\t}\n\n\tCell *emit();\n\n\t// Removes init attribute from the Q output, but keeps val_init unchanged.\n\t// It will be automatically reattached on emit. Use this before changing sig_q.\n\tvoid remove_init() {\n\t\tif (initvals)\n\t\t\tinitvals->remove_init(sig_q);\n\t}\n\n\tvoid remove();\n\n\t// Flip the sense of the given bit slices of the FF: insert inverters on data\n\t// inputs and output, flip the corresponding init/reset bits, swap clr/set\n\t// inputs with proper priority fix.\n\tvoid flip_bits(const pool<int> &bits);\n\n\tvoid flip_rst_bits(const pool<int> &bits);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
162
162
  "ffinit.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FFINIT_H\n#define FFINIT_H\n\n#include \"kernel/yosys.h\"\n#include \"kernel/sigtools.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\nstruct FfInitVals\n{\n\tconst SigMap *sigmap;\n\tdict<SigBit, std::pair<State,SigBit>> initbits;\n\n\tvoid set(const SigMap *sigmap_, RTLIL::Module *module)\n\t{\n\t\tsigmap = sigmap_;\n\t\tinitbits.clear();\n\t\tfor (auto wire : module->wires())\n\t\t{\n\t\t\tif (wire->attributes.count(ID::init) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tSigSpec wirebits = (*sigmap)(wire);\n\t\t\tConst initval = wire->attributes.at(ID::init);\n\n\t\t\tfor (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)\n\t\t\t{\n\t\t\t\tSigBit bit = wirebits[i];\n\t\t\t\tState val = initval[i];\n\n\t\t\t\tif (val != State::S0 && val != State::S1 && bit.wire != nullptr)\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (initbits.count(bit)) {\n\t\t\t\t\tif (initbits.at(bit).first != val)\n\t\t\t\t\t\tlog_error(\"Conflicting init values for signal %s (%s = %s != %s).\\n\",\n\t\t\t\t\t\t\t\tlog_signal(bit), log_signal(SigBit(wire, i)),\n\t\t\t\t\t\t\t\tlog_signal(val), log_signal(initbits.at(bit).first));\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\tinitbits[bit] = std::make_pair(val,SigBit(wire,i));\n\t\t\t}\n\t\t}\n\t}\n\n\tRTLIL::State operator()(RTLIL::SigBit bit) const\n\t{\n\t\tauto it = initbits.find((*sigmap)(bit));\n\t\tif (it != initbits.end())\n\t\t\treturn it->second.first;\n\t\telse\n\t\t\treturn State::Sx;\n\t}\n\n\tRTLIL::Const operator()(const RTLIL::SigSpec &sig) const\n\t{\n\t\tRTLIL::Const res;\n\t\tfor (auto bit : sig)\n\t\t\tres.bits.push_back((*this)(bit));\n\t\treturn res;\n\t}\n\n\tvoid set_init(RTLIL::SigBit bit, RTLIL::State val)\n\t{\n\t\tSigBit mbit = (*sigmap)(bit);\n\t\tSigBit abit = bit;\n\t\tauto it = initbits.find(mbit);\n\t\tif (it != initbits.end())\n\t\t\tabit = it->second.second;\n\t\telse if (val == State::Sx)\n\t\t\treturn;\n\t\tlog_assert(abit.wire);\n\t\tinitbits[mbit] = std::make_pair(val,abit);\n\t\tauto it2 = abit.wire->attributes.find(ID::init);\n\t\tif (it2 != abit.wire->attributes.end()) {\n\t\t\tit2->second[abit.offset] = val;\n\t\t\tif (it2->second.is_fully_undef())\n\t\t\t\tabit.wire->attributes.erase(it2);\n\t\t} else if (val != State::Sx) {\n\t\t\tConst cval(State::Sx, GetSize(abit.wire));\n\t\t\tcval[abit.offset] = val;\n\t\t\tabit.wire->attributes[ID::init] = cval;\n\t\t}\n\t}\n\n\tvoid set_init(const RTLIL::SigSpec &sig, RTLIL::Const val)\n\t{\n\t\tlog_assert(GetSize(sig) == GetSize(val));\n\t\tfor (int i = 0; i < GetSize(sig); i++)\n\t\t\tset_init(sig[i], val[i]);\n\t}\n\n\tvoid remove_init(RTLIL::SigBit bit)\n\t{\n\t\tset_init(bit, State::Sx);\n\t}\n\n\tvoid remove_init(const RTLIL::SigSpec &sig)\n\t{\n\t\tfor (auto bit : sig)\n\t\t\tremove_init(bit);\n\t}\n\n\tvoid clear()\n\t{\n\t\tinitbits.clear();\n\t}\n\n\tFfInitVals (const SigMap *sigmap, RTLIL::Module *module)\n\t{\n\t\tset(sigmap, module);\n\t}\n\n\tFfInitVals () {}\n};\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
163
163
  "ffmerge.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FFMERGE_H\n#define FFMERGE_H\n\n#include \"kernel/ffinit.h\"\n#include \"kernel/ff.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// A helper class for passes that want to merge FFs on the input or output\n// of a cell into the cell itself.\n//\n// The procedure is:\n//\n// 1. Construct this class (at beginning of processing for a given module).\n// 2. For every considered cell:\n//\n// a. Call find_output_ff for every considered output.\n// b. Call find_input_ff for every considered input.\n// c. Look at the FF description returned (if any) from each call, reject\n// results that cannot be merged into given cell for any reason.\n// If both inputs and outputs are being merged, take care of FF bits that\n// are returned in both input and output results (a FF bit cannot be\n// merged to both). Decide on the final set of FF bits to merge.\n// d. Call remove_output_ff for every find_output_ff result that will be used\n// for merging. This removes the actual FF bits from design and from index.\n// e. Call mark_input_ff for every find_input_ff result that will be used\n// for merging. This updates the index disallowing further usage of these\n// FF bits for output FF merging, if they were eligible before. The actual\n// FF bits are still left in the design and can be merged into other inputs.\n// If the FF bits are not otherwise used, they will be removed by later\n// opt passes.\n// f. Merge the FFs into the cell.\n//\n// Note that, if both inputs and outputs are being considered for merging in\n// a single pass, the result may be nondeterministic (depending on cell iteration\n// order) because a given FF bit could be eligible for both input and output merge,\n// perhaps in different cells. For this reason, it may be a good idea to separate\n// input and output merging.\n\nstruct FfMergeHelper\n{\n\tconst SigMap *sigmap;\n\tRTLIL::Module *module;\n\tFfInitVals *initvals;\n\n\tdict<SigBit, std::pair<Cell*, int>> dff_driver;\n\tdict<SigBit, pool<std::pair<Cell*, int>>> dff_sink;\n\tdict<SigBit, int> sigbit_users_count;\n\n\t// Returns true if all bits in sig are completely unused.\n\tbool is_output_unused(RTLIL::SigSpec sig);\n\n\t// Finds the FF to merge into a given cell output. Takes sig, which\n\t// is the current cell output — it will be the sig_d of the found FF.\n\t// If found, returns true, and fills the two output arguments.\n\t//\n\t// For every bit of sig, this function finds a FF bit that has\n\t// the same sig_d, and fills the output FfData according to the FF\n\t// bits found. This function will only consider FF bits that are\n\t// the only user of the given sig bits — if any bit in sig is used\n\t// by anything other than a single FF, this function will return false.\n\t//\n\t// The returned FfData structure does not correspond to any actual FF\n\t// cell in the design — it is the amalgamation of extracted FF bits,\n\t// possibly coming from several FF cells.\n\t//\n\t// If some of the bits in sig have no users at all, this function\n\t// will accept them as well (and fill returned FfData with dummy values\n\t// for the given bit, effectively synthesizing an unused FF bit of the\n\t// appropriate type). However, if all bits in sig are completely\n\t// unused, this function will fail and return false (having no idea\n\t// what kind of FF to produce) — use the above helper if that case\n\t// is important to handle.\n\t//\n\t// Note that this function does not remove the FF bits returned from\n\t// the design — this is so that the caller can decide whether to accept\n\t// this FF for merging or not. If the result is accepted,\n\t// remove_output_ff should be called on the second output argument.\n\tbool find_output_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits);\n\n\t// Like above, but returns a FF to merge into a given cell input. Takes\n\t// sig_q, which is the current cell input — it will search for FFs with\n\t// matching sig_q.\n\t//\n\t// As opposed to find_output_ff, this function doesn't care about usage\n\t// counts, and may return FF bits that also have other fanout. This\n\t// should not be a problem for input FF merging.\n\t//\n\t// As a special case, if some of the bits in sig_q are constant, this\n\t// function will accept them as well, by synthesizing in-place\n\t// a constant-input FF bit (with matching initial value and reset value).\n\t// However, this will not work if the input is all-constant — if the caller\n\t// cares about this case, it needs to check for it explicitely.\n\tbool find_input_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits);\n\n\t// To be called on find_output_ff result that will be merged. This\n\t// marks the given FF bits as used up (and not to be considered for\n\t// further merging as inputs), and reconnects their Q ports to a dummy\n\t// wire (since the wire previously connected there will now be driven\n\t// by the merged-to cell instead).\n\tvoid remove_output_ff(const pool<std::pair<Cell *, int>> &bits);\n\n\t// To be called on find_input_ff result that will be merged. This\n\t// marks the given FF bits as used, and disallows merging them as\n\t// outputs. They can, however, still be merged as inputs again\n\t// (perhaps for another cell).\n\tvoid mark_input_ff(const pool<std::pair<Cell *, int>> &bits);\n\n\tvoid set(FfInitVals *initvals_, RTLIL::Module *module_);\n\n\tvoid clear();\n\n\tFfMergeHelper(FfInitVals *initvals, RTLIL::Module *module) {\n\t\tset(initvals, module);\n\t}\n\n\tFfMergeHelper() {}\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
164
- "fmt.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FMT_H\n#define FMT_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// Verilog format argument, such as the arguments in:\n// $display(\"foo %d bar %01x\", 4'b0, $signed(2'b11))\nstruct VerilogFmtArg {\n\tenum {\n\t\tSTRING = 0,\n\t\tINTEGER = 1,\n\t\tTIME = 2,\n\t} type;\n\n\t// All types\n\tstd::string filename;\n\tunsigned first_line;\n\n\t// STRING type\n\tstd::string str;\n\n\t// INTEGER type\n\tRTLIL::SigSpec sig;\n\tbool signed_ = false;\n\n\t// TIME type\n\tbool realtime = false;\n};\n\n// RTLIL format part, such as the substitutions in:\n// \"foo {4:> 4du} bar {2:<01hs}\"\nstruct FmtPart {\n\tenum {\n\t\tSTRING \t= 0,\n\t\tINTEGER \t= 1,\n\t\tCHARACTER = 2,\n\t\tTIME \t= 3,\n\t} type;\n\n\t// STRING type\n\tstd::string str;\n\n\t// INTEGER/CHARACTER types\n\tRTLIL::SigSpec sig;\n\n\t// INTEGER/CHARACTER/TIME types\n\tenum {\n\t\tRIGHT\t= 0,\n\t\tLEFT\t= 1,\n\t} justify = RIGHT;\n\tchar padding = '\\0';\n\tsize_t width = 0;\n\t\n\t// INTEGER type\n\tunsigned base = 10;\n\tbool signed_ = false;\n\tbool plus = false;\n\n\t// TIME type\n\tbool realtime = false;\n};\n\nstruct Fmt {\npublic:\n\tstd::vector<FmtPart> parts;\n\n\tvoid append_string(const std::string &str);\n\n\tvoid parse_rtlil(const RTLIL::Cell *cell);\n\tvoid emit_rtlil(RTLIL::Cell *cell) const;\n\n\tvoid parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_like, int default_base, RTLIL::IdString task_name, RTLIL::IdString module_name);\n\tstd::vector<VerilogFmtArg> emit_verilog() const;\n\n\tvoid emit_cxxrtl(std::ostream &f, std::function<void(const RTLIL::SigSpec &)> emit_sig) const;\n\n\tstd::string render() const;\n\nprivate:\n\tvoid apply_verilog_automatic_sizing_and_add(FmtPart &part);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
164
+ "fmt.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2020 whitequark <whitequark@whitequark.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef FMT_H\n#define FMT_H\n\n#include \"kernel/yosys.h\"\n\nYOSYS_NAMESPACE_BEGIN\n\n// Verilog format argument, such as the arguments in:\n// $display(\"foo %d bar %01x\", 4'b0, $signed(2'b11))\nstruct VerilogFmtArg {\n\tenum {\n\t\tSTRING = 0,\n\t\tINTEGER = 1,\n\t\tTIME = 2,\n\t} type;\n\n\t// All types\n\tstd::string filename;\n\tunsigned first_line;\n\n\t// STRING type\n\tstd::string str;\n\n\t// INTEGER type\n\tRTLIL::SigSpec sig;\n\tbool signed_ = false;\n\n\t// TIME type\n\tbool realtime = false;\n};\n\n// RTLIL format part, such as the substitutions in:\n// \"foo {4:> 4du} bar {2:<01hs}\"\n// Must be kept in sync with `struct fmt_part` in backends/cxxrtl/runtime/cxxrtl/cxxrtl.h!\nstruct FmtPart {\n\tenum {\n\t\tSTRING \t= 0,\n\t\tINTEGER \t= 1,\n\t\tCHARACTER = 2,\n\t\tVLOG_TIME = 3,\n\t} type;\n\n\t// STRING type\n\tstd::string str;\n\n\t// INTEGER/CHARACTER types\n\tRTLIL::SigSpec sig;\n\n\t// INTEGER/CHARACTER/VLOG_TIME types\n\tenum {\n\t\tRIGHT\t= 0,\n\t\tLEFT\t= 1,\n\t} justify = RIGHT;\n\tchar padding = '\\0';\n\tsize_t width = 0;\n\n\t// INTEGER type\n\tunsigned base = 10;\n\tbool signed_ = false;\n\tbool plus = false;\n\n\t// VLOG_TIME type\n\tbool realtime = false;\n};\n\nstruct Fmt {\npublic:\n\tstd::vector<FmtPart> parts;\n\n\tvoid append_string(const std::string &str);\n\n\tvoid parse_rtlil(const RTLIL::Cell *cell);\n\tvoid emit_rtlil(RTLIL::Cell *cell) const;\n\n\tvoid parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_like, int default_base, RTLIL::IdString task_name, RTLIL::IdString module_name);\n\tstd::vector<VerilogFmtArg> emit_verilog() const;\n\n\tvoid emit_cxxrtl(std::ostream &os, std::string indent, std::function<void(const RTLIL::SigSpec &)> emit_sig, const std::string &context) const;\n\n\tstd::string render() const;\n\nprivate:\n\tvoid apply_verilog_automatic_sizing_and_add(FmtPart &part);\n};\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
165
165
  "hashlib.h": "// This is free and unencumbered software released into the public domain.\n//\n// Anyone is free to copy, modify, publish, use, compile, sell, or\n// distribute this software, either in source code form or as a compiled\n// binary, for any purpose, commercial or non-commercial, and by any\n// means.\n\n// -------------------------------------------------------\n// Written by Claire Xenia Wolf <claire@yosyshq.com> in 2014\n// -------------------------------------------------------\n\n#ifndef HASHLIB_H\n#define HASHLIB_H\n\n#include <stdexcept>\n#include <algorithm>\n#include <string>\n#include <vector>\n\nnamespace hashlib {\n\nconst int hashtable_size_trigger = 2;\nconst int hashtable_size_factor = 3;\n\n// The XOR version of DJB2\ninline unsigned int mkhash(unsigned int a, unsigned int b) {\n\treturn ((a << 5) + a) ^ b;\n}\n\n// traditionally 5381 is used as starting value for the djb2 hash\nconst unsigned int mkhash_init = 5381;\n\n// The ADD version of DJB2\n// (use this version for cache locality in b)\ninline unsigned int mkhash_add(unsigned int a, unsigned int b) {\n\treturn ((a << 5) + a) + b;\n}\n\ninline unsigned int mkhash_xorshift(unsigned int a) {\n\tif (sizeof(a) == 4) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 17;\n\t\ta ^= a << 5;\n\t} else if (sizeof(a) == 8) {\n\t\ta ^= a << 13;\n\t\ta ^= a >> 7;\n\t\ta ^= a << 17;\n\t} else\n\t\tthrow std::runtime_error(\"mkhash_xorshift() only implemented for 32 bit and 64 bit ints\");\n\treturn a;\n}\n\ntemplate<typename T> struct hash_ops {\n\tstatic inline bool cmp(const T &a, const T &b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(const T &a) {\n\t\treturn a.hash();\n\t}\n};\n\nstruct hash_int_ops {\n\ttemplate<typename T>\n\tstatic inline bool cmp(T a, T b) {\n\t\treturn a == b;\n\t}\n};\n\ntemplate<> struct hash_ops<bool> : hash_int_ops\n{\n\tstatic inline unsigned int hash(bool a) {\n\t\treturn a ? 1 : 0;\n\t}\n};\ntemplate<> struct hash_ops<int32_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(int32_t a) {\n\t\treturn a;\n\t}\n};\ntemplate<> struct hash_ops<int64_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(int64_t a) {\n\t\treturn mkhash((unsigned int)(a), (unsigned int)(a >> 32));\n\t}\n};\ntemplate<> struct hash_ops<uint32_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(uint32_t a) {\n\t\treturn a;\n\t}\n};\ntemplate<> struct hash_ops<uint64_t> : hash_int_ops\n{\n\tstatic inline unsigned int hash(uint64_t a) {\n\t\treturn mkhash((unsigned int)(a), (unsigned int)(a >> 32));\n\t}\n};\n\ntemplate<> struct hash_ops<std::string> {\n\tstatic inline bool cmp(const std::string &a, const std::string &b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(const std::string &a) {\n\t\tunsigned int v = 0;\n\t\tfor (auto c : a)\n\t\t\tv = mkhash(v, c);\n\t\treturn v;\n\t}\n};\n\ntemplate<typename P, typename Q> struct hash_ops<std::pair<P, Q>> {\n\tstatic inline bool cmp(std::pair<P, Q> a, std::pair<P, Q> b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(std::pair<P, Q> a) {\n\t\treturn mkhash(hash_ops<P>::hash(a.first), hash_ops<Q>::hash(a.second));\n\t}\n};\n\ntemplate<typename... T> struct hash_ops<std::tuple<T...>> {\n\tstatic inline bool cmp(std::tuple<T...> a, std::tuple<T...> b) {\n\t\treturn a == b;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I == sizeof...(T), unsigned int>::type hash(std::tuple<T...>) {\n\t\treturn mkhash_init;\n\t}\n\ttemplate<size_t I = 0>\n\tstatic inline typename std::enable_if<I != sizeof...(T), unsigned int>::type hash(std::tuple<T...> a) {\n\t\ttypedef hash_ops<typename std::tuple_element<I, std::tuple<T...>>::type> element_ops_t;\n\t\treturn mkhash(hash<I+1>(a), element_ops_t::hash(std::get<I>(a)));\n\t}\n};\n\ntemplate<typename T> struct hash_ops<std::vector<T>> {\n\tstatic inline bool cmp(std::vector<T> a, std::vector<T> b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(std::vector<T> a) {\n\t\tunsigned int h = mkhash_init;\n\t\tfor (auto k : a)\n\t\t\th = mkhash(h, hash_ops<T>::hash(k));\n\t\treturn h;\n\t}\n};\n\nstruct hash_cstr_ops {\n\tstatic inline bool cmp(const char *a, const char *b) {\n\t\tfor (int i = 0; a[i] || b[i]; i++)\n\t\t\tif (a[i] != b[i])\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\tstatic inline unsigned int hash(const char *a) {\n\t\tunsigned int hash = mkhash_init;\n\t\twhile (*a)\n\t\t\thash = mkhash(hash, *(a++));\n\t\treturn hash;\n\t}\n};\n\nstruct hash_ptr_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\tstatic inline unsigned int hash(const void *a) {\n\t\treturn (uintptr_t)a;\n\t}\n};\n\nstruct hash_obj_ops {\n\tstatic inline bool cmp(const void *a, const void *b) {\n\t\treturn a == b;\n\t}\n\ttemplate<typename T>\n\tstatic inline unsigned int hash(const T *a) {\n\t\treturn a ? a->hash() : 0;\n\t}\n};\n\ntemplate<typename T>\ninline unsigned int mkhash(const T &v) {\n\treturn hash_ops<T>().hash(v);\n}\n\ninline int hashtable_size(int min_size)\n{\n\tstatic std::vector<int> zero_and_some_primes = {\n\t\t0, 23, 29, 37, 47, 59, 79, 101, 127, 163, 211, 269, 337, 431, 541, 677,\n\t\t853, 1069, 1361, 1709, 2137, 2677, 3347, 4201, 5261, 6577, 8231, 10289,\n\t\t12889, 16127, 20161, 25219, 31531, 39419, 49277, 61603, 77017, 96281,\n\t\t120371, 150473, 188107, 235159, 293957, 367453, 459317, 574157, 717697,\n\t\t897133, 1121423, 1401791, 1752239, 2190299, 2737937, 3422429, 4278037,\n\t\t5347553, 6684443, 8355563, 10444457, 13055587, 16319519, 20399411,\n\t\t25499291, 31874149, 39842687, 49803361, 62254207, 77817767, 97272239,\n\t\t121590311, 151987889, 189984863, 237481091, 296851369, 371064217\n\t};\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (p >= min_size) return p;\n\n\tif (sizeof(int) == 4)\n\t\tthrow std::length_error(\"hash table exceeded maximum size.\\nDesign is likely too large for yosys to handle, if possible try not to flatten the design.\");\n\n\tfor (auto p : zero_and_some_primes)\n\t\tif (100129 * p > min_size) return 100129 * p;\n\n\tthrow std::length_error(\"hash table exceeded maximum size.\");\n}\n\ntemplate<typename K, typename T, typename OPS = hash_ops<K>> class dict;\ntemplate<typename K, int offset = 0, typename OPS = hash_ops<K>> class idict;\ntemplate<typename K, typename OPS = hash_ops<K>> class pool;\ntemplate<typename K, typename OPS = hash_ops<K>> class mfp;\n\ntemplate<typename K, typename T, typename OPS>\nclass dict\n{\n\tstruct entry_t\n\t{\n\t\tstd::pair<K, T> udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const std::pair<K, T> &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(std::pair<K, T> &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t\tbool operator<(const entry_t &other) const { return udata.first < other.udata.first; }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"dict<> assert failed.\");\n\t}\n#endif\n\n\tint do_hash(const K &key) const\n\t{\n\t\tunsigned int hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key) % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tint hash = do_hash(entries[i].udata.first);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, int hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tint back_hash = do_hash(entries[back_idx].udata.first);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, int &hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\t((dict*)this)->do_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata.first, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_insert(const K &key, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t} else {\n\t\t\tentries.emplace_back(std::pair<K, T>(key, T()), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(const std::pair<K, T> &value, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value.first);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(std::pair<K, T> &&rvalue, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tauto key = rvalue.first;\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(key);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<std::pair<K, T>>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tconst dict *ptr;\n\t\tint index;\n\t\tconst_iterator(const dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tconst_iterator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const const_iterator &other) const { return index > other.index; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class dict;\n\tprotected:\n\t\tdict *ptr;\n\t\tint index;\n\t\titerator(dict *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef std::pair<K, T> value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef std::pair<K, T>* pointer;\n\t\ttypedef std::pair<K, T>& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\titerator operator+=(int amt) { index -= amt; return *this; }\n\t\tbool operator<(const iterator &other) const { return index > other.index; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tstd::pair<K, T> &operator*() { return ptr->entries[index].udata; }\n\t\tstd::pair<K, T> *operator->() { return &ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> &operator*() const { return ptr->entries[index].udata; }\n\t\tconst std::pair<K, T> *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr dict()\n\t{\n\t}\n\n\tdict(const dict &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tdict(dict &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tdict &operator=(const dict &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tdict &operator=(dict &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tdict(const std::initializer_list<std::pair<K, T>> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tdict(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(key, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(const std::pair<K, T> &value)\n\t{\n\t\tint hash = do_hash(value.first);\n\t\tint i = do_lookup(value.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(std::pair<K, T> &&rvalue)\n\t{\n\t\tint hash = do_hash(rvalue.first);\n\t\tint i = do_lookup(rvalue.first, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<std::pair<K, T>>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T const &value)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K const &key, T &&rvalue)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(key, std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T const &value)\n\t{\n\t\tint hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), value), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> emplace(K &&rkey, T &&rvalue)\n\t{\n\t\tint hash = do_hash(rkey);\n\t\tint i = do_lookup(rkey, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::make_pair(std::forward<K>(rkey), std::forward<T>(rvalue)), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tint hash = do_hash(it->first);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tT& at(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"dict::at()\");\n\t\treturn entries[i].udata.second;\n\t}\n\n\tconst T& at(const K &key, const T &defval) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn entries[i].udata.second;\n\t}\n\n\tT& operator[](const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = do_insert(std::pair<K, T>(key, T()), hash);\n\t\treturn entries[i].udata.second;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata.first, a.udata.first); });\n\t\tdo_rehash();\n\t}\n\n\tvoid swap(dict &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const dict &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries) {\n\t\t\tauto oit = other.find(it.udata.first);\n\t\t\tif (oit == other.end() || !(oit->second == it.udata.second))\n\t\t\t\treturn false;\n\t\t}\n\t\treturn true;\n\t}\n\n\tbool operator!=(const dict &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\tunsigned int hash() const {\n\t\tunsigned int h = mkhash_init;\n\t\tfor (auto &entry : entries) {\n\t\t\th ^= hash_ops<K>::hash(entry.udata.first);\n\t\t\th ^= hash_ops<T>::hash(entry.udata.second);\n\t\t}\n\t\treturn h;\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, typename OPS>\nclass pool\n{\n\ttemplate<typename, int, typename> friend class idict;\n\nprotected:\n\tstruct entry_t\n\t{\n\t\tK udata;\n\t\tint next;\n\n\t\tentry_t() { }\n\t\tentry_t(const K &udata, int next) : udata(udata), next(next) { }\n\t\tentry_t(K &&udata, int next) : udata(std::move(udata)), next(next) { }\n\t};\n\n\tstd::vector<int> hashtable;\n\tstd::vector<entry_t> entries;\n\tOPS ops;\n\n#ifdef NDEBUG\n\tstatic inline void do_assert(bool) { }\n#else\n\tstatic inline void do_assert(bool cond) {\n\t\tif (!cond) throw std::runtime_error(\"pool<> assert failed.\");\n\t}\n#endif\n\n\tint do_hash(const K &key) const\n\t{\n\t\tunsigned int hash = 0;\n\t\tif (!hashtable.empty())\n\t\t\thash = ops.hash(key) % (unsigned int)(hashtable.size());\n\t\treturn hash;\n\t}\n\n\tvoid do_rehash()\n\t{\n\t\thashtable.clear();\n\t\thashtable.resize(hashtable_size(entries.capacity() * hashtable_size_factor), -1);\n\n\t\tfor (int i = 0; i < int(entries.size()); i++) {\n\t\t\tdo_assert(-1 <= entries[i].next && entries[i].next < int(entries.size()));\n\t\t\tint hash = do_hash(entries[i].udata);\n\t\t\tentries[i].next = hashtable[hash];\n\t\t\thashtable[hash] = i;\n\t\t}\n\t}\n\n\tint do_erase(int index, int hash)\n\t{\n\t\tdo_assert(index < int(entries.size()));\n\t\tif (hashtable.empty() || index < 0)\n\t\t\treturn 0;\n\n\t\tint k = hashtable[hash];\n\t\tif (k == index) {\n\t\t\thashtable[hash] = entries[index].next;\n\t\t} else {\n\t\t\twhile (entries[k].next != index) {\n\t\t\t\tk = entries[k].next;\n\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t}\n\t\t\tentries[k].next = entries[index].next;\n\t\t}\n\n\t\tint back_idx = entries.size()-1;\n\n\t\tif (index != back_idx)\n\t\t{\n\t\t\tint back_hash = do_hash(entries[back_idx].udata);\n\n\t\t\tk = hashtable[back_hash];\n\t\t\tif (k == back_idx) {\n\t\t\t\thashtable[back_hash] = index;\n\t\t\t} else {\n\t\t\t\twhile (entries[k].next != back_idx) {\n\t\t\t\t\tk = entries[k].next;\n\t\t\t\t\tdo_assert(0 <= k && k < int(entries.size()));\n\t\t\t\t}\n\t\t\t\tentries[k].next = index;\n\t\t\t}\n\n\t\t\tentries[index] = std::move(entries[back_idx]);\n\t\t}\n\n\t\tentries.pop_back();\n\n\t\tif (entries.empty())\n\t\t\thashtable.clear();\n\n\t\treturn 1;\n\t}\n\n\tint do_lookup(const K &key, int &hash) const\n\t{\n\t\tif (hashtable.empty())\n\t\t\treturn -1;\n\n\t\tif (entries.size() * hashtable_size_trigger > hashtable.size()) {\n\t\t\t((pool*)this)->do_rehash();\n\t\t\thash = do_hash(key);\n\t\t}\n\n\t\tint index = hashtable[hash];\n\n\t\twhile (index >= 0 && !ops.cmp(entries[index].udata, key)) {\n\t\t\tindex = entries[index].next;\n\t\t\tdo_assert(-1 <= index && index < int(entries.size()));\n\t\t}\n\n\t\treturn index;\n\t}\n\n\tint do_insert(const K &value, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(value, -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(value);\n\t\t} else {\n\t\t\tentries.emplace_back(value, hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\n\tint do_insert(K &&rvalue, int &hash)\n\t{\n\t\tif (hashtable.empty()) {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), -1);\n\t\t\tdo_rehash();\n\t\t\thash = do_hash(rvalue);\n\t\t} else {\n\t\t\tentries.emplace_back(std::forward<K>(rvalue), hashtable[hash]);\n\t\t\thashtable[hash] = entries.size() - 1;\n\t\t}\n\t\treturn entries.size() - 1;\n\t}\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tconst pool *ptr;\n\t\tint index;\n\t\tconst_iterator(const pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index--; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t};\n\n\tclass iterator\n\t{\n\t\tfriend class pool;\n\tprotected:\n\t\tpool *ptr;\n\t\tint index;\n\t\titerator(pool *ptr, int index) : ptr(ptr), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\titerator() { }\n\t\titerator operator++() { index--; return *this; }\n\t\tbool operator==(const iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const iterator &other) const { return index != other.index; }\n\t\tK &operator*() { return ptr->entries[index].udata; }\n\t\tK *operator->() { return &ptr->entries[index].udata; }\n\t\tconst K &operator*() const { return ptr->entries[index].udata; }\n\t\tconst K *operator->() const { return &ptr->entries[index].udata; }\n\t\toperator const_iterator() const { return const_iterator(ptr, index); }\n\t};\n\n\tconstexpr pool()\n\t{\n\t}\n\n\tpool(const pool &other)\n\t{\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t}\n\n\tpool(pool &&other)\n\t{\n\t\tswap(other);\n\t}\n\n\tpool &operator=(const pool &other) {\n\t\tentries = other.entries;\n\t\tdo_rehash();\n\t\treturn *this;\n\t}\n\n\tpool &operator=(pool &&other) {\n\t\tclear();\n\t\tswap(other);\n\t\treturn *this;\n\t}\n\n\tpool(const std::initializer_list<K> &list)\n\t{\n\t\tfor (auto &it : list)\n\t\t\tinsert(it);\n\t}\n\n\ttemplate<class InputIterator>\n\tpool(InputIterator first, InputIterator last)\n\t{\n\t\tinsert(first, last);\n\t}\n\n\ttemplate<class InputIterator>\n\tvoid insert(InputIterator first, InputIterator last)\n\t{\n\t\tfor (; first != last; ++first)\n\t\t\tinsert(*first);\n\t}\n\n\tstd::pair<iterator, bool> insert(const K &value)\n\t{\n\t\tint hash = do_hash(value);\n\t\tint i = do_lookup(value, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(value, hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\tstd::pair<iterator, bool> insert(K &&rvalue)\n\t{\n\t\tint hash = do_hash(rvalue);\n\t\tint i = do_lookup(rvalue, hash);\n\t\tif (i >= 0)\n\t\t\treturn std::pair<iterator, bool>(iterator(this, i), false);\n\t\ti = do_insert(std::forward<K>(rvalue), hash);\n\t\treturn std::pair<iterator, bool>(iterator(this, i), true);\n\t}\n\n\ttemplate<typename... Args>\n\tstd::pair<iterator, bool> emplace(Args&&... args)\n\t{\n\t\treturn insert(K(std::forward<Args>(args)...));\n\t}\n\n\tint erase(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint index = do_lookup(key, hash);\n\t\treturn do_erase(index, hash);\n\t}\n\n\titerator erase(iterator it)\n\t{\n\t\tint hash = do_hash(*it);\n\t\tdo_erase(it.index, hash);\n\t\treturn ++it;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tint count(const K &key, const_iterator it) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i < 0 || i > it.index ? 0 : 1;\n\t}\n\n\titerator find(const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn iterator(this, i);\n\t}\n\n\tconst_iterator find(const K &key) const\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn end();\n\t\treturn const_iterator(this, i);\n\t}\n\n\tbool operator[](const K &key)\n\t{\n\t\tint hash = do_hash(key);\n\t\tint i = do_lookup(key, hash);\n\t\treturn i >= 0;\n\t}\n\n\ttemplate<typename Compare = std::less<K>>\n\tvoid sort(Compare comp = Compare())\n\t{\n\t\tstd::sort(entries.begin(), entries.end(), [comp](const entry_t &a, const entry_t &b){ return comp(b.udata, a.udata); });\n\t\tdo_rehash();\n\t}\n\n\tK pop()\n\t{\n\t\titerator it = begin();\n\t\tK ret = *it;\n\t\terase(it);\n\t\treturn ret;\n\t}\n\n\tvoid swap(pool &other)\n\t{\n\t\thashtable.swap(other.hashtable);\n\t\tentries.swap(other.entries);\n\t}\n\n\tbool operator==(const pool &other) const {\n\t\tif (size() != other.size())\n\t\t\treturn false;\n\t\tfor (auto &it : entries)\n\t\t\tif (!other.count(it.udata))\n\t\t\t\treturn false;\n\t\treturn true;\n\t}\n\n\tbool operator!=(const pool &other) const {\n\t\treturn !operator==(other);\n\t}\n\n\tunsigned int hash() const {\n\t\tunsigned int hashval = mkhash_init;\n\t\tfor (auto &it : entries)\n\t\t\thashval ^= ops.hash(it.udata);\n\t\treturn hashval;\n\t}\n\n\tvoid reserve(size_t n) { entries.reserve(n); }\n\tsize_t size() const { return entries.size(); }\n\tbool empty() const { return entries.empty(); }\n\tvoid clear() { hashtable.clear(); entries.clear(); }\n\n\titerator begin() { return iterator(this, int(entries.size())-1); }\n\titerator element(int n) { return iterator(this, int(entries.size())-1-n); }\n\titerator end() { return iterator(nullptr, -1); }\n\n\tconst_iterator begin() const { return const_iterator(this, int(entries.size())-1); }\n\tconst_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }\n\tconst_iterator end() const { return const_iterator(nullptr, -1); }\n};\n\ntemplate<typename K, int offset, typename OPS>\nclass idict\n{\n\tpool<K, OPS> database;\n\npublic:\n\tclass const_iterator\n\t{\n\t\tfriend class idict;\n\tprotected:\n\t\tconst idict &container;\n\t\tint index;\n\t\tconst_iterator(const idict &container, int index) : container(container), index(index) { }\n\tpublic:\n\t\ttypedef std::forward_iterator_tag iterator_category;\n\t\ttypedef K value_type;\n\t\ttypedef ptrdiff_t difference_type;\n\t\ttypedef K* pointer;\n\t\ttypedef K& reference;\n\t\tconst_iterator() { }\n\t\tconst_iterator operator++() { index++; return *this; }\n\t\tbool operator==(const const_iterator &other) const { return index == other.index; }\n\t\tbool operator!=(const const_iterator &other) const { return index != other.index; }\n\t\tconst K &operator*() const { return container[index]; }\n\t\tconst K *operator->() const { return &container[index]; }\n\t};\n\n\tconstexpr idict()\n\t{\n\t}\n\n\tint operator()(const K &key)\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\ti = database.do_insert(key, hash);\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key) const\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\tthrow std::out_of_range(\"idict::at()\");\n\t\treturn i + offset;\n\t}\n\n\tint at(const K &key, int defval) const\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\tif (i < 0)\n\t\t\treturn defval;\n\t\treturn i + offset;\n\t}\n\n\tint count(const K &key) const\n\t{\n\t\tint hash = database.do_hash(key);\n\t\tint i = database.do_lookup(key, hash);\n\t\treturn i < 0 ? 0 : 1;\n\t}\n\n\tvoid expect(const K &key, int i)\n\t{\n\t\tint j = (*this)(key);\n\t\tif (i != j)\n\t\t\tthrow std::out_of_range(\"idict::expect()\");\n\t}\n\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database.entries.at(index - offset).udata;\n\t}\n\n\tvoid swap(idict &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); }\n\n\tconst_iterator begin() const { return const_iterator(*this, offset); }\n\tconst_iterator element(int n) const { return const_iterator(*this, n); }\n\tconst_iterator end() const { return const_iterator(*this, offset + size()); }\n};\n\ntemplate<typename K, typename OPS>\nclass mfp\n{\n\tmutable idict<K, 0, OPS> database;\n\tmutable std::vector<int> parents;\n\npublic:\n\ttypedef typename idict<K, 0, OPS>::const_iterator const_iterator;\n\n\tconstexpr mfp()\n\t{\n\t}\n\n\tint operator()(const K &key) const\n\t{\n\t\tint i = database(key);\n\t\tparents.resize(database.size(), -1);\n\t\treturn i;\n\t}\n\n\tconst K &operator[](int index) const\n\t{\n\t\treturn database[index];\n\t}\n\n\tint ifind(int i) const\n\t{\n\t\tint p = i, k = i;\n\n\t\twhile (parents[p] != -1)\n\t\t\tp = parents[p];\n\n\t\twhile (k != p) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = p;\n\t\t\tk = next_k;\n\t\t}\n\n\t\treturn p;\n\t}\n\n\tvoid imerge(int i, int j)\n\t{\n\t\ti = ifind(i);\n\t\tj = ifind(j);\n\n\t\tif (i != j)\n\t\t\tparents[i] = j;\n\t}\n\n\tvoid ipromote(int i)\n\t{\n\t\tint k = i;\n\n\t\twhile (k != -1) {\n\t\t\tint next_k = parents[k];\n\t\t\tparents[k] = i;\n\t\t\tk = next_k;\n\t\t}\n\n\t\tparents[i] = -1;\n\t}\n\n\tint lookup(const K &a) const\n\t{\n\t\treturn ifind((*this)(a));\n\t}\n\n\tconst K &find(const K &a) const\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i < 0)\n\t\t\treturn a;\n\t\treturn (*this)[ifind(i)];\n\t}\n\n\tvoid merge(const K &a, const K &b)\n\t{\n\t\timerge((*this)(a), (*this)(b));\n\t}\n\n\tvoid promote(const K &a)\n\t{\n\t\tint i = database.at(a, -1);\n\t\tif (i >= 0)\n\t\t\tipromote(i);\n\t}\n\n\tvoid swap(mfp &other)\n\t{\n\t\tdatabase.swap(other.database);\n\t\tparents.swap(other.parents);\n\t}\n\n\tvoid reserve(size_t n) { database.reserve(n); }\n\tsize_t size() const { return database.size(); }\n\tbool empty() const { return database.empty(); }\n\tvoid clear() { database.clear(); parents.clear(); }\n\n\tconst_iterator begin() const { return database.begin(); }\n\tconst_iterator element(int n) const { return database.element(n); }\n\tconst_iterator end() const { return database.end(); }\n};\n\n} /* namespace hashlib */\n\n#endif\n",
166
166
  "json.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2022 Jannis Harder <jix@yosyshq.com> <me@jix.one>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#ifndef JSON_H\n#define JSON_H\n\n#include \"kernel/yosys.h\"\n#include \"libs/json11/json11.hpp\"\n#include <functional>\n\nYOSYS_NAMESPACE_BEGIN\n\nusing json11::Json;\n\nclass PrettyJson\n{\n enum Scope {\n VALUE,\n OBJECT_FIRST,\n OBJECT,\n ARRAY_FIRST,\n ARRAY,\n };\n\n struct Target {\n virtual void emit(const char *data) = 0;\n virtual void flush() {};\n virtual ~Target() {};\n };\n\n std::string newline_indent = \"\\n\";\n std::vector<std::unique_ptr<Target>> targets;\n std::vector<Scope> state = {VALUE};\n int compact_depth = INT_MAX;\npublic:\n\n void emit_to_log();\n void append_to_string(std::string &target);\n bool write_to_file(const std::string &path);\n\n bool active() { return !targets.empty(); }\n\n void compact() { compact_depth = GetSize(state); }\n\n void line(bool space_if_inline = true);\n void raw(const char *raw_json);\n void flush();\n void begin_object();\n void begin_array();\n void end_object();\n void end_array();\n void name(const char *name);\n void begin_value();\n void end_value();\n void value_json(const Json &value);\n void value(unsigned int value) { value_json(Json((int)value)); }\n template<typename T>\n void value(T &&value) { value_json(Json(std::forward<T>(value))); };\n\n void entry_json(const char *name, const Json &value);\n void entry(const char *name, unsigned int value) { entry_json(name, Json((int)value)); }\n template<typename T>\n void entry(const char *name, T &&value) { entry_json(name, Json(std::forward<T>(value))); };\n\n template<typename T>\n void object(const T &&values)\n {\n begin_object();\n for (auto &item : values)\n entry(item.first, item.second);\n end_object();\n }\n\n template<typename T>\n void array(const T &&values)\n {\n begin_object();\n for (auto &item : values)\n value(item);\n end_object();\n }\n};\n\n\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
167
167
  "log.h": "/*\n * yosys -- Yosys Open SYnthesis Suite\n *\n * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#include \"kernel/yosys.h\"\n\n#ifndef LOG_H\n#define LOG_H\n\n#include <time.h>\n\n#include <regex>\n#define YS_REGEX_COMPILE(param) std::regex(param, \\\n\t\t\t\tstd::regex_constants::nosubs | \\\n\t\t\t\tstd::regex_constants::optimize | \\\n\t\t\t\tstd::regex_constants::egrep)\n#define YS_REGEX_COMPILE_WITH_SUBS(param) std::regex(param, \\\n\t\t\t\tstd::regex_constants::optimize | \\\n\t\t\t\tstd::regex_constants::egrep)\n\n#if defined(_WIN32)\n# include <intrin.h>\n#else\n# include <sys/time.h>\n# include <sys/resource.h>\n# if defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n# include <signal.h>\n# endif\n#endif\n\n#if defined(_MSC_VER)\n// At least this is not in MSVC++ 2013.\n# define __PRETTY_FUNCTION__ __FUNCTION__\n#endif\n\n// from libs/sha1/sha1.h\nclass SHA1;\n\nYOSYS_NAMESPACE_BEGIN\n\n#define S__LINE__sub2(x) #x\n#define S__LINE__sub1(x) S__LINE__sub2(x)\n#define S__LINE__ S__LINE__sub1(__LINE__)\n\n// YS_DEBUGTRAP is a macro that is functionally equivalent to a breakpoint\n// if the platform provides such functionality, and does nothing otherwise.\n// If no debugger is attached, it starts a just-in-time debugger if available,\n// and crashes the process otherwise.\n#if defined(_WIN32)\n# define YS_DEBUGTRAP __debugbreak()\n#else\n# ifndef __has_builtin\n// __has_builtin is a GCC/Clang extension; on a different compiler (or old enough GCC/Clang)\n// that does not have it, using __has_builtin(...) is a syntax error.\n# define __has_builtin(x) 0\n# endif\n# if __has_builtin(__builtin_debugtrap)\n# define YS_DEBUGTRAP __builtin_debugtrap()\n# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n# define YS_DEBUGTRAP raise(SIGTRAP)\n# else\n# define YS_DEBUGTRAP do {} while(0)\n# endif\n#endif\n\n// YS_DEBUGTRAP_IF_DEBUGGING is a macro that is functionally equivalent to a breakpoint\n// if a debugger is attached, and does nothing otherwise.\n#if defined(_WIN32)\n# define YS_DEBUGTRAP_IF_DEBUGGING do { if (IsDebuggerPresent()) DebugBreak(); } while(0)\n# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))\n// There is no reliable (or portable) *nix equivalent of IsDebuggerPresent(). However,\n// debuggers will stop when SIGTRAP is raised, even if the action is set to ignore.\n# define YS_DEBUGTRAP_IF_DEBUGGING do { \\\n\t\tauto old = signal(SIGTRAP, SIG_IGN); raise(SIGTRAP); signal(SIGTRAP, old); \\\n\t} while(0)\n#else\n# define YS_DEBUGTRAP_IF_DEBUGGING do {} while(0)\n#endif\n\nstruct log_cmd_error_exception { };\n\nextern std::vector<FILE*> log_files;\nextern std::vector<std::ostream*> log_streams;\nextern std::vector<std::string> log_scratchpads;\nextern std::map<std::string, std::set<std::string>> log_hdump;\nextern std::vector<std::regex> log_warn_regexes, log_nowarn_regexes, log_werror_regexes;\nextern std::set<std::string> log_warnings, log_experimentals, log_experimentals_ignored;\nextern int log_warnings_count;\nextern int log_warnings_count_noexpect;\nextern bool log_expect_no_warnings;\nextern bool log_hdump_all;\nextern FILE *log_errfile;\nextern SHA1 *log_hasher;\n\nextern bool log_time;\nextern bool log_error_stderr;\nextern bool log_cmd_error_throw;\nextern bool log_quiet_warnings;\nextern int log_verbose_level;\nextern string log_last_error;\nextern void (*log_error_atexit)();\n\nextern int log_make_debug;\nextern int log_force_debug;\nextern int log_debug_suppressed;\n\nvoid logv(const char *format, va_list ap);\nvoid logv_header(RTLIL::Design *design, const char *format, va_list ap);\nvoid logv_warning(const char *format, va_list ap);\nvoid logv_warning_noprefix(const char *format, va_list ap);\n[[noreturn]] void logv_error(const char *format, va_list ap);\n[[noreturn]] void logv_file_error(const string &filename, int lineno, const char *format, va_list ap);\n\nvoid log(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\nvoid log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(format(printf, 2, 3));\nvoid log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\nvoid log_experimental(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\nvoid set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg));\nextern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg);\n\n// Log with filename to report a problem in a source file.\nvoid log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\nvoid log_file_info(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\n\nvoid log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n[[noreturn]] void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n[[noreturn]] void log_file_error(const string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));\n[[noreturn]] void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));\n\n#ifndef NDEBUG\nstatic inline bool ys_debug(int n = 0) { if (log_force_debug) return true; log_debug_suppressed += n; return false; }\n#else\nstatic inline bool ys_debug(int = 0) { return false; }\n#endif\n# define log_debug(...) do { if (ys_debug(1)) log(__VA_ARGS__); } while (0)\n\nstatic inline void log_suppressed() {\n\tif (log_debug_suppressed && !log_make_debug) {\n\t\tlog(\"<suppressed ~%d debug messages>\\n\", log_debug_suppressed);\n\t\tlog_debug_suppressed = 0;\n\t}\n}\n\nstruct LogMakeDebugHdl {\n\tbool status = false;\n\tLogMakeDebugHdl(bool start_on = false) {\n\t\tif (start_on)\n\t\t\ton();\n\t}\n\t~LogMakeDebugHdl() {\n\t\toff();\n\t}\n\tvoid on() {\n\t\tif (status) return;\n\t\tstatus=true;\n\t\tlog_make_debug++;\n\t}\n\tvoid off_silent() {\n\t\tif (!status) return;\n\t\tstatus=false;\n\t\tlog_make_debug--;\n\t}\n\tvoid off() {\n\t\toff_silent();\n\t}\n};\n\nvoid log_spacer();\nvoid log_push();\nvoid log_pop();\n\nvoid log_backtrace(const char *prefix, int levels);\nvoid log_reset_stack();\nvoid log_flush();\n\nstruct LogExpectedItem\n{\n\tLogExpectedItem(const std::regex &pat, int expected) :\n\t\t\tpattern(pat), expected_count(expected), current_count(0) {}\n\tLogExpectedItem() : expected_count(0), current_count(0) {}\n\n\tstd::regex pattern;\n\tint expected_count;\n\tint current_count;\n};\n\nextern dict<std::string, LogExpectedItem> log_expect_log, log_expect_warning, log_expect_error;\nvoid log_check_expected();\n\nconst char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true);\nconst char *log_const(const RTLIL::Const &value, bool autoint = true);\nconst char *log_id(const RTLIL::IdString &id);\n\ntemplate<typename T> static inline const char *log_id(T *obj, const char *nullstr = nullptr) {\n\tif (nullstr && obj == nullptr)\n\t\treturn nullstr;\n\treturn log_id(obj->name);\n}\n\nvoid log_module(RTLIL::Module *module, std::string indent = \"\");\nvoid log_cell(RTLIL::Cell *cell, std::string indent = \"\");\nvoid log_wire(RTLIL::Wire *wire, std::string indent = \"\");\n\n#ifndef NDEBUG\nstatic inline void log_assert_worker(bool cond, const char *expr, const char *file, int line) {\n\tif (!cond) log_error(\"Assert `%s' failed in %s:%d.\\n\", expr, file, line);\n}\n# define log_assert(_assert_expr_) YOSYS_NAMESPACE_PREFIX log_assert_worker(_assert_expr_, #_assert_expr_, __FILE__, __LINE__)\n#else\n# define log_assert(_assert_expr_) do { if (0) { (void)(_assert_expr_); } } while(0)\n#endif\n\n#define log_abort() YOSYS_NAMESPACE_PREFIX log_error(\"Abort in %s:%d.\\n\", __FILE__, __LINE__)\n#define log_ping() YOSYS_NAMESPACE_PREFIX log(\"-- %s:%d %s --\\n\", __FILE__, __LINE__, __PRETTY_FUNCTION__)\n\n\n// ---------------------------------------------------\n// This is the magic behind the code coverage counters\n// ---------------------------------------------------\n\n#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__))\n\n#define cover(_id) do { \\\n static CoverData __d __attribute__((section(\"yosys_cover_list\"), aligned(1), used)) = { __FILE__, __FUNCTION__, _id, __LINE__, 0 }; \\\n __d.counter++; \\\n} while (0)\n\nstruct CoverData {\n\tconst char *file, *func, *id;\n\tint line, counter;\n} YS_ATTRIBUTE(packed);\n\n// this two symbols are created by the linker for the \"yosys_cover_list\" ELF section\nextern \"C\" struct CoverData __start_yosys_cover_list[];\nextern \"C\" struct CoverData __stop_yosys_cover_list[];\n\nextern dict<std::string, std::pair<std::string, int>> extra_coverage_data;\n\nvoid cover_extra(std::string parent, std::string id, bool increment = true);\ndict<std::string, std::pair<std::string, int>> get_coverage_data();\n\n#define cover_list(_id, ...) do { cover(_id); \\\n\tstd::string r = cover_list_worker(_id, __VA_ARGS__); \\\n\tlog_assert(r.empty()); \\\n} while (0)\n\nstatic inline std::string cover_list_worker(std::string, std::string last) {\n\treturn last;\n}\n\ntemplate<typename... T>\nstd::string cover_list_worker(std::string prefix, std::string first, T... rest) {\n\tstd::string selected = cover_list_worker(prefix, rest...);\n\tcover_extra(prefix, prefix + \".\" + first, first == selected);\n\treturn first == selected ? \"\" : selected;\n}\n\n#else\n# define cover(...) do { } while (0)\n# define cover_list(...) do { } while (0)\n#endif\n\n\n// ------------------------------------------------------------\n// everything below this line are utilities for troubleshooting\n// ------------------------------------------------------------\n\n// simple timer for performance measurements\n// toggle the '#if 1' to get a baseline for the performance penalty added by the measurement\nstruct PerformanceTimer\n{\n#if 1\n\tint64_t total_ns;\n\n\tPerformanceTimer() {\n\t\ttotal_ns = 0;\n\t}\n\n\tstatic int64_t query() {\n# ifdef _WIN32\n\t\treturn 0;\n# elif defined(RUSAGE_SELF)\n\t\tstruct rusage rusage;\n\t\tint64_t t = 0;\n\t\tfor (int who : {RUSAGE_SELF, RUSAGE_CHILDREN}) {\n\t\t\tif (getrusage(who, &rusage) == -1) {\n\t\t\t\tlog_cmd_error(\"getrusage failed!\\n\");\n\t\t\t\tlog_abort();\n\t\t\t}\n\t\t\tt += 1000000000ULL * (int64_t) rusage.ru_utime.tv_sec + (int64_t) rusage.ru_utime.tv_usec * 1000ULL;\n\t\t\tt += 1000000000ULL * (int64_t) rusage.ru_stime.tv_sec + (int64_t) rusage.ru_stime.tv_usec * 1000ULL;\n\t\t}\n\t\treturn t;\n# else\n# error \"Don't know how to measure per-process CPU time. Need alternative method (times()/clocks()/gettimeofday()?).\"\n# endif\n\t}\n\n\tvoid reset() {\n\t\ttotal_ns = 0;\n\t}\n\n\tvoid begin() {\n\t\ttotal_ns -= query();\n\t}\n\n\tvoid end() {\n\t\ttotal_ns += query();\n\t}\n\n\tfloat sec() const {\n\t\treturn total_ns * 1e-9f;\n\t}\n#else\n\tstatic int64_t query() { return 0; }\n\tvoid reset() { }\n\tvoid begin() { }\n\tvoid end() { }\n\tfloat sec() const { return 0; }\n#endif\n};\n\n// simple API for quickly dumping values when debugging\n\nstatic inline void log_dump_val_worker(short v) { log(\"%d\", v); }\nstatic inline void log_dump_val_worker(unsigned short v) { log(\"%u\", v); }\nstatic inline void log_dump_val_worker(int v) { log(\"%d\", v); }\nstatic inline void log_dump_val_worker(unsigned int v) { log(\"%u\", v); }\nstatic inline void log_dump_val_worker(long int v) { log(\"%ld\", v); }\nstatic inline void log_dump_val_worker(unsigned long int v) { log(\"%lu\", v); }\n#ifndef _WIN32\nstatic inline void log_dump_val_worker(long long int v) { log(\"%lld\", v); }\nstatic inline void log_dump_val_worker(unsigned long long int v) { log(\"%lld\", v); }\n#endif\nstatic inline void log_dump_val_worker(char c) { log(c >= 32 && c < 127 ? \"'%c'\" : \"'\\\\x%02x'\", c); }\nstatic inline void log_dump_val_worker(unsigned char c) { log(c >= 32 && c < 127 ? \"'%c'\" : \"'\\\\x%02x'\", c); }\nstatic inline void log_dump_val_worker(bool v) { log(\"%s\", v ? \"true\" : \"false\"); }\nstatic inline void log_dump_val_worker(double v) { log(\"%f\", v); }\nstatic inline void log_dump_val_worker(char *v) { log(\"%s\", v); }\nstatic inline void log_dump_val_worker(const char *v) { log(\"%s\", v); }\nstatic inline void log_dump_val_worker(std::string v) { log(\"%s\", v.c_str()); }\nstatic inline void log_dump_val_worker(PerformanceTimer p) { log(\"%f seconds\", p.sec()); }\nstatic inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); }\nvoid log_dump_val_worker(RTLIL::IdString v);\nvoid log_dump_val_worker(RTLIL::SigSpec v);\nvoid log_dump_val_worker(RTLIL::State v);\n\ntemplate<typename K, typename T, typename OPS> static inline void log_dump_val_worker(dict<K, T, OPS> &v);\ntemplate<typename K, typename OPS> static inline void log_dump_val_worker(pool<K, OPS> &v);\ntemplate<typename K> static inline void log_dump_val_worker(std::vector<K> &v);\ntemplate<typename T> static inline void log_dump_val_worker(T *ptr);\n\ntemplate<typename K, typename T, typename OPS>\nstatic inline void log_dump_val_worker(dict<K, T, OPS> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it.first);\n\t\tlog(\": \");\n\t\tlog_dump_val_worker(it.second);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename K, typename OPS>\nstatic inline void log_dump_val_worker(pool<K, OPS> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename K>\nstatic inline void log_dump_val_worker(std::vector<K> &v) {\n\tlog(\"{\");\n\tbool first = true;\n\tfor (auto &it : v) {\n\t\tlog(first ? \" \" : \", \");\n\t\tlog_dump_val_worker(it);\n\t\tfirst = false;\n\t}\n\tlog(\" }\");\n}\n\ntemplate<typename T>\nstatic inline void log_dump_val_worker(T *ptr) { log(\"%p\", ptr); }\n\ntemplate<typename T, typename ... Args>\nvoid log_dump_args_worker(const char *p, T first, Args ... args)\n{\n\tint next_p_state = 0;\n\tconst char *next_p = p;\n\twhile (*next_p && (next_p_state != 0 || *next_p != ',')) {\n\t\tif (*next_p == '\"')\n\t\t\tdo {\n\t\t\t\tnext_p++;\n\t\t\t\twhile (*next_p == '\\\\' && *(next_p + 1))\n\t\t\t\t\tnext_p += 2;\n\t\t\t} while (*next_p && *next_p != '\"');\n\t\tif (*next_p == '\\'') {\n\t\t\tnext_p++;\n\t\t\tif (*next_p == '\\\\')\n\t\t\t\tnext_p++;\n\t\t\tif (*next_p)\n\t\t\t\tnext_p++;\n\t\t}\n\t\tif (*next_p == '(' || *next_p == '[' || *next_p == '{')\n\t\t\tnext_p_state++;\n\t\tif ((*next_p == ')' || *next_p == ']' || *next_p == '}') && next_p_state > 0)\n\t\t\tnext_p_state--;\n\t\tnext_p++;\n\t}\n\tlog(\"\\n\\t%.*s => \", int(next_p - p), p);\n\tif (*next_p == ',')\n\t\tnext_p++;\n\twhile (*next_p == ' ' || *next_p == '\\t' || *next_p == '\\r' || *next_p == '\\n')\n\t\tnext_p++;\n\tlog_dump_val_worker(first);\n\tlog_dump_args_worker(next_p, args ...);\n}\n\n#define log_dump(...) do { \\\n\tlog(\"DEBUG DUMP IN %s AT %s:%d:\", __PRETTY_FUNCTION__, __FILE__, __LINE__); \\\n\tlog_dump_args_worker(#__VA_ARGS__, __VA_ARGS__); \\\n\tlog(\"\\n\"); \\\n} while (0)\n\nYOSYS_NAMESPACE_END\n\n#endif\n",
package/gen/share/quicklogic/qlf_k6n10f/bram_types_sim.v CHANGED
@@ -1,5 +1,5 @@
1
1
  // **AUTOGENERATED FILE** **DO NOT EDIT**
2
- // Generated by ../yosys-src/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py at 2024-01-17 01:04:10.547695+00:00
2
+ // Generated by ../yosys-src/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py at 2024-01-20 01:31:51.331963+00:00
3
3
  `timescale 1ns /10ps
4
4
 
5
5
  module TDP36K_BRAM_A_X1_B_X1_nonsplit (
package/gen/yosys.core.wasm CHANGED
Binary file
package/package.json CHANGED
@@ -1,6 +1,6 @@
1
1
  {
2
2
  "name": "@yowasp/yosys",
3
- "version": "0.37.647",
3
+ "version": "0.38.21-dev.654",
4
4
  "description": "Yosys Open SYnthesis Suite",
5
5
  "author": "Catherine <whitequark@whitequark.org>",
6
6
  "license": "ISC",
@@ -21,19 +21,19 @@
21
21
  "gen/share/"
22
22
  ],
23
23
  "exports": {
24
- "default": "./gen/bundle.js",
25
- "types": "./lib/api.d.ts"
24
+ "types": "./lib/api.d.ts",
25
+ "default": "./gen/bundle.js"
26
26
  },
27
27
  "types": "./lib/api.d.ts",
28
28
  "devDependencies": {
29
29
  "@bytecodealliance/jco": "0.14.2",
30
- "@yowasp/runtime": "6.0.34",
30
+ "@yowasp/runtime": "7.0.35",
31
31
  "esbuild": "^0.19.8"
32
32
  },
33
33
  "scripts": {
34
34
  "transpile": "jco new ../yosys-build/yosys.wasm --wasi-command --output yosys.wasm && jco transpile yosys.wasm --instantiation async --no-typescript --no-namespaced-exports --map 'wasi:io/*=runtime#io' --map 'wasi:cli/*=runtime#cli' --map 'wasi:clocks/*=runtime#*' --map 'wasi:filesystem/*=runtime#fs' --map 'wasi:random/*=runtime#random' --out-dir gen/",
35
35
  "pack": "yowasp-pack-resources gen/resources-yosys.js gen ../yosys-build/share",
36
- "build": "esbuild --bundle lib/api.js --outfile=gen/bundle.js --format=esm --platform=node",
36
+ "build": "esbuild --bundle lib/api.js --outfile=gen/bundle.js --format=esm --platform=node --external:./resources-*.js",
37
37
  "all": "npm run transpile && npm run pack && npm run build"
38
38
  }
39
39
  }