@vessel-dsp/compiler 0.8.1 → 0.14.0

package/dist/fixtures/circuits.d.ts

@@ -1476,11 +1476,11 @@ export declare const packagedOptocoupler: string;
  * placeholders and VTL5C2's own datasheet -- cited in the packet's own
  * `SelectedLaneLedCurrentToResistanceLaw` property (R@1mA=5.5k, R@10mA=800, R@40mA=200,
  * dark>=1M) -- was never fit to a law at all. `part-catalog.ts`'s dedicated VTL5C2 entry carries
- * that fit now (`ldrPowerLawCoefficientOhms`/`ldrPowerLawExponent`); this fixture is what keeps it
- * pinned, since nothing else in this suite exercises it.
+ * those three anchors as a measured table now (`ldrTableCurrentAmps`/`ldrTableOhms`); this
+ * fixture is what keeps it pinned, since nothing else in this suite exercises it.
  *
  * **Bias.** `R_LED` (7k2 from the 9 V rail) puts the LED within a few percent of the datasheet's
- * 1 mA anchor -- close enough that a regression in the fit or an accidental fallback to the generic
+ * 1 mA anchor -- close enough that a regression in the table or an accidental fallback to the generic
  * exponential moves the verdict, not so exact that the fixture is fragile to the diode law's own
  * rounding. `RLOAD` (10k from output to ground) turns the LDR into a divider so its resistance is
  * what decides the gain, rather than leaving `ldrA`/`ldrB` floating in series with nothing to load
@@ -1488,7 +1488,7 @@ export declare const packagedOptocoupler: string;
  *
  * **What this proves and what it cannot** -- same limit `emitOptocoupler`'s own comment states for
  * every optocoupler resident: the from-source deck's LDR side is a `B`-source that *restates* the
- * runtime's own formula (now the power law, when the device carries one) rather than deriving it
+ * runtime's own formula (now the table, when the device carries one) rather than deriving it
  * independently, so ngspice cannot catch an error shared between the restatement and the runtime.
  * What it grades independently is the pin mapping, the part-specific `ldrMinOhms`/`ldrMaxOhms`
  * clamp, and -- because `source-to-spice.ts` reads the law fields off the same compiled program,
@@ -1674,6 +1674,31 @@ export declare const bufferedMechanicalDpdt: string;
  * requirements `findBistableLatches` states, so this is derived `buffered` by the latch.
  */
 export declare const flipFlopBypassLatched: string;
+/**
+ * Flip-flop with a control in exactly one gated path, so the engaged side derives
+ * from connectivity rather than the fallback: `Q_FF1`'s collector steers the effect
+ * FET (`Q_GATE_FX`), whose drain reaches the `Drive` pot one resistor away, while
+ * `Q_FF2`'s dry FET (`Q_GATE_DRY`) reaches nothing any control varies. The latch is
+ * therefore `connectivity`-provenance with `Q_FF1` off when engaged and `Q_FF2` on,
+ * which is what the polarity test in `latch-seed.test.ts` asserts through the seed
+ * and the steering stamps of a compiled program. The `Drive` wiper is loaded by
+ * `R_WIPER` because a floating wiper is a structural refusal, not a test detail.
+ */
+export declare const flipFlopEngagedPolarity: string;
+/**
+ * Flip-flop nobody can read out (no control in either gated path, so the side
+ * falls back) with a CHECK LED whose cathode sits directly on `Q_FF2`'s collector.
+ * The LED resolves the side the derivation cannot: provenance `effect-status-led`,
+ * `Q_FF2` ON when engaged, seed on base 24 rather than the fallback's 23.
+ */
+export declare const flipFlopLedSeed: string;
+/**
+ * `flipFlopEngagedPolarity` with a CHECK LED whose cathode sits directly on the
+ * *gating* member's collector (`Q_FF1`): connectivity holds `Q_FF2` ON when engaged
+ * while the LED indicates `Q_FF1`. The detector keeps the connectivity answer and
+ * raises `latch-engaged-disagrees` naming both — never a silent choice.
+ */
+export declare const flipFlopLedDisagrees: string;
 /**
  * The same JFET gates driven by two BJTs that are **not** cross-coupled (an inverter chain), so
  * the latch detector finds nothing and the `buffered` verdict rests on the JFET-plus-BJTs
@@ -1749,6 +1774,64 @@ export declare const pt2399ClockDerivedDelay: string;
  * whole tremolo depends on.
  */
 export declare const linearVcaCell: (controlVolts: number, comVolts?: number) => string;
+/**
+ * Synthetic stand-in for the CS-3 VCA stage: bare-pin uPC1252H2 in strict datasheet pin
+ * order (the CS-3 `IC3` shell's own spelling: `pin1`..`pin8` with `role: pin`, so every
+ * terminal folds to a null role token and the entry binds positionally). Input jack 1
+ * through Rin 14.2k into the VCA input (node 3, ground-referenced current input),
+ * VCA output (node 4) into Ro 14.3k to ground, both GC pins on the DC control node
+ * (node 5, CS-3 node 70's role), ref/GND/ISET/Vc on ground (node 0).
+ *
+ * Rin is 14.2k rather than the pedal's R9 10k so the cell's input current per source
+ * volt matches the pedal's engine-measured 0.7x buffer loss (0.7/10k = 1/14.3k), and
+ * Ro is 14.3k (= Rin + 100) so the input divider times the input impedance times the
+ * load is exactly unity: renders read the law's own voltage gain, and session
+ * comparisons read the law rather than either divider. The law reads the smoothed
+ * SUSTAIN-coupled rest plus the smoothed log-domain envelope (attack 0.5 ms /
+ * release 50 ms with depth-varying release), so one static-control program serves
+ * the transfer proofs below: sweep the DC control for the external path, sweep the
+ * input amplitude for the internal path, and pin control at the pedal's GC rest
+ * offsets to reproduce the re-traced CS-3's operating conditions per SUSTAIN setting.
+ */
+export declare const dbxVcaCell: (controlVolts: number) => string;
+/**
+ * Pedal-program stand-in for the session-8 release work: the `dbxVcaCell` VCA
+ * stage (same Rin/Ro transimpedance, loaded at LEVEL 1 by the full 50k LEVEL
+ * track to an exact, hand-computed factor) with a SUSTAIN-coupled control
+ * node and a LEVEL output divider, i.e. the law in its pedal biasing rather
+ * than the bare cell. The control node is dialed to the engine-measured V70
+ * for the SUSTAIN setting (4.6325 + sustainPos*0.0403 V, the rest span the v4
+ * fit is joint against); the SUSTAIN-to-V70 divider itself lives in the
+ * packet, the law reads its result. LEVEL is a linear 50k pot to ground
+ * (wiper to the output jack); release tests run it at 1. Unlike the cell,
+ * this program exercises the law end-to-end (control path plus output stage)
+ * under the session-8 stimulus: history, gap, pip, probe.
+ */
+export declare const dbxVcaPedalChain: (sustainPos: number, levelPos: number) => string;
+/**
+ * The same VCA stage spelled the way `boss-lm-2`'s `IC1_UPC1252H2` spells it: every pin
+ * carries a role suffix (`pin1_input` ... `pin8_output`), so each terminal folds to a
+ * real role token and the entry binds by clean role bijection instead of positionally.
+ * Same nodes and numbers as `dbxVcaCell`; the law and its transfer proof live there.
+ */
+export declare const dbxVcaNamedCell: (controlVolts: number) => string;
+/**
+ * Synthetic stand-in for the re-traced CS-3 detector/sustain buffer: bare-pin BA718 in
+ * strict datasheet pin order (`pin1`..`pin9` with `role: pin`), channel A as a follower
+ * buffering the input into channel B as a second follower driving the output jack. Both
+ * followers run at mid-rail (the render drives 4.5 V +/- 0.05), inside the 9 V / ground
+ * rails on pins 1+9 / pin 5. Compiling this fixture proves the 9-pin dual admission:
+ * the entry must expand to two `ideal-opamp` sections (pins [3,2,1] and [5,6,7] in the
+ * [+, -, out] order) instead of opening with registry-arity-mismatch.
+ */
+export declare const ba718DualCell: () => string;
+/**
+ * The older BA718 5-pin single-section capture: channel 1's five pins in declaration
+ * order (VCC, OUT1, I1, IN1, VEE) as a follower buffering the input to the output jack.
+ * The 9-pin dual entry must not shadow it: `identify` tells the two apart by arity, so
+ * this still expands to exactly one `ideal-opamp` section.
+ */
+export declare const ba718SingleCell: () => string;
 /**
  * Bypass-engagement contract: the switchedDivider graph (a shunt switch the signal routes
  * around, so the connectivity default is open/0) steered by control SW1, with audio.bypass

package/dist/fixtures/circuits.d.ts.map

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package/dist/fixtures/circuits.js

@@ -12231,11 +12231,11 @@ wires: []
  * placeholders and VTL5C2's own datasheet -- cited in the packet's own
  * `SelectedLaneLedCurrentToResistanceLaw` property (R@1mA=5.5k, R@10mA=800, R@40mA=200,
  * dark>=1M) -- was never fit to a law at all. `part-catalog.ts`'s dedicated VTL5C2 entry carries
- * that fit now (`ldrPowerLawCoefficientOhms`/`ldrPowerLawExponent`); this fixture is what keeps it
- * pinned, since nothing else in this suite exercises it.
+ * those three anchors as a measured table now (`ldrTableCurrentAmps`/`ldrTableOhms`); this
+ * fixture is what keeps it pinned, since nothing else in this suite exercises it.
  *
  * **Bias.** `R_LED` (7k2 from the 9 V rail) puts the LED within a few percent of the datasheet's
- * 1 mA anchor -- close enough that a regression in the fit or an accidental fallback to the generic
+ * 1 mA anchor -- close enough that a regression in the table or an accidental fallback to the generic
  * exponential moves the verdict, not so exact that the fixture is fragile to the diode law's own
  * rounding. `RLOAD` (10k from output to ground) turns the LDR into a divider so its resistance is
  * what decides the gain, rather than leaving `ldrA`/`ldrB` floating in series with nothing to load
@@ -12243,7 +12243,7 @@ wires: []
  *
  * **What this proves and what it cannot** -- same limit `emitOptocoupler`'s own comment states for
  * every optocoupler resident: the from-source deck's LDR side is a `B`-source that *restates* the
- * runtime's own formula (now the power law, when the device carries one) rather than deriving it
+ * runtime's own formula (now the table, when the device carries one) rather than deriving it
  * independently, so ngspice cannot catch an error shared between the restatement and the runtime.
  * What it grades independently is the pin mapping, the part-specific `ldrMinOhms`/`ldrMaxOhms`
  * clamp, and -- because `source-to-spice.ts` reads the law fields off the same compiled program,
@@ -13726,6 +13726,147 @@ export const flipFlopBypassLatched = bypassFixture("Flip-Flop Bypass Latched Fix
     jfet("Q_GATE_IN", 1, 25, 10) +
     jfet("Q_GATE_OUT", 11, 26, 2) +
     bypassCore(10, 11));
+/**
+ * Flip-flop with a control in exactly one gated path, so the engaged side derives
+ * from connectivity rather than the fallback: `Q_FF1`'s collector steers the effect
+ * FET (`Q_GATE_FX`), whose drain reaches the `Drive` pot one resistor away, while
+ * `Q_FF2`'s dry FET (`Q_GATE_DRY`) reaches nothing any control varies. The latch is
+ * therefore `connectivity`-provenance with `Q_FF1` off when engaged and `Q_FF2` on,
+ * which is what the polarity test in `latch-seed.test.ts` asserts through the seed
+ * and the steering stamps of a compiled program. The `Drive` wiper is loaded by
+ * `R_WIPER` because a floating wiper is a structural refusal, not a test detail.
+ */
+export const flipFlopEngagedPolarity = `${header("Flip-Flop Engaged Polarity Fixture")}audio:
+  input: JIN
+  output: JOUT
+  bypass:
+    switch: SW1
+    engagedPosition: 0
+deviceInterface:
+  controls:
+    - id: Bypass
+      label: BYPASS
+      kind: footswitch
+      role: bypass
+    - id: Drive
+      label: DRIVE
+      kind: knob
+      role: drive
+components:
+${jacks}${supply9(9) +
+    resistor("R_C1", 9, 21, "10k") +
+    resistor("R_C2", 9, 22, "10k") +
+    bjt("Q_FF1", 21, 23, 0) +
+    bjt("Q_FF2", 22, 24, 0) +
+    resistor("R_X1", 21, 24, "47k") +
+    resistor("R_X2", 22, 23, "47k") +
+    momentaryToGround("SW1", 30) +
+    capacitor("C_SW", 30, 23, "1u") +
+    resistor("R_G1", 21, 25, "1meg") +
+    resistor("R_G2", 22, 26, "1meg") +
+    jfet("Q_GATE_FX", 1, 25, 10) +
+    jfet("Q_GATE_DRY", 11, 26, 2) +
+    resistor("R_FX1", 1, 41, "1k") +
+    part("VR_FX", "potentiometer", "Circuit.Potentiometer", [
+        ["end1", "end", 41],
+        ["wiper", "wiper", 40],
+        ["end2", "end", 0],
+    ], { Resistance: "10k", ControlId: "Drive" }) +
+    resistor("R_WIPER", 40, 2, "100k") +
+    bypassCore(10, 11)}`;
+/**
+ * Flip-flop nobody can read out (no control in either gated path, so the side
+ * falls back) with a CHECK LED whose cathode sits directly on `Q_FF2`'s collector.
+ * The LED resolves the side the derivation cannot: provenance `effect-status-led`,
+ * `Q_FF2` ON when engaged, seed on base 24 rather than the fallback's 23.
+ */
+export const flipFlopLedSeed = `${header("Flip-Flop LED Seed Fixture")}audio:
+  input: JIN
+  output: JOUT
+  bypass:
+    switch: SW1
+    engagedPosition: 0
+deviceInterface:
+  controls:
+    - id: Bypass
+      label: BYPASS
+      kind: footswitch
+      role: bypass
+    - id: D_LED
+      label: CHECK
+      kind: led
+      role: effect-status
+components:
+${jacks}${supply9(9) +
+    resistor("R_C1", 9, 21, "10k") +
+    resistor("R_C2", 9, 22, "10k") +
+    bjt("Q_FF1", 21, 23, 0) +
+    bjt("Q_FF2", 22, 24, 0) +
+    resistor("R_X1", 21, 24, "47k") +
+    resistor("R_X2", 22, 23, "47k") +
+    momentaryToGround("SW1", 30) +
+    capacitor("C_SW", 30, 23, "1u") +
+    resistor("R_G1", 21, 25, "1meg") +
+    resistor("R_G2", 22, 26, "1meg") +
+    jfet("Q_GATE_FX", 1, 25, 10) +
+    jfet("Q_GATE_DRY", 11, 26, 2) +
+    part("D_LED", "led", "Circuit.LED", [
+        ["anode", "anode", 9],
+        ["cathode", "cathode", 22],
+    ], { Color: "red" }) +
+    bypassCore(10, 11)}`;
+/**
+ * `flipFlopEngagedPolarity` with a CHECK LED whose cathode sits directly on the
+ * *gating* member's collector (`Q_FF1`): connectivity holds `Q_FF2` ON when engaged
+ * while the LED indicates `Q_FF1`. The detector keeps the connectivity answer and
+ * raises `latch-engaged-disagrees` naming both — never a silent choice.
+ */
+export const flipFlopLedDisagrees = `${header("Flip-Flop LED Disagrees Fixture")}audio:
+  input: JIN
+  output: JOUT
+  bypass:
+    switch: SW1
+    engagedPosition: 0
+deviceInterface:
+  controls:
+    - id: Bypass
+      label: BYPASS
+      kind: footswitch
+      role: bypass
+    - id: Drive
+      label: DRIVE
+      kind: knob
+      role: drive
+    - id: D_LED
+      label: CHECK
+      kind: led
+      role: effect-status
+components:
+${jacks}${supply9(9) +
+    resistor("R_C1", 9, 21, "10k") +
+    resistor("R_C2", 9, 22, "10k") +
+    bjt("Q_FF1", 21, 23, 0) +
+    bjt("Q_FF2", 22, 24, 0) +
+    resistor("R_X1", 21, 24, "47k") +
+    resistor("R_X2", 22, 23, "47k") +
+    momentaryToGround("SW1", 30) +
+    capacitor("C_SW", 30, 23, "1u") +
+    resistor("R_G1", 21, 25, "1meg") +
+    resistor("R_G2", 22, 26, "1meg") +
+    jfet("Q_GATE_FX", 1, 25, 10) +
+    jfet("Q_GATE_DRY", 11, 26, 2) +
+    resistor("R_FX1", 1, 41, "1k") +
+    part("VR_FX", "potentiometer", "Circuit.Potentiometer", [
+        ["end1", "end", 41],
+        ["wiper", "wiper", 40],
+        ["end2", "end", 0],
+    ], { Resistance: "10k", ControlId: "Drive" }) +
+    resistor("R_WIPER", 40, 2, "100k") +
+    part("D_LED", "led", "Circuit.LED", [
+        ["anode", "anode", 9],
+        ["cathode", "cathode", 21],
+    ], { Color: "red" }) +
+    bypassCore(10, 11)}`;
 /**
  * The same JFET gates driven by two BJTs that are **not** cross-coupled (an inverter chain), so
  * the latch detector finds nothing and the `buffered` verdict rests on the JFET-plus-BJTs
@@ -13994,6 +14135,258 @@ export const linearVcaCell = (controlVolts, comVolts = 0) => {
         part("VCTRL", "voltage-source", "Circuit.VoltageSource", [["plus", "positive", 5], ["minus", "negative", com]], { Voltage: `${controlVolts}` }) +
         comSource);
 };
+/**
+ * Synthetic stand-in for the CS-3 VCA stage: bare-pin uPC1252H2 in strict datasheet pin
+ * order (the CS-3 `IC3` shell's own spelling: `pin1`..`pin8` with `role: pin`, so every
+ * terminal folds to a null role token and the entry binds positionally). Input jack 1
+ * through Rin 14.2k into the VCA input (node 3, ground-referenced current input),
+ * VCA output (node 4) into Ro 14.3k to ground, both GC pins on the DC control node
+ * (node 5, CS-3 node 70's role), ref/GND/ISET/Vc on ground (node 0).
+ *
+ * Rin is 14.2k rather than the pedal's R9 10k so the cell's input current per source
+ * volt matches the pedal's engine-measured 0.7x buffer loss (0.7/10k = 1/14.3k), and
+ * Ro is 14.3k (= Rin + 100) so the input divider times the input impedance times the
+ * load is exactly unity: renders read the law's own voltage gain, and session
+ * comparisons read the law rather than either divider. The law reads the smoothed
+ * SUSTAIN-coupled rest plus the smoothed log-domain envelope (attack 0.5 ms /
+ * release 50 ms with depth-varying release), so one static-control program serves
+ * the transfer proofs below: sweep the DC control for the external path, sweep the
+ * input amplitude for the internal path, and pin control at the pedal's GC rest
+ * offsets to reproduce the re-traced CS-3's operating conditions per SUSTAIN setting.
+ */
+export const dbxVcaCell = (controlVolts) => `${header("dbx VCA Cell")}components:
+  - id: JIN
+    kind: jack
+    name: VCA_IN
+    sourceTypeName: Circuit.Input
+    origin:
+      x: -200
+      y: 0
+    rotation: 0
+    flipped: false
+    terminals:
+      - name: tip
+        node: 1
+        position:
+          x: -200
+          y: 0
+    properties: {}
+  - id: JOUT
+    kind: jack
+    name: VCA_OUT
+    sourceTypeName: Circuit.Output
+    origin:
+      x: 200
+      y: 0
+    rotation: 0
+    flipped: false
+    terminals:
+      - name: tip
+        node: 4
+        position:
+          x: 200
+          y: 0
+    properties: {}
+` +
+    resistor("RIN", 1, 3, "14.2k") +
+    resistor("RO", 4, 0, "14.3k") +
+    part("U1", "ic", "Circuit.IC", [["pin1", "pin", 3], ["pin2", "pin", 5], ["pin3", "pin", 5], ["pin4", "pin", 0], ["pin5", "pin", 0], ["pin6", "pin", 0], ["pin7", "pin", 0], ["pin8", "pin", 4]], { PartNumber: "uPC1252H2" }) +
+    part("VCTRL", "voltage-source", "Circuit.VoltageSource", [["plus", "positive", 5], ["minus", "negative", 0]], { Voltage: `${controlVolts}` });
+/**
+ * Pedal-program stand-in for the session-8 release work: the `dbxVcaCell` VCA
+ * stage (same Rin/Ro transimpedance, loaded at LEVEL 1 by the full 50k LEVEL
+ * track to an exact, hand-computed factor) with a SUSTAIN-coupled control
+ * node and a LEVEL output divider, i.e. the law in its pedal biasing rather
+ * than the bare cell. The control node is dialed to the engine-measured V70
+ * for the SUSTAIN setting (4.6325 + sustainPos*0.0403 V, the rest span the v4
+ * fit is joint against); the SUSTAIN-to-V70 divider itself lives in the
+ * packet, the law reads its result. LEVEL is a linear 50k pot to ground
+ * (wiper to the output jack); release tests run it at 1. Unlike the cell,
+ * this program exercises the law end-to-end (control path plus output stage)
+ * under the session-8 stimulus: history, gap, pip, probe.
+ */
+export const dbxVcaPedalChain = (sustainPos, levelPos) => {
+    const controlVolts = 4.6325 + sustainPos * 0.0403;
+    return (`${header("dbx VCA Pedal Chain")}deviceInterface:
+  controls:
+    - id: Level
+      label: Level
+      kind: knob
+      role: output-level
+      taper: linear
+components:
+  - id: JIN
+    kind: jack
+    name: PEDAL_IN
+    sourceTypeName: Circuit.Input
+    origin:
+      x: -200
+      y: 0
+    rotation: 0
+    flipped: false
+    terminals:
+      - name: tip
+        node: 1
+        position:
+          x: -200
+          y: 0
+    properties: {}
+  - id: JOUT
+    kind: jack
+    name: PEDAL_OUT
+    sourceTypeName: Circuit.Output
+    origin:
+      x: 200
+      y: 0
+    rotation: 0
+    flipped: false
+    terminals:
+      - name: tip
+        node: 2
+        position:
+          x: 200
+          y: 0
+    properties: {}
+` +
+        resistor("RIN", 1, 3, "14.2k") +
+        resistor("RO", 4, 0, "14.3k") +
+        part("U1", "ic", "Circuit.IC", [["pin1", "pin", 3], ["pin2", "pin", 5], ["pin3", "pin", 5], ["pin4", "pin", 0], ["pin5", "pin", 0], ["pin6", "pin", 0], ["pin7", "pin", 0], ["pin8", "pin", 4]], { PartNumber: "uPC1252H2" }) +
+        part("VCTRL", "voltage-source", "Circuit.VoltageSource", [["plus", "positive", 5], ["minus", "negative", 0]], { Voltage: `${controlVolts}` }) +
+        part("VRLEVEL", "potentiometer", "Circuit.Potentiometer", [["end1", "end", 4], ["wiper", "wiper", 2], ["end2", "end", 0]], { Resistance: "50k", ControlId: "Level", Wipe: `${levelPos}` }));
+};
+/**
+ * The same VCA stage spelled the way `boss-lm-2`'s `IC1_UPC1252H2` spells it: every pin
+ * carries a role suffix (`pin1_input` ... `pin8_output`), so each terminal folds to a
+ * real role token and the entry binds by clean role bijection instead of positionally.
+ * Same nodes and numbers as `dbxVcaCell`; the law and its transfer proof live there.
+ */
+export const dbxVcaNamedCell = (controlVolts) => `${header("dbx VCA Named Cell")}components:
+  - id: JIN
+    kind: jack
+    name: VCA_IN
+    sourceTypeName: Circuit.Input
+    origin:
+      x: -200
+      y: 0
+    rotation: 0
+    flipped: false
+    terminals:
+      - name: tip
+        node: 1
+        position:
+          x: -200
+          y: 0
+    properties: {}
+  - id: JOUT
+    kind: jack
+    name: VCA_OUT
+    sourceTypeName: Circuit.Output
+    origin:
+      x: 200
+      y: 0
+    rotation: 0
+    flipped: false
+    terminals:
+      - name: tip
+        node: 4
+        position:
+          x: 200
+          y: 0
+    properties: {}
+` +
+    resistor("RIN", 1, 3, "14.2k") +
+    resistor("RO", 4, 0, "14.3k") +
+    part("U1", "ic", "Circuit.IC", [["pin1_input", "pin", 3], ["pin2_gc2", "pin", 5], ["pin3_gc1", "pin", 5], ["pin4_symmetry", "pin", 0], ["pin5_iset", "pin", 0], ["pin6_ground_reference", "pin", 0], ["pin7_vcc", "pin", 0], ["pin8_output", "pin", 4]], { PartNumber: "uPC1252H2" }) +
+    part("VCTRL", "voltage-source", "Circuit.VoltageSource", [["plus", "positive", 5], ["minus", "negative", 0]], { Voltage: `${controlVolts}` });
+/**
+ * Synthetic stand-in for the re-traced CS-3 detector/sustain buffer: bare-pin BA718 in
+ * strict datasheet pin order (`pin1`..`pin9` with `role: pin`), channel A as a follower
+ * buffering the input into channel B as a second follower driving the output jack. Both
+ * followers run at mid-rail (the render drives 4.5 V +/- 0.05), inside the 9 V / ground
+ * rails on pins 1+9 / pin 5. Compiling this fixture proves the 9-pin dual admission:
+ * the entry must expand to two `ideal-opamp` sections (pins [3,2,1] and [5,6,7] in the
+ * [+, -, out] order) instead of opening with registry-arity-mismatch.
+ */
+export const ba718DualCell = () => `${header("BA718 Dual Cell")}components:
+  - id: JIN
+    kind: jack
+    name: BUF_IN
+    sourceTypeName: Circuit.Input
+    origin:
+      x: -200
+      y: 0
+    rotation: 0
+    flipped: false
+    terminals:
+      - name: tip
+        node: 1
+        position:
+          x: -200
+          y: 0
+    properties: {}
+  - id: JOUT
+    kind: jack
+    name: BUF_OUT
+    sourceTypeName: Circuit.Output
+    origin:
+      x: 200
+      y: 0
+    rotation: 0
+    flipped: false
+    terminals:
+      - name: tip
+        node: 5
+        position:
+          x: 200
+          y: 0
+    properties: {}
+` +
+    resistor("RIN", 1, 3, "10k") +
+    part("U1", "ic", "Circuit.OpAmp", [["pin1", "pin", 6], ["pin2", "pin", 4], ["pin3", "pin", 4], ["pin4", "pin", 3], ["pin5", "pin", 0], ["pin6", "pin", 4], ["pin7", "pin", 5], ["pin8", "pin", 5], ["pin9", "pin", 6]], { PartNumber: "BA718" }) +
+    part("V9", "voltage-source", "Circuit.VoltageSource", [["plus", "positive", 6], ["minus", "negative", 0]], { Voltage: "9" });
+/**
+ * The older BA718 5-pin single-section capture: channel 1's five pins in declaration
+ * order (VCC, OUT1, I1, IN1, VEE) as a follower buffering the input to the output jack.
+ * The 9-pin dual entry must not shadow it: `identify` tells the two apart by arity, so
+ * this still expands to exactly one `ideal-opamp` section.
+ */
+export const ba718SingleCell = () => `${header("BA718 Single Cell")}components:
+  - id: JIN
+    kind: jack
+    name: BUF_IN
+    sourceTypeName: Circuit.Input
+    origin:
+      x: -200
+      y: 0
+    rotation: 0
+    flipped: false
+    terminals:
+      - name: tip
+        node: 1
+        position:
+          x: -200
+          y: 0
+    properties: {}
+  - id: JOUT
+    kind: jack
+    name: BUF_OUT
+    sourceTypeName: Circuit.Output
+    origin:
+      x: 200
+      y: 0
+    rotation: 0
+    flipped: false
+    terminals:
+      - name: tip
+        node: 5
+        position:
+          x: 200
+          y: 0
+    properties: {}
+` +
+    resistor("RIN", 1, 3, "10k") +
+    part("U1", "ic", "Circuit.OpAmp", [["pin1", "pin", 6], ["pin2", "pin", 5], ["pin3", "pin", 5], ["pin4", "pin", 3], ["pin5", "pin", 0]], { PartNumber: "BA718" }) +
+    part("V9", "voltage-source", "Circuit.VoltageSource", [["plus", "positive", 6], ["minus", "negative", 0]], { Voltage: "9" });
 /**
  * Bypass-engagement contract: the switchedDivider graph (a shunt switch the signal routes
  * around, so the connectivity default is open/0) steered by control SW1, with audio.bypass