@vessel-dsp/compiler 0.4.0 → 0.6.0

package/dist/part-catalog.js

@@ -9,9 +9,10 @@
 // them. So the generator and the lowering JSON were deleted and this file kept, rather than the
 // reverse: the hand edits are the corrections. Recovery point for both: `892cdcf6`.
 //
-// The electrical parameters that come from the device database
-// (`web/assets/registry/component-*-chips.json`, still the product's canonical device data) are
-// held in agreement with this file by `scripts/report-part-store-drift.ts`, not by generation.
+// The electrical parameters that come from the device database live in
+// `registry-data/` as cited values (`{ value, basis, source }`), and this file builds the
+// entries that carry them. `scripts/report-part-store-drift.ts` is gone (deleted with the
+// lowering-JSON generator); nothing re-runs a generator over this file.
 //
 // `registry.ts` deliberately holds no parts -- it is the shape and the matching rules, so the
 // compiler itself knows about no specific chip and `emptyRegistry` stays a legitimate
@@ -29,7 +30,32 @@
 // The one thing this file needs from an op-amp datasheet is **open-loop gain**. `ideal-opamp` takes
 // `openLoopGain` plus rails, and the rails are the pedal's rather than the part's, so a dual op-amp
 // is a complete model from one published number and its pinout.
-import { foldPartId } from "./registry.js";
+//
+// **Gain-bandwidth product is the second figure, and it lives in the data registry**
+// (`registry-data/opamp.ts`) rather than as a field on each entry, because one entry here
+// often covers parts whose datasheets print different products (the TL072/NE5532/LM358 entry
+// is one law over three datasheets). The TYP column is transcribed ("typical" here is that
+// datasheet's own TYP column for that part, not a generic typical value), never MIN or MAX,
+// never a graph read by eye, never a registry or curated-record number.
+// A part whose datasheet prints no TYP gain-bandwidth row is listed in
+// `opampGainBandwidthAbsent` with the reason and gets no figure, so its stamp is `null`
+// and the compile names it (`opamp-gain-bandwidth-default`).
+// Matching is by exact folded part id, as everywhere in this file: an id the datasheet
+// does not print is not covered because a sibling is.
+//
+// **Output swing is the third figure, and lives there too** (`registry-data/opamp.ts`): the
+// distance the output stops short of each rail, as a printed **pair** (positive side, negative
+// side) with the condition it was printed at (total supply, load) and how it is carried to a
+// pedal on another supply (`translation`, `"constant"` or `"proportional"`). TYP column only,
+// printed rows only; an id with no such row is listed in `opampOutputSwingAbsent` with the
+// reason and states no swing. Nearly every printed row is at +-15 V and nearly every pedal
+// runs at 9 V, so the carry is a named choice, and `opamp-law-default-parameters` names
+// every device it was carried for.
+import { foldPartId, opampOutputSwingOf } from "./registry.js";
+import { bjtRegistryRecords, chargePumpRegistryRecords, diodeRegistryRecords, findPartRegistryData, jfetRegistryRecords, mosfetRegistryRecords, opampGainBandwidthAbsent, opampOutputSwingAbsent, opampRegistryRecords, regulatorRegistryRecords, zenerRegistryRecords, communityProvenanceOf, } from "./registry-data/index.js";
+// The absent lists and the merged op-amp records live in `registry-data/opamp.ts` and are
+// re-exported here so their existing import sites keep working.
+export { opampGainBandwidthAbsent, opampOutputSwingAbsent, opampRegistryRecords, } from "./registry-data/index.js";
 /**
  * An op-amp section as the registry states it: the part's own gain, and no rails.
  */
@@ -77,11 +103,13 @@ function tubeLaw(partIds, law) {
  * So a newly covered zener renders its old forward behaviour exactly and only gains a
  * reverse knee; deriving the forward law is plan step 2's work, not this entry's.
  */
-function zenerLaw(partIds, breakdownVolts) {
+function zenerLaw(record) {
+    const breakdownVolts = zenerBreakdownVoltsOf(record);
     return {
-        partIds,
+        partIds: [...record.partIds],
         declaredTypes: [],
         terminalRoleGroups: [],
+        ...provisionalArmOf(record),
         model: {
             kind: "law",
             law: {
@@ -96,118 +124,430 @@ function zenerLaw(partIds, breakdownVolts) {
     };
 }
 /**
- * Every part id a `zenerLaw` entry covers, folded for comparison. `report-part-store-drift.ts`
- * keys its forward-law exclusion on this set -- a catalog product -- rather than on the
- * registry row's `type`, so a hand-fitted diode law that happens to sit on a zener id is
- * still graded, and a zener entry is never mistaken for a forward claim.
+ * The `provisionalParams` arm of a law entry built from a data record: the record's
+ * `community`-basis parameters with their source URLs, or absent when the record holds
+ * none. Spread into the built entry, so an entry with no provisional value is shaped
+ * exactly as before (the field stays absent, not empty).
  */
-// --- Switch JFETs: per-part silicon gate data, channel deliberately unrefined -----------------
-//
-// The JFET class default (`device-laws.ts`'s `case "jfet"`) is avowedly no part's values, and
-// its gate prefactor (`gateSaturationCurrent: 1e-5`, reused from the triode grid) parks a
-// series switch whose gate sits ~0.4 V above its channel in the junction's exponential foot,
-// rectifying microamp signal currents into the audio path. Measured 2026-10-06 on
-// `ibanez-ts9` Q102 (Vgs +0.392, gate peaks 5 uA): the engine's H2 sits at -29.6 dB there
-// against -57 to -64 dB on the physical reissue specimen and -77.9 dB with the FET replaced
-// by 100 ohm; killing only the gate terms reproduces the resistor swap to the printed digit,
-// and ngspice with the stock-card-equivalent NJF mapping agrees with the engine to 0.1/0.8 dB,
-// so the defect is the parameter value, not the solver. The TS9 H2 is channel-inert (a
-// 52-to-836-ohm Rds sweep moves it 0.2 dB), so the entry below refines the gate term only.
+function provisionalArmOf(record) {
+    const provisional = communityProvenanceOf(record);
+    return provisional.length === 0 ? {} : { provisionalParams: provisional };
+}
+/**
+ * Every part id a `zenerLaw` entry covers, folded for comparison: a hand-fitted diode law
+ * that happens to sit on a zener id is still graded as a forward claim, and a zener entry
+ * is never mistaken for one.
+ */
+// --- Wave-1 discrete builders: cited record -> law entry --------------------------------------
 //
-// The entry carries the class channel by construction, not by measurement:
-// `thresholdVolts`, `transconductance`, `channelLengthModulation` and `subthresholdVolts`
-// repeat the class default, and `device-laws.ts` reads only the gate term from a part
-// entry. The channel is rank-dependent (an unbinned 2SK30A spans IDSS 0.3-6.5 mA across
-// R/O/Y/GR), and the database row's beta.typ disagrees with `boss-sg-1-slow-gear`'s
-// recorded gain-cell island (report 4: the island's own Beta=1.2m reproduces its 59.9x,
-// beta.typ 0.0004664 would halve it), so refining the channel here would trade one
-// packet's fix for another's regression on evidence neither side owns. A rank-binned
-// channel fit belongs in the packet or a rank-suffixed entry, not here.
+// Stage-1 wired the bjt, mosfet, diode-forward and jfet-channel cases to read the registry
+// (document-typed > registry > class default, exact folded part id). These builders turn the
+// wave-1 `registry-data` records into the law entries those cases read. Every builder maps the
+// record's PRESENT parameters and gap-fills the rest with the class default the unregistered
+// path stamps -- the literals below repeat `device-laws.ts` (`SILICON_SATURATION_CURRENT`,
+// `SILICON_FORWARD_BETA`, reverseBeta 1, `THERMAL_VOLTAGE`, leakageAmps 0; the JFET/MOSFET
+// channel and gate constants; the diode forward defaults) BY VALUE, deliberately: importing
+// them would drag the stamping path into the catalog, and a drift between the two copies is
+// caught by the sparse-record test (`registry-discrete-wiring`), which stamps a one-parameter
+// entry and requires every omitted field to equal the empty-registry stamp.
 //
-// Provenance and uncertainty, stated rather than fitted: the gate transcribes the device
-// database's silicon-junction convention (`saturationCurrent.typ` 1e-14, the same constant
-// as `SILICON_SATURATION_CURRENT`); onset/scale stay class. The Toshiba 2SK30A sheet
-// (`parts/jfets/2SK30A/datasheets/toshiba-2sk30a.pdf`, curated in `parts/jfets/2SK30A.md`)
-// prints IDSS ranks, VGS(off) and Yfs, and no forward gate current at all (only reverse
-// IGSS). The gate IS is therefore a silicon-junction order choice, not a measured 2SK30A
-// forward current: it puts the foot current at switch biases three orders below signal
-// currents (verified H2-free for gateSaturationCurrent in {1e-7, 1e-8, 1e-9, 0}; 1e-14 sits
-// inside that verified-flat region at the repo's silicon constant). Never fitted to a specimen.
+// Bin and package spellings merge into the entry's `partIds`: `registryLawFor` matches whole
+// folded ids against `partIds` only, so an alias that stayed on the record would never match.
+// The data loader's uniqueness scope already covers ids plus aliases, so the merge cannot
+// introduce a collision the loader missed.
 //
-// Coverage is deliberately a single exact id: the part `ibanez-ts9` declares.
-// The match is `registryLawFor`'s whole folded id (`2sk30a`), with no prefix or
-// substring rule anywhere on the path, so `2SK30ATM`, `2SK30ATM-Y` and `2SK44SPC
-// do not match. `boss-cs-2` (2SK30ATM-Y), `boss-ds-1` (2SK30ATM), `boss-dm-2`
-// (2SK30ATM-Y) and `ibanez-ts808` (2SK44SPC) each need their own packet study
-// before their behaviour may move, so they stay on the class default until then.
-// `boss-sg-1-slow-gear` declares the same id; its gate sits 0.5 V below onset in
-// every state, so the gate refinement is inert there (a ~0.02 dB Vgs shift from the
-// removed 4.5 nA foot current, measured in the report-5 rerun).
-function fetLaw(partIds, law) {
+// Structural fields stay at stamp time, never in the entry: a bjt entry's `polarity` and a
+// fet entry's `channel` are inert placeholders (`npn` / `n`) that `device-laws.ts` always
+// overwrites from the device's own `pnp` / `pChannel`. A bjt entry therefore serves NPN and
+// PNP parts alike, and no entry asserts a polarity or channel about anyone's part.
+/** One record's cited value for a schema parameter, or absent when the record omits it. */
+function citedValueOf(record, name) {
+    const param = record.params[name];
+    return param === undefined ? undefined : param.value;
+}
+/** The entry's id list: canonical ids plus typed alias spellings, in listing order. */
+function entryIdsOf(record) {
+    return [...record.partIds, ...(record.aliases ?? [])];
+}
+/** A bjt record's law entry. Throws when the record is not class `bjt` or states nothing. */
+export function bjtLawEntry(record) {
+    if (record.class !== "bjt") {
+        throw new Error(`${record.partIds.join(",")}: a bjt entry needs class "bjt", not "${record.class}"`);
+    }
+    if (Object.keys(record.params).length === 0) {
+        throw new Error(`${record.partIds.join(",")}: a bjt record states no parameters`);
+    }
     return {
-        partIds,
+        partIds: entryIdsOf(record),
         declaredTypes: [],
         terminalRoleGroups: [],
-        model: { kind: "law", law },
+        ...provisionalArmOf(record),
+        model: {
+            kind: "law",
+            law: {
+                kind: "bjt",
+                polarity: "npn",
+                saturationCurrent: citedValueOf(record, "saturationCurrent") ?? 1e-14,
+                forwardBeta: citedValueOf(record, "forwardBeta") ?? 100,
+                reverseBeta: citedValueOf(record, "reverseBeta") ?? 1,
+                thermalVoltage: citedValueOf(record, "thermalVoltage") ?? 0.025_852,
+                leakageAmps: citedValueOf(record, "leakageAmps") ?? 0,
+            },
+        },
+    };
+}
+/**
+ * A signal-diode record's law entry. Requires the forward pair together: the only
+ * derivation the registry admits (two printed (If, Vf) points) yields IS and n as one
+ * working, so a lone IS without n is a broken derivation and throws rather than shipping
+ * half a knee. Gap-filled breakdownVolts 0 keeps the no-knee reading the unregistered path
+ * stamps (a zener knee belongs to class `zener` and the existing `zenerLaw` path, not here).
+ */
+export function diodeLawEntry(record) {
+    if (record.class !== "diode") {
+        throw new Error(`${record.partIds.join(",")}: a diode entry needs class "diode", not "${record.class}"`);
+    }
+    const saturationCurrent = citedValueOf(record, "saturationCurrent");
+    const emissionCoefficient = citedValueOf(record, "emissionCoefficient");
+    if (saturationCurrent === undefined || emissionCoefficient === undefined) {
+        throw new Error(`${record.partIds.join(",")}: a diode record states no forward pair ` +
+            `(saturationCurrent ${saturationCurrent === undefined ? "absent" : "present"}, ` +
+            `emissionCoefficient ${emissionCoefficient === undefined ? "absent" : "present"})`);
+    }
+    return {
+        partIds: entryIdsOf(record),
+        declaredTypes: [],
+        terminalRoleGroups: [],
+        ...provisionalArmOf(record),
+        model: {
+            kind: "law",
+            law: {
+                kind: "diode",
+                saturationCurrent,
+                emissionCoefficient,
+                thermalVoltage: citedValueOf(record, "thermalVoltage") ?? 0.025_852,
+                breakdownVolts: citedValueOf(record, "breakdownVolts") ?? 0,
+                seriesResistance: citedValueOf(record, "seriesResistance") ?? 1.0,
+                isLed: false,
+            },
+        },
+    };
+}
+/**
+ * A JFET- or MOSFET-channel record's law entry. The class selects the gap-fill constants
+ * (JFET depletion defaults with the silicon gate; MOSFET enhancement defaults with the
+ * insulated gate), so a JFET record can never stamp MOSFET gate zeros and the reverse.
+ * Throws on any other class and on an empty record.
+ */
+export function fetLawEntry(record, cls) {
+    if (record.class !== cls) {
+        throw new Error(`${record.partIds.join(",")}: a ${cls} entry needs class "${cls}", not "${record.class}"`);
+    }
+    if (Object.keys(record.params).length === 0) {
+        throw new Error(`${record.partIds.join(",")}: a ${cls} record states no parameters`);
+    }
+    const channelDefaults = cls === "jfet"
+        ? {
+            thresholdVolts: -2,
+            transconductance: 1e-3,
+            channelLengthModulation: 0,
+            subthresholdVolts: 0.07,
+            gateSaturationCurrent: 1e-5,
+            gateOnsetVolts: 0.5,
+            gateScaleVolts: 0.06,
+        }
+        : {
+            thresholdVolts: 2,
+            transconductance: 1e-3,
+            channelLengthModulation: 0,
+            subthresholdVolts: 0,
+            gateSaturationCurrent: 0,
+            gateOnsetVolts: 0,
+            gateScaleVolts: 1,
+        };
+    return {
+        partIds: entryIdsOf(record),
+        declaredTypes: [],
+        terminalRoleGroups: [],
+        ...provisionalArmOf(record),
+        model: {
+            kind: "law",
+            law: {
+                kind: "fet",
+                channel: "n",
+                thresholdVolts: citedValueOf(record, "thresholdVolts") ??
+                    channelDefaults.thresholdVolts,
+                transconductance: citedValueOf(record, "transconductance") ??
+                    channelDefaults.transconductance,
+                channelLengthModulation: citedValueOf(record, "channelLengthModulation") ??
+                    channelDefaults.channelLengthModulation,
+                subthresholdVolts: citedValueOf(record, "subthresholdVolts") ??
+                    channelDefaults.subthresholdVolts,
+                gateSaturationCurrent: citedValueOf(record, "gateSaturationCurrent") ??
+                    channelDefaults.gateSaturationCurrent,
+                gateOnsetVolts: citedValueOf(record, "gateOnsetVolts") ??
+                    channelDefaults.gateOnsetVolts,
+                gateScaleVolts: citedValueOf(record, "gateScaleVolts") ??
+                    channelDefaults.gateScaleVolts,
+            },
+        },
     };
 }
-// --- Zener diodes: reverse breakdown from the device database ------------------------------------
+// --- JFET channel records: built by `fetLawEntry` (wave-1 builders above) -------------------
+//
+// The JFET class default is avowedly no part's values; see `registry-data/jfet.ts` for the
+// measured gate-defect note, the rank argument for keeping the 2SK30A class channel, and the
+// provenance. The generic builder maps each record's present parameters and gap-fills the
+// class channel, so 2SK30A (gate term only) stamps byte-identically to before while full
+// channels (2N5457) stamp their cited values.
+// --- Zener diodes: reverse breakdown from the data registry -------------------------------------
 //
 // `breakdownVolts` only; forward behaviour repeats the class default by construction (see
 // `zenerLaw` above). A device that declares its own breakdown keeps it: `device-laws.ts`
-// overlays the declared value on a catalog match, so the 26 corpus diodes that already
+// overlays the declared value on a catalog match, so the corpus diodes that already
 // declare one (e.g. `boss-ph-1r` D1 11 V against the registry's 10.99) render unchanged.
+// The rows live in `registry-data/zener.ts` as cited values; the entries array below maps
+// them through `zenerLaw`, so the membership set below and the shipped entries cannot
+// drift apart: there is one list, not two.
+/** Read a zener record's cited breakdown, loudly. The loader guarantees the citation. */
+function zenerBreakdownVoltsOf(record) {
+    const breakdown = record.params["breakdownVolts"];
+    if (breakdown === undefined || !Number.isFinite(breakdown.value)) {
+        throw new Error(`${record.partIds.join(",")}: a zener record states no breakdownVolts`);
+    }
+    return breakdown.value;
+}
+export const zenerCatalogPartIds = new Set(zenerRegistryRecords.flatMap((record) => record.partIds.map((id) => foldPartId(id))));
+// --- Fixed-rail regulators: wiring skeletons over registry-data voltages ---------------------------
+// The rail numbers live in `registry-data/regulator.ts` as cited values; this table holds only
+// the terminal wiring (role groups, section terminals) each rail's entry shares. Keyed by the
+// rail volts the record states, so a record always lands on its own wiring and a skeleton row
+// no record consumes throws at load (see the check below). `pinout` is `[null, null, null]`
+// for all of them: no regulator entry asserts a pin order.
+const regulatorTerminalStructures = {
+    // UNRESOLVED: this entry conflates two packages with OPPOSITE pin orders. The TO-92/SOT-89 78L05 is pin1=VOUT, pin2=GND, pin3=VIN (verified: TI LM78L, SNVS754O, Figure 4-2 SOT-89 top view and Figure 4-3 LP 3-pin TO-92 bottom view). The TO-220 7805 is pin1=VIN, pin2=GND, pin3=VOUT. The role groups below assert the 7805 order, because `pin1` sits in the vin group and `pin3` in the vout group.
+    // Consequence: a document that declares a 78L05's terminals as pin1/pin2/pin3 binds its input and output the wrong way round. No corpus packet does today -- all seven three-pin regulators declare typed roles as of 2026-09-05 -- so this is latent, not live. Fixing it means SPLITTING the entry by package before a `pinout` can be written, because one pin map cannot serve both.
+    5: {
+        terminalRoleGroups: [["vin", "in", "input", "pin1"], ["gnd", "pin2"], ["vout", "out", "output", "pin3"]],
+        terminals: [2, 1],
+    },
+    9: {
+        terminalRoleGroups: [["vin", "in", "input", "pin1"], ["gnd", "pin2"], ["vout", "out", "output", "pin3"]],
+        terminals: [2, 1],
+    },
+    // Wave 5: 12 V and 3.3 V 78Lxx rails (LM78L12/LM78L33, TI SNVS754O). Same wiring
+    // shape as the 5 V/9 V entries, and the same latent TO-92-vs-TO-220 pin-order
+    // caveat as the 5 V entry above: no corpus packet names these rails today, so the
+    // order is asserted for parity, not verified against a packet.
+    12: {
+        terminalRoleGroups: [["vin", "in", "input", "pin1"], ["gnd", "pin2"], ["vout", "out", "output", "pin3"]],
+        terminals: [2, 1],
+    },
+    3.3: {
+        terminalRoleGroups: [["vin", "in", "input", "pin1"], ["gnd", "pin2"], ["vout", "out", "output", "pin3"]],
+        terminals: [2, 1],
+    },
+    // electro-harmonix-q-tron's U6 (PartNumber 78L18AC) is the 24V-to-+18V rail; it matches by part id on the first rung, so the role groups below are the standard in/gnd/out family spelling kept for parity with the 5V/9V entries, not a new contract.
+    18: {
+        terminalRoleGroups: [["vin", "in", "input", "pin1"], ["gnd", "ground", "pin2"], ["vout", "out", "output", "pin3"]],
+        terminals: [2, 1],
+    },
+    // `volts` here is SIGNED, which contradicts the convention its consumer documents: `declaredRegulatorTerminals` says "the law carries a magnitude" and reverses the source's sense for an output declared `negative`. Declaring `negative` against a signed -15 therefore double-negates and puts +15V on the rail -- measured 2026-09-05. Until this is settled, a negative regulator using this entry must declare its output `positive`, which is why deluxe-memory-man does.
+    [-15]: {
+        terminalRoleGroups: [["gnd", "pin1"], ["vin", "in", "input", "pin2"], ["vout", "out", "output", "pin3"]],
+        terminals: [2, 0],
+    },
+    // `terminalRoleGroups` is left empty rather than copying the existing regulators' generic `in`/`gnd`/`out` aliases: `VR1` already resolves through the exact part id, and this repo's own corpus shows that generic pinout-signature fallback misidentifying an unrelated part with similarly generic terminal names (`boss-oc-2`'s `BA634-5`, five terminals including `in`/`gnd`/`out`, incidentally satisfies the existing 78L05 groups and is only saved from a wrong law by the later terminal-count guard). No reason to add a second entry to that same weak ladder when the exact part id already does the job.
+    15: {
+        terminalRoleGroups: [],
+        terminals: [2, 1],
+    },
+};
+/** Build one regulator entry from its registry record and the wiring skeleton for its rail. */
+function regulatorEntry(record) {
+    const volts = record.params["volts"];
+    const sourceOhms = record.params["sourceOhms"];
+    if (volts === undefined || sourceOhms === undefined) {
+        throw new Error(`${record.partIds.join(",")}: a regulator record states no volts or sourceOhms`);
+    }
+    const structure = regulatorTerminalStructures[volts.value];
+    if (structure === undefined) {
+        throw new Error(`${record.partIds.join(",")}: no regulator wiring skeleton for ${String(volts.value)} V`);
+    }
+    return {
+        partIds: [...record.partIds],
+        declaredTypes: [],
+        terminalRoleGroups: structure.terminalRoleGroups,
+        ...provisionalArmOf(record),
+        model: {
+            kind: "sections",
+            sections: [
+                {
+                    law: {
+                        kind: "voltage-source",
+                        volts: volts.value,
+                        sourceOhms: sourceOhms.value,
+                    },
+                    terminals: [...structure.terminals],
+                },
+            ],
+            pinout: [null, null, null],
+        },
+    };
+}
+/** The regulator entry for one rail, by the volts its registry record states. Position-preserving. */
+function regulatorEntryForVolts(volts) {
+    const record = regulatorRegistryRecords.find((candidate) => candidate.params["volts"]?.value === volts);
+    if (record === undefined) {
+        throw new Error(`no regulator registry record states ${String(volts)} V`);
+    }
+    return regulatorEntry(record);
+}
+// Every skeleton row is consumed by exactly one record, and every record lands on a row:
+// a rail added to one side without the other throws here rather than silently defaulting.
+for (const key of Object.keys(regulatorTerminalStructures)) {
+    if (!regulatorRegistryRecords.some((record) => record.params["volts"]?.value === Number(key))) {
+        throw new Error(`regulator wiring skeleton for ${key} V is consumed by no registry record`);
+    }
+}
+// --- Charge pumps: wiring skeletons over registry-data loss/slope ---------------------------------
+// The two numbers the derivation reads (`sourceOhms`, `chargePumpLossVolts`) live in
+// `registry-data/charge-pump.ts` as cited values; this table holds only the terminal wiring
+// (role groups, package-order pinout) each pump's entry shares. The 8-pin parts are NOT
+// pin-identical: pin 1 is BOOST (TC1044S, ICL7660S, TC7662B, MAX1044), NC (ICL7660, ICL7660A),
+// FB/SD (LT1054) or SHDN (LTC1144). Keyed by the record's first part id, so a record always
+// lands on its own wiring; a record with no skeleton row, or a skeleton row no record
+// consumes, throws at load (see the check below).
 //
-// Only real manufacturer part numbers appear here: no prose aliases (`3V`, `5V6 zener`,
-// `zener/protection diode`) and no `SOURCE-*-ZENER` placeholder ids. A packet that prints a
-// voltage instead of a part number states no part, so the catalog must not answer it; those
-// values belong in the packet as declared `breakdownVolts`.
-//
-// Each row is `[partIds, breakdownVolts]`; the entries array below maps the table through
-// `zenerLaw`, so the drift script's membership set above and the shipped entries cannot drift
-// apart: there is one list, not two.
-const zenerBreakdownVolts = [
-    [["1N5230"], 4.7],
-    [["1N961B"], 10],
-    [["1N965B"], 15],
-    [["1N969B"], 22],
-    [["1N4744A"], 15],
-    [["1N4751A", "1N4751A 30V", "1N4751A-30V", "1N4751A 30 V"], 30],
-    [["1N4753A"], 36],
-    [["RD5.1EB3", "RD5.1EB 3", "RD5.1EB-3"], 5.235],
-    // Bare RD5.1EB spans every bin but only B3 is in the registry (NEC RD5.1E B3:
-    // Vz 5.12–5.35 V, typ 5.235; vendored at parts/diodes/RD5_1EB3). Stamping B3's
-    // typical for the unbinned part is a derived stand-in, disclosed, not a printed
-    // unbinned value.
-    [["RD5.1EB"], 5.235],
-    // RD3.0EB1/RD3.0EB3 are real part numbers whose registry value lives on the
-    // SOURCE-3V-ZENER row (BV 3); the placeholder id and the prose aliases stay out.
-    [["RD3.0EB3", "RD3.0EB1", "RD3.0EB-1", "RD3.0EB-3"], 3],
-    [["RD4.7EB", "02BZ4.7A", "02BZ4_7A", "02BZ4-7A"], 4.7],
-    [["RD5.6EB3", "RD-5.6EB3", "RD5.6EB 3", "RD5.6EB-3"], 5.76],
-    [["RD5.6EB2", "RD-5.6EB2", "RD5.6EB 2", "RD5.6EB-2", "RD5.6JB2", "RD5.6J B2", "RD5.6J-B2"], 5.58],
-    [["RD6.6EB3", "RD6.6EB 3", "RD6.6EB-3"], 6.62],
-    [["RD8.2EB3", "RD8.2EB 3", "RD8.2EB-3"], 8.18],
-    // MTZ5.6B is the real part behind the SOURCE-5V6-ZENER row (BV 5.6).
-    [["MTZ5.6B"], 5.6],
-    [["RD11EB3", "RD11EB 3", "RD11EB-3", "RD11E B3", "RD11E-B3"], 10.99],
-    // RD11EB is the unbinned part with its own registry row (NEC suffix-B range
-    // 10.18–11.26 V, typ 11): not the B3 typical under a shorter name.
-    [["RD11EB"], 11],
-    [["0Z11A", "05Z11A"], 11],
-    [["1N4733A"], 5.1],
-    [["1N5331"], 5.1],
-    [["1N5239B"], 9.1],
-    [["1N4742A", "1N4742"], 12],
-    [["RD5.6S", "RD5.6S B3", "RD5.6SB3", "RD5.6S-B3"], 5.6],
-    [["RD11FB3", "RD11FB-3"], 11.15],
-    [["PESD12VL1BA"], 12],
-    // The flat `component-zener-diode-chips.json` rows with no diode-file entry.
-    [["1N5231"], 5.1],
-    [["1N5231B"], 5.1],
-    [["1N4733"], 5.1],
-];
-export const zenerCatalogPartIds = new Set(zenerBreakdownVolts.flatMap(([partIds]) => partIds.map(foldPartId)));
+// `volts: 0` in the built law is an unused placeholder: the pump rail is derived per circuit
+// from the input node (see `pumpDerivation` in device-laws.ts), and pump parts bypass generic
+// section expansion, `registrySuppliedVoltages`, and `declaredRegulatorTerminals`, so this
+// number is never stamped.
+const chargePumpTerminalStructures = {
+    // Pinout verified against Microchip DS21348A (2001), p1 pin-configuration diagram and general
+    // description: 1 BOOST, 2 CAP+, 3 GND, 4 CAP-, 5 VOUT, 6 LV, 7 OSC, 8 V+.
+    BOOST_7660: {
+        terminalRoleGroups: [
+            ["boost"],
+            ["capp", "capplus"],
+            ["gnd", "ground"],
+            ["capm", "capminus"],
+            ["vout", "negativeoutput", "voutnegative", "out", "output"],
+            ["lv", "lowvoltage"],
+            ["osc", "oscillator"],
+            ["vplus", "vin", "vdd", "vcc", "input"],
+        ],
+        pinout: ["boost", "capp", "gnd", "capm", "vout", "lv", "osc", "vplus"],
+    },
+    // Pinout verified against Intersil FN3072 Rev 7.00, p1 pinout diagram (8 Ld PDIP/SOIC top view):
+    // 1 NC, 2 CAP+, 3 GND, 4 CAP-, 5 VOUT, 6 LV, 7 OSC, 8 V+.
+    NC_7660: {
+        terminalRoleGroups: [
+            ["nc", "noconnect"],
+            ["capp", "capplus"],
+            ["gnd", "ground"],
+            ["capm", "capminus"],
+            ["vout", "negativeoutput", "voutnegative", "out", "output"],
+            ["lv", "lowvoltage"],
+            ["osc", "oscillator"],
+            ["vplus", "vin", "vdd", "vcc", "input"],
+        ],
+        pinout: ["nc", "capp", "gnd", "capm", "vout", "lv", "osc", "vplus"],
+    },
+    // Pinout verified against TI SLVS033G, p3 pin config + pin-functions table (PDIP-8): 1 FB/SD
+    // (shutdown/error-amp input), 2 CAP+, 3 GND, 4 CAP-, 5 VOUT (output), 6 VREF (2.5 V reference
+    // output), 7 OSC (input), 8 VCC (supply). This is NOT the 7660 pin order: pin 1 is an input and
+    // pin 6 an output, so the part is footprint-compatible but not a drop-in substitute.
+    FBSD_LT1054: {
+        terminalRoleGroups: [
+            ["fbsd", "fb", "sd", "shutdown"],
+            ["capp", "capplus"],
+            ["gnd", "ground"],
+            ["capm", "capminus"],
+            ["vout", "negativeoutput", "voutnegative", "out", "output"],
+            ["vref", "reference"],
+            ["osc", "oscillator"],
+            ["vcc", "vin", "vplus", "vdd", "input"],
+        ],
+        pinout: ["fbsd", "capp", "gnd", "capm", "vout", "vref", "osc", "vcc"],
+    },
+    // Pinout verified against Linear Technology 1144fa, p2 config + p5 Pin Functions: 1 BOOST
+    // (x10 when tied high), 2 CAP+, 3 GND, 4 CAP-, 5 VOUT, 6 SHDN (float/V+ = run, GND = shutdown),
+    // 7 OSC, 8 V+. No LV pin and no low-voltage mode split.
+    SHDN_LTC1144: {
+        terminalRoleGroups: [
+            ["boost"],
+            ["capp", "capplus"],
+            ["gnd", "ground"],
+            ["capm", "capminus"],
+            ["vout", "negativeoutput", "voutnegative", "out", "output"],
+            ["shdn", "shutdown"],
+            ["osc", "oscillator"],
+            ["vplus", "vin", "vdd", "vcc", "input"],
+        ],
+        pinout: ["boost", "capp", "gnd", "capm", "vout", "shdn", "osc", "vplus"],
+    },
+};
+/** Which wiring skeleton each charge-pump record builds on, by the record's first part id. */
+const chargePumpStructureFor = {
+    TC1044S: "BOOST_7660",
+    ICL7660: "NC_7660",
+    ICL7660A: "NC_7660",
+    ICL7660S: "BOOST_7660",
+    TC7662B: "BOOST_7660",
+    LT1054: "FBSD_LT1054",
+    LTC1144: "SHDN_LTC1144",
+    MAX1044: "BOOST_7660",
+};
+/** Build one charge-pump entry from its registry record and its wiring skeleton. */
+function chargePumpEntry(record) {
+    const sourceOhms = record.params["sourceOhms"];
+    const loss = record.params["chargePumpLossVolts"];
+    if (sourceOhms === undefined || loss === undefined) {
+        throw new Error(`${record.partIds.join(",")}: a charge-pump record states no sourceOhms or chargePumpLossVolts`);
+    }
+    const key = record.partIds[0];
+    const skeletonName = key === undefined ? undefined : chargePumpStructureFor[key];
+    const skeleton = skeletonName === undefined ? undefined : chargePumpTerminalStructures[skeletonName];
+    if (skeleton === undefined) {
+        throw new Error(`${record.partIds.join(",")}: no charge-pump wiring skeleton for ${String(key)}`);
+    }
+    return {
+        partIds: [...record.partIds],
+        declaredTypes: [],
+        terminalRoleGroups: skeleton.terminalRoleGroups,
+        ...provisionalArmOf(record),
+        model: {
+            kind: "sections",
+            sections: [
+                {
+                    law: {
+                        kind: "voltage-source",
+                        volts: 0,
+                        sourceOhms: sourceOhms.value,
+                    },
+                    terminals: [4, 2],
+                },
+            ],
+            pinout: skeleton.pinout,
+        },
+        chargePumpLossVolts: loss.value,
+    };
+}
+/** The charge-pump entry for one family, by the record's first part id. Position-preserving. */
+function chargePumpEntryFor(firstPartId) {
+    const record = chargePumpRegistryRecords.find((candidate) => candidate.partIds[0] === firstPartId);
+    if (record === undefined) {
+        throw new Error(`no charge-pump registry record starts with ${firstPartId}`);
+    }
+    return chargePumpEntry(record);
+}
+// Every skeleton row is consumed by exactly one record, and every record lands on a row.
+for (const key of Object.keys(chargePumpStructureFor)) {
+    if (!chargePumpRegistryRecords.some((record) => record.partIds[0] === key)) {
+        throw new Error(`charge-pump wiring skeleton for ${key} is consumed by no registry record`);
+    }
+}
 const entries = [
     // uPC4558, from the artifacts library's own vendored copy:
     // `parts/op-amps/UPC4558/datasheets/renesas-upc258-upc4558.pdf` (Renesas `UPC258, UPC4558`,
@@ -287,12 +627,20 @@ const entries = [
     // 100 dB is 10^(100/20) = 100,000, which is what the part record's "100 k" states in the other
     // unit. `boss-ce-2b` says `NJM4558DD`; the datasheet's own numbers differ from it only in
     // package/rank suffix and are listed alongside.
+    // `JRC4558D` is the one knowingly non-printed id here: the Nisshinbo sheet prints NJM4558D,
+    // not JRC4558D, and the identification of JRC4558D as the NJR/JRC marking of the NJM4558D
+    // rests on `parts/op-amps/JRC4558D.md` ("NJR/JRC version. Same datasheet specs as NJM4558"),
+    // not on this sheet. It is carried anyway per owner decision 2026-10-15, because a real
+    // Boss SD-1 specimen carries a chip marked "JRC 4558D" and three corpus packets name it.
     // **Pin labels corrected and role groups added 2026-09-02 (W2).** The pinout read `OUT_B, IN_B_MINUS, IN_B_PLUS, VEE, IN_A_PLUS, IN_A_MINUS, OUT_A, VCC` -- the datasheet's A and B swapped. Electrically it made no difference, because both sections are the same `ideal-opamp` law and each section's triple was internally consistent, so this is a documentation correction: the positions are physical DIP-8 pins either way and the `sections` indices are unchanged.
     // The role groups carry **only** the pin-numbered spellings, deliberately. Generic aliases (`noninverting`, `out`) would let one declared role satisfy two different groups -- A's and B's -- and `matchesTerminalRoles` would then identify any 5-terminal section as this whole package. Pin-numbered tokens are unambiguous per position. `boss-dm-3`'s `IC1` is the only corpus device declaring a 4558 as an 8-pin package rather than as sections.
     {
         "partIds": [
             "NJM4558DD",
             "NJM4558D",
+            "JRC4558D",
+            "JRC4558",
+            "JRC4558DD",
             "NJM4558M",
             "NJM4558E",
             "NJM4558V",
@@ -381,18 +729,12 @@ const entries = [
     //
     //   VOM  Maximum peak output voltage swing  RL = 10 kOhm, TA = 25 C, VCC+- = +-15 V
     //        Min +-10 V   Typ +-13.5 V   (table 6.7)
-    //   Figure 6-1, VOM vs |VCC+-| (RL = 10 kOhm), is roughly linear: VOM is about 3.3 V at
-    //   |VCC+-| = 4.5 V, the +-4.5 V a 9 V single supply gives.
-    //
-    // `outputSwingDropVolts` is 1.2 V: the distance the output stops short of each rail at that
-    // 9 V operating point (4.5 - 3.3). **That figure is read by eye from the plotted line, not
-    // printed.** The printed figure is the 1.5 V (15 - 13.5) of table 6.7, at +-15 V. 1.2 was
-    // chosen because the pedals fitted with this part run on 9 V, and it is disclosed here rather
-    // than presented as a datasheet number. Open-loop gain stays the house 100000 the family
-    // entry it was split from carried; it is not a sourced TL06x figure.
     //
-    // The drop also reaches a *declared* `opamp` device (the ElectroSmash script-logo Phase 90's
-    // TL061s) through `registryOpampSwingDrop`, which reads the first section's law.
+    // Open-loop gain stays the house 100000 the family entry it was split from carried; it is not a
+    // sourced TL06x figure. The output swing is not in this entry: it has its own table,
+    // `registry-data/opamp.ts`, which stamps the printed pair (1.5 V a side, `constant`) onto these
+    // ids, for a declared `opamp` device and a package alike. The graph-read 1.2 V this entry carried
+    // until row 16 (Figure 6-1 at +-4.5 V) was not a printed figure and is gone.
     {
         "partIds": [
             "TL062",
@@ -420,8 +762,7 @@ const entries = [
                         "kind": "ideal-opamp",
                         "railHigh": null,
                         "railLow": null,
-                        "openLoopGain": 100000,
-                        "outputSwingDropVolts": 1.2
+                        "openLoopGain": 100000
                     },
                     "terminals": [
                         2,
@@ -434,8 +775,7 @@ const entries = [
                         "kind": "ideal-opamp",
                         "railHigh": null,
                         "railLow": null,
-                        "openLoopGain": 100000,
-                        "outputSwingDropVolts": 1.2
+                        "openLoopGain": 100000
                     },
                     "terminals": [
                         4,
@@ -478,8 +818,7 @@ const entries = [
                         "kind": "ideal-opamp",
                         "railHigh": null,
                         "railLow": null,
-                        "openLoopGain": 100000,
-                        "outputSwingDropVolts": 1.2
+                        "openLoopGain": 100000
                     },
                     "terminals": [
                         0,
@@ -3068,18 +3407,10 @@ const entries = [
     },
     // Texas Instruments OP07x, from "OP07x Precision Operational Amplifiers" SLOS099H (rev. March
     // 2023), `parts/op-amps/OP07/datasheets/op07-ti.pdf` in vessel-dsp/artifacts, section 6.5.
-    //
-    //   VOM  Output voltage swing, VS = +-15 V   RL = 10 kOhm: min +-12   typ +-13
-    //                                            RL = 2 kOhm:  min +-11.5 typ +-12.8
-    //
-    // `outputSwingDropVolts` is 2.2 V: 15 - 12.8, the table's own default condition (RL = 2 kOhm,
-    // typ). **That is a +-15 V figure carried to a 9 V single supply on the assumption that a
-    // bipolar output stage's headroom is constant, not proportional to the supply.** The datasheet
-    // states nothing at 9 V, and the proportional reading would give 0.66 V. The measured pin 6
-    // swing on a specimen has not been taken: the RAT specimen study
-    // (`packet-study/pro-co-rat-2-v4b-op07cp`) scored this law UNDECIDED, its band exceeding 20 dB,
-    // and it is shipped on the datasheet alone, as a typical and never a measured part. The datasheet
-    // bracket across load current is 2.0 (typ, 10 kOhm) to 3.5 (min spec, 2 kOhm).
+    // Open-loop gain stays the house 100000. The output swing is not in this entry: it has its own
+    // registry-data record (`registry-data/opamp.ts`), which types the printed +-12.8 V (RL = 2 kOhm, VS = +-15 V)
+    // as a `proportional` pair for OP07CP, OP07DP and OP07DN, and lists the bare `OP07` id absent (the
+    // sheet's characteristics apply to the C and D grades only).
     {
         "partIds": [
             "OP07",
@@ -3113,8 +3444,7 @@ const entries = [
                         "kind": "ideal-opamp",
                         "railHigh": null,
                         "railLow": null,
-                        "openLoopGain": 100000,
-                        "outputSwingDropVolts": 2.2
+                        "openLoopGain": 100000
                     },
                     "terminals": [
                         0,
@@ -3131,6 +3461,11 @@ const entries = [
         }
     },
     // --- Single Op-Amps (LM741, TL071, NJM5534D) --------------------------------------------------------------------------
+    // Wave 5: LM741CN rides this entry. It is the exact PDIP orderable spelling printed
+    // in the TI LM741 SNOSC25D (May 1998, rev Oct 2015) Package Option Addendum:
+    // 'LM741CN/NOPB | Active | Production | PDIP (P) | 8', part marking 'LM 741CN'.
+    // The specs sit under the LM741C column family; open-loop gain stays the house
+    // 100000 and no GBW row is quoted (see opampGainBandwidthAbsent).
     {
         "partIds": [
             "LM741",
@@ -3142,7 +3477,9 @@ const entries = [
             "NJM5534",
             "NJM5534D",
             "NE5534",
-            "NJM5534M"
+            "NJM5534M",
+            "JRC5534",
+            "LM741CN"
         ],
         "declaredTypes": [],
         "terminalRoleGroups": [
@@ -3220,170 +3557,16 @@ const entries = [
             ]
         }
     },
-    // --- 5V Voltage Regulators (78L05, uPC78L05, 78M05, TA78L05F) - Causal input-dependent physical modeling! ------------------
-    // UNRESOLVED: this entry conflates two packages with OPPOSITE pin orders. The TO-92/SOT-89 78L05 is pin1=VOUT, pin2=GND, pin3=VIN (verified: TI LM78L, SNVS754O, Figure 4-2 SOT-89 top view and Figure 4-3 LP 3-pin TO-92 bottom view). The TO-220 7805 is pin1=VIN, pin2=GND, pin3=VOUT. The role groups below assert the 7805 order, because `pin1` sits in the vin group and `pin3` in the vout group.
-    // Consequence: a document that declares a 78L05's terminals as pin1/pin2/pin3 binds its input and output the wrong way round. No corpus packet does today -- all seven three-pin regulators declare typed roles as of 2026-09-05 -- so this is latent, not live. Fixing it means SPLITTING the entry by package before a `pinout` can be written, because one pin map cannot serve both.
-    {
-        "partIds": [
-            "uPC78L05",
-            "78L05",
-            "7805",
-            "78M05",
-            "TA78L05F",
-            // Toshiba's TA78L05S (product page detail.TA78L05S): the same 5 V TA78L die in TO-92.
-            // Without it, `boss-dd-5`'s IC5 fell to the pin-name rung and matched the 78L18 entry,
-            // solving the pedal's 5 V rail at 18 V.
-            "TA78L05S",
-            "2930L05",
-            "BA78L05",
-            "uPC78L05T"
-        ],
-        "declaredTypes": [],
-        "terminalRoleGroups": [
-            [
-                "vin",
-                "in",
-                "input",
-                "pin1"
-            ],
-            [
-                "gnd",
-                "pin2"
-            ],
-            [
-                "vout",
-                "out",
-                "output",
-                "pin3"
-            ]
-        ],
-        "model": {
-            "kind": "sections",
-            "sections": [
-                {
-                    "law": {
-                        "kind": "voltage-source",
-                        "volts": 5,
-                        "sourceOhms": 1
-                    },
-                    "terminals": [
-                        2,
-                        1
-                    ]
-                }
-            ],
-            "pinout": [
-                null,
-                null,
-                null
-            ]
-        }
-    },
-    // --- 9V Voltage Regulators (7809, 78L09, 78M09, uPC78L09) - Causal input-dependent physical modeling! ------------------
-    {
-        "partIds": [
-            "uPC78L09",
-            "78L09",
-            "7809",
-            "78M09",
-            "TA78L09F",
-            "2930L09",
-            "BA78L09",
-            "uPC78L09T"
-        ],
-        "declaredTypes": [],
-        "terminalRoleGroups": [
-            [
-                "vin",
-                "in",
-                "input",
-                "pin1"
-            ],
-            [
-                "gnd",
-                "pin2"
-            ],
-            [
-                "vout",
-                "out",
-                "output",
-                "pin3"
-            ]
-        ],
-        "model": {
-            "kind": "sections",
-            "sections": [
-                {
-                    "law": {
-                        "kind": "voltage-source",
-                        "volts": 9,
-                        "sourceOhms": 1
-                    },
-                    "terminals": [
-                        2,
-                        1
-                    ]
-                }
-            ],
-            "pinout": [
-                null,
-                null,
-                null
-            ]
-        }
-    },
-    // --- 18V Voltage Regulators (78L18, 78L18AC, 78L18T) - same 3-pin voltage-source shape as 5V/9V above ----------------------
-    // electro-harmonix-q-tron's U6 (PartNumber 78L18AC) is the 24V-to-+18V rail; it matches by part id on the first rung, so the
-    // role groups below are the standard in/gnd/out family spelling kept for parity with the 5V/9V entries, not a new contract.
-    {
-        "partIds": [
-            "78L18",
-            "78L18AC",
-            "78L18T",
-            "7818"
-        ],
-        "declaredTypes": [],
-        "terminalRoleGroups": [
-            [
-                "vin",
-                "in",
-                "input",
-                "pin1"
-            ],
-            [
-                "gnd",
-                "ground",
-                "pin2"
-            ],
-            [
-                "vout",
-                "out",
-                "output",
-                "pin3"
-            ]
-        ],
-        "model": {
-            "kind": "sections",
-            "sections": [
-                {
-                    "law": {
-                        "kind": "voltage-source",
-                        "volts": 18,
-                        "sourceOhms": 1
-                    },
-                    "terminals": [
-                        2,
-                        1
-                    ]
-                }
-            ],
-            "pinout": [
-                null,
-                null,
-                null
-            ]
-        }
-    },
+    // --- 5V Voltage Regulators: ids and rail from registry-data/regulator.ts; wiring above --------
+    regulatorEntryForVolts(5),
+    // --- 9V Voltage Regulators: ids and rail from registry-data/regulator.ts; wiring above --------
+    regulatorEntryForVolts(9),
+    // --- 12V Voltage Regulators (wave 5: LM78L12): ids and rail from registry-data/regulator.ts; wiring above --------
+    regulatorEntryForVolts(12),
+    // --- 3.3V Voltage Regulators (wave 5: LM78L33): ids and rail from registry-data/regulator.ts; wiring above --------
+    regulatorEntryForVolts(3.3),
+    // --- 18V Voltage Regulators: ids and rail from registry-data/regulator.ts; wiring above --------
+    regulatorEntryForVolts(18),
     // --- Active Physical Analog Comparators (LM311, NJM311M, LM319, NJM319M) ----------------------------------------------------
     // --- Active Physical Analog Comparators (LM311, NJM311M, LM319, NJM319M, LM393, LM339) ------------------------------------
     {
@@ -5193,80 +5376,50 @@ const entries = [
             ]
         }
     },
-    // --- Negative Voltage Regulators (LM7915, LM7912) - Causal input-dependent physical modeling! --------------------------------
-    // UNRESOLVED, two separate problems. (1) `7912`/`LM7912` are -12V parts sharing an entry hardcoded to volts: -15, so a 7912 would be modelled 3V low. Only one corpus device uses this entry (deluxe-memory-man's U12_LM7915), so the defect is latent.
-    // (2) `volts` here is SIGNED, which contradicts the convention its consumer documents: `declaredRegulatorTerminals` says "the law carries a magnitude" and reverses the source's sense for an output declared `negative`. Declaring `negative` against a signed -15 therefore double-negates and puts +15V on the rail -- measured 2026-09-05. Until this is settled, a negative regulator using this entry must declare its output `positive`, which is why deluxe-memory-man does.
+    // --- Negative Voltage Regulators: ids and rail from registry-data/regulator.ts; wiring above --------
+    // The 7912/LM7912 sharing and the signed-volts convention are recorded on the record; the
+    // wiring skeleton for -15 V is shared. Until the convention is settled, a negative regulator
+    // using this entry must declare its output `positive`, which is why deluxe-memory-man does.
+    regulatorEntryForVolts(-15),
+    // --- TC1044S charge-pump inverter (Microchip): ids and loss/slope from registry-data/charge-pump.ts; wiring above ---
+    chargePumpEntryFor("TC1044S"),
+    // --- ICL7660 charge-pump inverter (Intersil/Renesas): ids and loss/slope from registry-data/charge-pump.ts; wiring above ---
+    chargePumpEntryFor("ICL7660"),
+    // --- ICL7660A charge-pump inverter (Intersil/Renesas): ids and loss/slope from registry-data/charge-pump.ts; wiring above ---
+    chargePumpEntryFor("ICL7660A"),
+    // --- ICL7660S charge-pump inverter (Renesas): ids and loss/slope from registry-data/charge-pump.ts; wiring above ---
+    chargePumpEntryFor("ICL7660S"),
+    // --- TC7662B charge-pump inverter (Microchip): ids and loss/slope from registry-data/charge-pump.ts; wiring above ---
+    chargePumpEntryFor("TC7662B"),
+    // --- LT1054 switched-capacitor converter (TI second source): ids and loss/slope from registry-data/charge-pump.ts; wiring above ---
+    chargePumpEntryFor("LT1054"),
+    // --- LTC1144 wide-input converter (Linear Tech): ids and loss/slope from registry-data/charge-pump.ts; wiring above ---
+    chargePumpEntryFor("LTC1144"),
+    // --- MAX1044 switched-capacitor converter (Maxim): ids and loss/slope from registry-data/charge-pump.ts; wiring above ---
+    chargePumpEntryFor("MAX1044"),
+    // --- AK4552VT8 8-pin codec body alternative ----------------------------------------------------------------------------------
     {
         "partIds": [
-            "LM7915",
-            "7915",
-            "7912",
-            "LM7912"
+            "AK4552VT8",
+            "AK4552VT",
+            "AK4552"
         ],
         "declaredTypes": [],
-        "terminalRoleGroups": [
-            [
-                "gnd",
-                "pin1"
-            ],
-            [
-                "vin",
-                "in",
-                "input",
-                "pin2"
-            ],
-            [
-                "vout",
-                "out",
-                "output",
-                "pin3"
-            ]
-        ],
+        "terminalRoleGroups": [],
         "model": {
             "kind": "sections",
             "sections": [
                 {
                     "law": {
-                        "kind": "voltage-source",
-                        "volts": -15,
-                        "sourceOhms": 1
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 10
                     },
                     "terminals": [
+                        0,
                         2,
-                        0
-                    ]
-                }
-            ],
-            "pinout": [
-                null,
-                null,
-                null
-            ]
-        }
-    },
-    // --- AK4552VT8 8-pin codec body alternative ----------------------------------------------------------------------------------
-    {
-        "partIds": [
-            "AK4552VT8",
-            "AK4552VT",
-            "AK4552"
-        ],
-        "declaredTypes": [],
-        "terminalRoleGroups": [],
-        "model": {
-            "kind": "sections",
-            "sections": [
-                {
-                    "law": {
-                        "kind": "ideal-opamp",
-                        "railHigh": null,
-                        "railLow": null,
-                        "openLoopGain": 10
-                    },
-                    "terminals": [
-                        0,
-                        2,
-                        2
+                        2
                     ]
                 },
                 {
@@ -5354,10 +5507,11 @@ const entries = [
     // output=pinout[0] -- the `ideal-opamp` law reads only those three; vplus/vminus are not
     // wired to the law (rails come from the circuit, exactly as the CD4049 template above).
     // No MC33178 datasheet is vendored in the artifacts library, so the open-loop gain is the
-    // class-general 100 dB (1e4) rather than a sourced MC33178 figure. `outputSwingDropVolts` 1.1 is
-    // the registry's (`component-opamp-chips.json`) figure, 15 V - 13.9 V from the onsemi MC33178-D
-    // output swing table at +-15 V, RL = 2 kOhm; that datasheet is likewise not vendored here, so the
-    // figure is carried from the registry's citation and not re-read.
+    // class-general 100 dB (1e4) rather than a sourced MC33178 figure. It states **no output swing**:
+    // the 1.1 V this entry carried until row 16 was the registry's (`component-opamp-chips.json`)
+    // citation of the onsemi MC33178-D table at +-15 V, never re-read here because the datasheet is not
+    // vendored, which does not meet the printed-TYP-only rule; the id is listed in
+    // `opampOutputSwingAbsent` with that reason.
     {
         "partIds": [
             "MC33178",
@@ -5374,8 +5528,7 @@ const entries = [
                         "kind": "ideal-opamp",
                         "railHigh": null,
                         "railLow": null,
-                        "openLoopGain": 100000,
-                        "outputSwingDropVolts": 1.1
+                        "openLoopGain": 100000
                     },
                     "terminals": [
                         2,
@@ -5707,52 +5860,14 @@ const entries = [
             ]
         }
     },
-    // --- LM340T-15 +15V linear regulator (mxr-m117r-flanger) --------------------------------------------------------------------
-    //
-    // Not a CMOS/analog-switch part either, but the sole remaining blocker on `mxr-m117r-flanger`
-    // after the `CD4013AE` fix above: its `VR1` names PartNumber `LM340T-15`, an unregistered fixed
-    // +15V linear regulator. Same shape and same `voltage-source` law as the existing 78L05/78L09
-    // entries above (input/ground/output, output held at the regulator's fixed rail relative to
-    // ground) -- only the voltage differs, read directly off the part number and the component's own
-    // `Description: "15 V regulator from the selected factory schematic."` `VR1` declares exactly
-    // three terminals, `input, ground, output`, in that order, matching the existing regulator
-    // entries' `terminals: [2, 1]` (output relative to ground) convention directly.
-    //
-    // `terminalRoleGroups` is left empty rather than copying the existing regulator entries'
-    // generic `in`/`gnd`/`out` aliases: `VR1` already resolves through the exact-partId rung, and
-    // this repo's own corpus shows that generic pinout-signature fallback misidentifying an unrelated
-    // part with similarly-generic terminal names (`boss-oc-2`'s `BA634-5`, five terminals including
-    // `in`/`gnd`/`out`, incidentally satisfies the existing 78L05 entry's groups and is only saved
-    // from a wrong law by the later terminal-count guard). No reason to add a second entry to that
-    // same weak ladder when the exact part id already does the job.
-    {
-        "partIds": [
-            "LM340T-15"
-        ],
-        "declaredTypes": [],
-        "terminalRoleGroups": [],
-        "model": {
-            "kind": "sections",
-            "sections": [
-                {
-                    "law": {
-                        "kind": "voltage-source",
-                        "volts": 15,
-                        "sourceOhms": 1
-                    },
-                    "terminals": [
-                        2,
-                        1
-                    ]
-                }
-            ],
-            "pinout": [
-                null,
-                null,
-                null
-            ]
-        }
-    },
+    // --- LM340T-15 +15V linear regulator (mxr-m117r-flanger): ids and rail from registry-data/regulator.ts; wiring above ----
+    // The sole remaining blocker on `mxr-m117r-flanger` after the `CD4013AE` fix above: its `VR1`
+    // names PartNumber `LM340T-15`, an unregistered fixed +15V linear regulator. Same shape and same
+    // `voltage-source` law as the 78L05/78L09 entries (input/ground/output, output held at the
+    // regulator's fixed rail relative to ground) -- `VR1` declares exactly three terminals,
+    // `input, ground, output`, in that order, matching the regulator entries' `terminals: [2, 1]`
+    // (output relative to ground) convention directly.
+    regulatorEntryForVolts(15),
     // --- Tube rectifiers ------------------------------------------------------------------
     //
     // A vacuum rectifier drops tens of volts where a silicon diode drops less than one, and that
@@ -6680,33 +6795,2019 @@ const entries = [
             ]
         }
     },
-    ...zenerBreakdownVolts.map(([partIds, breakdownVolts]) => zenerLaw(partIds, breakdownVolts)),
-    // 2SK30A series/shunt switches (`ibanez-ts9` Q102/Q104, the only packet with
-    // specimen evidence; `boss-sg-1-slow-gear` declares the same id and its gate is
-    // inert there). Channel repeats the class default by construction (see above);
-    // only `gateSaturationCurrent` carries part data.
-    fetLaw(["2SK30A"], {
-        kind: "fet",
-        channel: "n",
-        thresholdVolts: -2,
-        transconductance: 1e-3,
-        channelLengthModulation: 0,
-        subthresholdVolts: 0.07,
-        gateSaturationCurrent: 1e-14,
-        gateOnsetVolts: 0.5,
-        gateScaleVolts: 0.06,
-    }),
-];
-/**
- * Every part id whose `fet` entry refines the gate term only, folded for comparison.
- * `report-part-store-drift.ts` keys its channel-field exclusion on this set -- a catalog
- * product -- rather than on the registry row, so a gate-only entry's avowed class channel
- * is never graded against the database's beta/lambda/Vp the way a transcribed channel
- * would be. Mirrors `zenerCatalogPartIds` above.
- */
-export const gateOnlyFetPartIds = new Set(["2sk30a"]);
-/**
- * The catalog the corpus-facing scripts inject.
- */
-export const pedalPartCatalog = { entries };
+    // Wave-1 op-amp entries: sections whose gain-bandwidth product the data registry
+    // stamps (see `registry-data/opamp.ts` and `withDatasheetGainBandwidth` below). The
+    // open-loop gain is the sheet's own TYP AOL transcribed; the swing pair is deliberately
+    // absent (owner D4 freeze, upheld for this wave).
+    // TI LM833 dual audio op-amp, from `parts/op-amps/LM833/datasheets/lm833-ti.pdf` (TI
+    // SLOS481B, rev Oct 2014). Pin diagram and Pin Functions table, 6 p3 (D/SOIC, DGK/MSOP
+    // and P/PDIP packages, TOP VIEW): 1 OUT1, 2 IN1-, 3 IN1+, 4 VCC-, 5 IN2+, 6 IN2-,
+    // 7 OUT2, 8 VCC+ -- the standard dual order, read off the sheet's own table, with the
+    // same pin-numbered role convention as the 4558 entry above (pin-numbered tokens only;
+    // no generic alias may satisfy two sections at once).
+    //
+    // Electrical characteristics 7.5/7.6 p5 at VCC+- = +-15 V, TA = 25 C:
+    //   Large-signal differential voltage amplification AVD, RL >= 2 kOhm, VO = +-10 V:
+    //   MIN 90 TYP 110 dB. Used as `openLoopGain: decibelGain(110)`, the typ figure.
+    // GBW is not in this entry: it lives in the data-registry row (TYP 16 MHz at f = 100 kHz),
+    // stamped by the pass below. Wave 4: LM833N rides this entry for open-loop gain
+    // (TI LM833-N sheet SNOSBD8E prints LM833N/NOPB as the PDIP orderable of the same
+    // die with the same AV 110 dB TYP) but carries its own GBW row: the LM833-N sheet
+    // prints GBW TYP 15 MHz, not the LM833 sheet's 16, so the pass splits the entry.
+    {
+        "partIds": [
+            "LM833",
+            "LM833N"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "OUT_A_pin1"
+            ],
+            [
+                "INVERTING_A_pin2"
+            ],
+            [
+                "NONINVERTING_A_pin3"
+            ],
+            [
+                "V_MINUS_pin4"
+            ],
+            [
+                "NONINVERTING_B_pin5"
+            ],
+            [
+                "INVERTING_B_pin6"
+            ],
+            [
+                "OUT_B_pin7"
+            ],
+            [
+                "V_PLUS_pin8"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "pinout": [
+                "OUT_A",
+                "IN_A_MINUS",
+                "IN_A_PLUS",
+                "VEE",
+                "IN_B_PLUS",
+                "IN_B_MINUS",
+                "OUT_B",
+                "VCC"
+            ],
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 316227.7660168379
+                    },
+                    "terminals": [
+                        2,
+                        1,
+                        0
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 316227.7660168379
+                    },
+                    "terminals": [
+                        4,
+                        5,
+                        6
+                    ]
+                }
+            ]
+        }
+    },
+    // Wave-3 op-amp entries: sections whose open-loop gain is the sheet's own TYP AOL
+    // transcribed (the gain-bandwidth product lives in `registry-data/opamp.ts`, stamped by
+    // the passes below; the swing pair stays absent per the D4 freeze). GBW rows and catalog
+    // entries are 1:1 by part id, so no entry splits. LM1458/N carry AOL only (no GBW row
+    // exists; see `opampGainBandwidthAbsent`).
+    // NJR NJM4580 dual audio op-amp, from `parts/op-amps/JRC4580/datasheets/njm4580d-njr.pdf`
+    // (NJR Ver. 2012-09-14). PIN FUNCTION table, p1 (DIP-8 TOP VIEW): 1 A OUTPUT, 2 A -INPUT,
+    // 3 A +INPUT, 4 V-, 5 B +INPUT, 6 B -INPUT, 7 B OUTPUT, 8 V+ -- the standard dual order,
+    // with the same pin-numbered role convention as the LM833 entry above (pin-numbered
+    // tokens only; no generic alias may satisfy two sections at once).
+    //
+    // Electrical characteristics p2 at V+/V- = +-15 V, Ta = 25 C:
+    //   Voltage Gain AV, RL >= 2 kOhm, VO = +-10 V: MIN 90 TYP 110 dB.
+    // Used as `openLoopGain: decibelGain(110)`, the typ figure (the D rank changes the noise
+    // row only). The JRC ids rest on `parts/op-amps/JRC4580.md` ('JRC4580D / NJM4580D',
+    // primary local datasheet this sheet) -- the JRC4558D precedent (owner decision
+    // 2026-10-15: the NJR/JRC marking rides the NJM sheet). GBW is not in this entry: it
+    // lives in the data-registry row (TYP 15 MHz at f = 10 kHz), stamped by the pass below.
+    {
+        "partIds": [
+            "JRC4580D",
+            "JRC4580",
+            "NJM4580D",
+            "NJM4580"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "OUT_A_pin1"
+            ],
+            [
+                "INVERTING_A_pin2"
+            ],
+            [
+                "NONINVERTING_A_pin3"
+            ],
+            [
+                "V_MINUS_pin4"
+            ],
+            [
+                "NONINVERTING_B_pin5"
+            ],
+            [
+                "INVERTING_B_pin6"
+            ],
+            [
+                "OUT_B_pin7"
+            ],
+            [
+                "V_PLUS_pin8"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "pinout": [
+                "OUT_A",
+                "IN_A_MINUS",
+                "IN_A_PLUS",
+                "VEE",
+                "IN_B_PLUS",
+                "IN_B_MINUS",
+                "OUT_B",
+                "VCC"
+            ],
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 316227.7660168379
+                    },
+                    "terminals": [
+                        2,
+                        1,
+                        0
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 316227.7660168379
+                    },
+                    "terminals": [
+                        4,
+                        5,
+                        6
+                    ]
+                }
+            ]
+        }
+    },
+    // TI OPA2134 dual audio op-amp, from `parts/op-amps/OPA2134/datasheets/opa2134-ti.pdf`
+    // (TI SBOS058B, Dec 1997, Rev. B Nov 2024). Table 4-1 Pin Functions: OPA2134, p3 (D/SOIC
+    // and P/PDIP 8-pin, top view Fig. 4-2): OUT A-1, -IN A-2, +IN A-3, V--4, +IN B-5, -IN B-6,
+    // OUT B-7, V+-8 -- the standard dual order, same pin-numbered role convention.
+    // OPA2134PA is a printed PDIP-8 orderable of the same die (orderable table, marking
+    // OPA2134PA); the specs below are family-wide with no per-orderable split.
+    //
+    // Electrical characteristics 5.7 p7 at TA = 25 C, VS = +-15 V:
+    //   AOL Open-loop voltage gain, RL = 2 kOhm, -13.8 V <= VO <= 13.5 V:
+    //   MIN 104 TYP 120 dB (a second row at RL = 10 kOhm reads the same 104/120).
+    // Used as `openLoopGain: decibelGain(120)`, the typ figure. GBW is not in this entry:
+    // it lives in the data-registry row (TYP 8 MHz), stamped by the pass below.
+    {
+        "partIds": [
+            "OPA2134",
+            "OPA2134PA"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "OUT_A_pin1"
+            ],
+            [
+                "INVERTING_A_pin2"
+            ],
+            [
+                "NONINVERTING_A_pin3"
+            ],
+            [
+                "V_MINUS_pin4"
+            ],
+            [
+                "NONINVERTING_B_pin5"
+            ],
+            [
+                "INVERTING_B_pin6"
+            ],
+            [
+                "OUT_B_pin7"
+            ],
+            [
+                "V_PLUS_pin8"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "pinout": [
+                "OUT_A",
+                "IN_A_MINUS",
+                "IN_A_PLUS",
+                "VEE",
+                "IN_B_PLUS",
+                "IN_B_MINUS",
+                "OUT_B",
+                "VCC"
+            ],
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 1000000
+                    },
+                    "terminals": [
+                        2,
+                        1,
+                        0
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 1000000
+                    },
+                    "terminals": [
+                        4,
+                        5,
+                        6
+                    ]
+                }
+            ]
+        }
+    },
+    // TI LM1458 dual op-amp, from `parts/op-amps/LM1458/datasheets/lm1458.pdf` (TI SNOSBU4D,
+    // Apr 1998, Rev. D Mar 2013, ex-National; NOT the ST sheet `MC1458.md` points at).
+    // Connection Diagram Fig. 2 Dual-In-Line Package (Top View), p1: 1 OUTPUT A,
+    // 2 INVERTING INPUT A, 3 NON-INVERTING INPUT A, 4 V-, 5 NON-INVERTING INPUT B,
+    // 6 INVERTING INPUT B, 7 OUTPUT B, 8 V+ -- the standard dual order, same pin-numbered
+    // role convention. LM1458N is printed (Abs Max 'LM1458N 400 mW' p2; orderables
+    // LM1458N/NOPB p5, PDIP-8); the AC specs sit under the generic LM1458 column, which
+    // covers it (the CA1458 entry above is the neighbouring point not jumped to: Harris
+    // 200,000 vs TI 160,000 for the same row, so this comes from the document that names
+    // LM1458).
+    //
+    // Electrical characteristics p2 at TA = 25 C, VS = +-15 V, VOUT = +-10 V, RL >= 2 kOhm:
+    //   Large Signal Voltage Gain: LM1458 MIN 20 TYP 160 V/mV (LM1558 50/160 is the sibling
+    //   column). Used as `openLoopGain: 160000`, the typ figure. The sheet prints no GBW row
+    //   at all (see `opampGainBandwidthAbsent`); the swing pair stays absent per the D4 freeze
+    //   (see `opampOutputSwingAbsent`).
+    {
+        "partIds": [
+            "LM1458",
+            "LM1458N"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "OUT_A_pin1"
+            ],
+            [
+                "INVERTING_A_pin2"
+            ],
+            [
+                "NONINVERTING_A_pin3"
+            ],
+            [
+                "V_MINUS_pin4"
+            ],
+            [
+                "NONINVERTING_B_pin5"
+            ],
+            [
+                "INVERTING_B_pin6"
+            ],
+            [
+                "OUT_B_pin7"
+            ],
+            [
+                "V_PLUS_pin8"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "pinout": [
+                "OUT_A",
+                "IN_A_MINUS",
+                "IN_A_PLUS",
+                "VEE",
+                "IN_B_PLUS",
+                "IN_B_MINUS",
+                "OUT_B",
+                "VCC"
+            ],
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 160000
+                    },
+                    "terminals": [
+                        2,
+                        1,
+                        0
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 160000
+                    },
+                    "terminals": [
+                        4,
+                        5,
+                        6
+                    ]
+                }
+            ]
+        }
+    },
+    // Wave-4 op-amp entries: sections whose open-loop gain is the sheet's own TYP AOL
+    // transcribed (the gain-bandwidth product lives in `registry-data/opamp.ts`, stamped by
+    // the passes below; the swing pair stays absent per the D4 freeze). GBW rows and catalog
+    // entries are 1:1 by part id, so no entry splits. LM308 and UA741CP carry AOL only (no
+    // GBW row exists; see `opampGainBandwidthAbsent`).
+    // TI LM108/LM208/LM308 single precision op-amp, from SNOSBS5A (May 2004, rev Sept
+    // 2011, OBSOLETE): 5.x Electrical Characteristics (TA = 25C, VS = +-15 V, VOUT = +-10 V,
+    // RL >= 10 kOhm): 'Large Signal Voltage Gain | MIN 50 (LM108/208) / 25 (LM308) |
+    // TYP 300 | V/mV'. Used as `openLoopGain: 300000`. No GBW row is transcribed (the
+    // sheet prints compensation values and open-loop response graphs only; the Fig. 6
+    // 250 kHz/3.5 MHz numbers belong to the LM101A-boosted application circuit).
+    // Pinout: Figure 8 Dual-In-Line Package Top View (8-Pin) p11 (1 COMP, 2 INPUT-,
+    // 3 INPUT+, 4 V-, 5 NC, 6 OUTPUT, 7 V+, 8 COMP 2); the entry keeps the LF351
+    // three-terminal capture (IN+ pin3, IN- pin2, OUT pin6), which is the same
+    // LM741-compatible single layout.
+    {
+        "partIds": [
+            "LM308"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "vin+",
+                "in+",
+                "pin3"
+            ],
+            [
+                "vin-",
+                "in-",
+                "pin2"
+            ],
+            [
+                "vout",
+                "out",
+                "pin6"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 300000
+                    },
+                    "terminals": [
+                        0,
+                        1,
+                        2
+                    ]
+                }
+            ],
+            "pinout": [
+                "vin+",
+                "vin-",
+                "vout"
+            ]
+        }
+    },
+    // TI LM324 quad op-amp, from SLOS066AE (Aug 1975, rev Sept 2025): 6.7 Electrical
+    // Characteristics for LM324/LM324K (VCC = 15 V, VO = 1 V to 11 V, RL >= 2 kOhm, 25C):
+    // 'Large-signal differential voltage amplification AVD | MIN 25 TYP 100 | V/mV'.
+    // Used as `openLoopGain: 100000`. GBW is not in this entry: it lives in the
+    // data-registry row (B1 unity-gain bandwidth TYP 1.2 MHz, 6.10 Operating Conditions),
+    // stamped by the pass below. Pinout: Table 5-1 Pin Functions N (PDIP) p3, the
+    // standard quad order (1OUT, 1IN-, 1IN+, VCC+, 2IN+, 2IN-, 2OUT, 3OUT, 3IN-, 3IN+,
+    // VCC-, 4IN+, 4IN-, 4OUT), same A/B/C/D convention as the TL074 entry above.
+    {
+        "partIds": [
+            "LM324"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "OUT_A_pin1"
+            ],
+            [
+                "INVERTING_A_pin2"
+            ],
+            [
+                "NONINVERTING_A_pin3"
+            ],
+            [
+                "V_PLUS_pin4"
+            ],
+            [
+                "NONINVERTING_B_pin5"
+            ],
+            [
+                "INVERTING_B_pin6"
+            ],
+            [
+                "OUT_B_pin7"
+            ],
+            [
+                "OUT_C_pin8"
+            ],
+            [
+                "INVERTING_C_pin9"
+            ],
+            [
+                "NONINVERTING_C_pin10"
+            ],
+            [
+                "V_MINUS_pin11"
+            ],
+            [
+                "NONINVERTING_D_pin12"
+            ],
+            [
+                "INVERTING_D_pin13"
+            ],
+            [
+                "OUT_D_pin14"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "pinout": [
+                "OUT_A",
+                "IN_A_MINUS",
+                "IN_A_PLUS",
+                "VCC",
+                "IN_B_PLUS",
+                "IN_B_MINUS",
+                "OUT_B",
+                "OUT_C",
+                "IN_C_MINUS",
+                "IN_C_PLUS",
+                "VEE",
+                "IN_D_PLUS",
+                "IN_D_MINUS",
+                "OUT_D"
+            ],
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 100000
+                    },
+                    "terminals": [
+                        2,
+                        1,
+                        0
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 100000
+                    },
+                    "terminals": [
+                        4,
+                        5,
+                        6
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 100000
+                    },
+                    "terminals": [
+                        9,
+                        8,
+                        7
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 100000
+                    },
+                    "terminals": [
+                        11,
+                        12,
+                        13
+                    ]
+                }
+            ]
+        }
+    },
+    // TI uA741C single op-amp in the PDIP-8 UA741CP orderable, from SLOS094H (Nov 1970,
+    // rev Feb 2026): 5.4 Electrical Characteristics uA741C (VCC+- = +-15 V, VO = +-10 V,
+    // RL >= 2 kOhm, 25C): 'Large-signal differential voltage amplification AVD |
+    // MIN 20 TYP 200 | V/mV'. Used as `openLoopGain: 200000`. The sheet prints the
+    // orderable as UA741CP (PDIP P|8) and the device table as uA741CP; the ASCII id is
+    // the orderable spelling. No GBW row is transcribed (switching tables print only
+    // rise time, overshoot and SR). Pinout: Figure 4-2 D-or-P 8-pin Top View + Table 4-2
+    // Pin Functions p3 (1 NC, 2 IN-, 3 IN+, 4 VCC-, 5 NC, 6 OUT, 7 VCC+, 8 NC); the entry
+    // keeps the LF351 three-terminal capture (IN+ pin3, IN- pin2, OUT pin6).
+    {
+        "partIds": [
+            "UA741CP"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "vin+",
+                "in+",
+                "pin3"
+            ],
+            [
+                "vin-",
+                "in-",
+                "pin2"
+            ],
+            [
+                "vout",
+                "out",
+                "pin6"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 200000
+                    },
+                    "terminals": [
+                        0,
+                        1,
+                        2
+                    ]
+                }
+            ],
+            "pinout": [
+                "vin+",
+                "vin-",
+                "vout"
+            ]
+        }
+    },
+    // TI TLC2262 dual LinCMOS op-amp, from SLOS177D (Feb 1997, rev Mar 2001): TLC2262C
+    // operating characteristics (VDD+- = +-5 V, the 10 V table closest to a 9 V pedal):
+    // 'Large-signal differential voltage amplification, RL = 50 kOhm, VO = +-4 V:
+    // MIN 80 TYP 200 V/mV'. Used as `openLoopGain: 200000`. Coordinator standing rule
+    // 2026-10-19: the bare id the sheet names in its description takes the commercial (C)
+    // grade column, disclosed here; no suffixed grade is aliased. GBW is not in this
+    // entry: it lives in the data-registry row (TYP 0.73 MHz, same table), stamped by the
+    // pass below. Pinout: D/P/PW 8-pin Top View p3, the standard dual order
+    // (1OUT, 1IN-, 1IN+, VDD-/GND, 2IN+, 2IN-, 2OUT, VDD+), same A/B convention as the
+    // LM833 entry above.
+    {
+        "partIds": [
+            "TLC2262"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "OUT_A_pin1"
+            ],
+            [
+                "INVERTING_A_pin2"
+            ],
+            [
+                "NONINVERTING_A_pin3"
+            ],
+            [
+                "V_MINUS_pin4"
+            ],
+            [
+                "NONINVERTING_B_pin5"
+            ],
+            [
+                "INVERTING_B_pin6"
+            ],
+            [
+                "OUT_B_pin7"
+            ],
+            [
+                "V_PLUS_pin8"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "pinout": [
+                "OUT_A",
+                "IN_A_MINUS",
+                "IN_A_PLUS",
+                "VEE",
+                "IN_B_PLUS",
+                "IN_B_MINUS",
+                "OUT_B",
+                "VCC"
+            ],
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 200000
+                    },
+                    "terminals": [
+                        2,
+                        1,
+                        0
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 200000
+                    },
+                    "terminals": [
+                        4,
+                        5,
+                        6
+                    ]
+                }
+            ]
+        }
+    },
+    // onsemi MC33174 quad op-amp, from MC33171/D Rev. 14 Jul 2025: DC table (VCC = +15 V,
+    // VEE = -15 V, RL to ground, TA = 25C) p3: 'Large Signal Voltage Gain (VO = +-10 V,
+    // RL = 10 k), AVOL MIN 50 TYP 500 V/mV'. Used as `openLoopGain: 500000`. GBW is not
+    // in this entry: it lives in the data-registry row (TYP 1.8 MHz at f = 100 kHz, AC
+    // table p4), stamped by the pass below. Pinout: PIN CONNECTIONS quad diagram p2
+    // incl. PDIP-14 (Output 1 = 1, Inputs 1, VCC, Inputs 2, Output 2, Output 3,
+    // Inputs 3, VEE, Inputs 4, Output 4), the standard quad order, same A/B/C/D
+    // convention as the TL074 entry.
+    {
+        "partIds": [
+            "MC33174"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "OUT_A_pin1"
+            ],
+            [
+                "INVERTING_A_pin2"
+            ],
+            [
+                "NONINVERTING_A_pin3"
+            ],
+            [
+                "V_PLUS_pin4"
+            ],
+            [
+                "NONINVERTING_B_pin5"
+            ],
+            [
+                "INVERTING_B_pin6"
+            ],
+            [
+                "OUT_B_pin7"
+            ],
+            [
+                "OUT_C_pin8"
+            ],
+            [
+                "INVERTING_C_pin9"
+            ],
+            [
+                "NONINVERTING_C_pin10"
+            ],
+            [
+                "V_MINUS_pin11"
+            ],
+            [
+                "NONINVERTING_D_pin12"
+            ],
+            [
+                "INVERTING_D_pin13"
+            ],
+            [
+                "OUT_D_pin14"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "pinout": [
+                "OUT_A",
+                "IN_A_MINUS",
+                "IN_A_PLUS",
+                "VCC",
+                "IN_B_PLUS",
+                "IN_B_MINUS",
+                "OUT_B",
+                "OUT_C",
+                "IN_C_MINUS",
+                "IN_C_PLUS",
+                "VEE",
+                "IN_D_PLUS",
+                "IN_D_MINUS",
+                "OUT_D"
+            ],
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 500000
+                    },
+                    "terminals": [
+                        2,
+                        1,
+                        0
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 500000
+                    },
+                    "terminals": [
+                        4,
+                        5,
+                        6
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 500000
+                    },
+                    "terminals": [
+                        9,
+                        8,
+                        7
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 500000
+                    },
+                    "terminals": [
+                        11,
+                        12,
+                        13
+                    ]
+                }
+            ]
+        }
+    },
+    // Wave-5 op-amp entries: sections whose open-loop gain is the sheet's own TYP AOL
+    // transcribed (the gain-bandwidth product lives in `registry-data/opamp.ts`, stamped by
+    // the passes below; the swing pair stays absent per the D4 freeze). GBW rows and catalog
+    // entries are 1:1 by part id, so no entry splits. TL072C carries AOL only (no single
+    // GBW figure exists; see `opampGainBandwidthAbsent`).
+    // TI TL072C dual JFET-input op-amp, from SLOS080W (Sep 1978, rev Jul 2025): 5.8 DC
+    // (VS = +-15 V, TA = 25C, VO = 0 V): 'AOL | Open-loop voltage gain | TL07xC |
+    // MIN 25 TYP 200 V/mV'. Used as `openLoopGain: 200000` (bare id takes the commercial
+    // C-grade column, disclosed; no suffixed alias). Pinout: Table 4-3 Pin Functions
+    // TL072x (1 1OUT, 2 1IN-, 3 1IN+, 4 VCC-, 5 2IN+, 6 2IN-, 7 2OUT, 8 VCC+), the
+    // standard dual order, same pin-numbered role convention as the NJM4580 entry.
+    {
+        "partIds": [
+            "TL072C"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "OUT_A_pin1"
+            ],
+            [
+                "INVERTING_A_pin2"
+            ],
+            [
+                "NONINVERTING_A_pin3"
+            ],
+            [
+                "V_MINUS_pin4"
+            ],
+            [
+                "NONINVERTING_B_pin5"
+            ],
+            [
+                "INVERTING_B_pin6"
+            ],
+            [
+                "OUT_B_pin7"
+            ],
+            [
+                "V_PLUS_pin8"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "pinout": [
+                "OUT_A",
+                "IN_A_MINUS",
+                "IN_A_PLUS",
+                "VEE",
+                "IN_B_PLUS",
+                "IN_B_MINUS",
+                "OUT_B",
+                "VCC"
+            ],
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 200000
+                    },
+                    "terminals": [
+                        2,
+                        1,
+                        0
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 200000
+                    },
+                    "terminals": [
+                        4,
+                        5,
+                        6
+                    ]
+                }
+            ]
+        }
+    },
+    // TI OPA1678 dual audio op-amp, from SBOS855E (Jan 2017 - Dec 2022): 6.7 Electrical
+    // Characteristics (VS = +-15 V, TA = 25C, RL = 2 kOhm, VCM = VOUT = midsupply):
+    // 'AOL | Open-loop voltage gain | (V-) + 0.8 V <= VO <= (V+) - 0.8 V | MIN 106
+    // TYP 114 | dB'. Used as `openLoopGain: decibelGain(114)` = 501187.2336272725.
+    // GBW lives in the data-registry row (TYP 16 MHz at G = 1). Pinout: 5 Pin
+    // Configuration and Functions, Pin Functions OPA1678 (OUT A-1, -IN A-2, +IN A-3,
+    // V--4, +IN B-5, -IN B-6, OUT B-7, V+-8), the standard dual order.
+    {
+        "partIds": [
+            "OPA1678"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "OUT_A_pin1"
+            ],
+            [
+                "INVERTING_A_pin2"
+            ],
+            [
+                "NONINVERTING_A_pin3"
+            ],
+            [
+                "V_MINUS_pin4"
+            ],
+            [
+                "NONINVERTING_B_pin5"
+            ],
+            [
+                "INVERTING_B_pin6"
+            ],
+            [
+                "OUT_B_pin7"
+            ],
+            [
+                "V_PLUS_pin8"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "pinout": [
+                "OUT_A",
+                "IN_A_MINUS",
+                "IN_A_PLUS",
+                "VEE",
+                "IN_B_PLUS",
+                "IN_B_MINUS",
+                "OUT_B",
+                "VCC"
+            ],
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 501187.2336272725
+                    },
+                    "terminals": [
+                        2,
+                        1,
+                        0
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 501187.2336272725
+                    },
+                    "terminals": [
+                        4,
+                        5,
+                        6
+                    ]
+                }
+            ]
+        }
+    },
+    // TI (Burr-Brown) OPA134 single audio op-amp, from SBOS058B (Dec 1997, Rev. B
+    // Nov 2024): 5.7 Electrical Characteristics (TA = 25C, VS = +-15 V): 'AOL |
+    // Open-loop voltage gain | RL = 2 kOhm, -13.8 V <= VO <= 13.5 V | MIN 104
+    // TYP 120 | dB' (a second row at RL = 10 kOhm reads the same 104/120). Used as
+    // `openLoopGain: decibelGain(120)` = 1000000. GBW lives in the data-registry row
+    // (TYP 8 MHz). OPA134PA is the printed PDIP-8 orderable of the same die
+    // (orderable table: 'OPA134PA | Active | Production | PDIP (P) | 8'; family specs
+    // with no per-orderable split). Pinout: Figure 4-1 + Pin Functions OPA134
+    // (+IN-3, -IN-2, OUT-6); the entry keeps the LF351 three-terminal capture.
+    {
+        "partIds": [
+            "OPA134PA"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "vin+",
+                "in+",
+                "pin3"
+            ],
+            [
+                "vin-",
+                "in-",
+                "pin2"
+            ],
+            [
+                "vout",
+                "out",
+                "pin6"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 1000000
+                    },
+                    "terminals": [
+                        0,
+                        1,
+                        2
+                    ]
+                }
+            ],
+            "pinout": [
+                "vin+",
+                "vin-",
+                "vout"
+            ]
+        }
+    },
+    // TI (Burr-Brown) OPA604 single op-amp, from SBOS019A (Jan 1992 - Sep 2003):
+    // ELECTRICAL CHARACTERISTICS (TA = +25C, VS = +-15 V, MIN/TYP/MAX columns):
+    // 'OPEN-LOOP GAIN | Open-Loop Voltage Gain, VO = +-10 V, RL = 1 kOhm: MIN 80
+    // TYP 100 dB'. Used as `openLoopGain: decibelGain(100)` = 100000. GBW lives in
+    // the data-registry row (TYP 20 MHz at G = 100, quoted with its condition).
+    // OPA604AP is named by the specs header ('OPA604AP, AU'); the PDIP suffix follows
+    // the Burr-Brown AP convention (the Package Option Addendum lists AU active).
+    // Pinout: the DIP/SOIC diagram (-In-2, +In-3, OUT-6); the LF351 three-terminal
+    // capture, same as the UA741CP entry.
+    {
+        "partIds": [
+            "OPA604AP"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "vin+",
+                "in+",
+                "pin3"
+            ],
+            [
+                "vin-",
+                "in-",
+                "pin2"
+            ],
+            [
+                "vout",
+                "out",
+                "pin6"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 100000
+                    },
+                    "terminals": [
+                        0,
+                        1,
+                        2
+                    ]
+                }
+            ],
+            "pinout": [
+                "vin+",
+                "vin-",
+                "vout"
+            ]
+        }
+    },
+    // Wave-2 op-amp entries: sections whose open-loop gain is the sheet's own TYP AOL
+    // transcribed (the gain-bandwidth product lives in `registry-data/opamp.ts`, stamped by
+    // the passes below; the swing pair stays absent per the D4 freeze). GBW rows and catalog
+    // entries are 1:1 by part id, so no entry splits.
+    // ADI AD712 dual precision BiFET op-amp, from the ADI AD712 datasheet Rev. B
+    // (SPECIFICATIONS at VS = +-15 V @ TA = +25C): OPEN-LOOP GAIN MIN 150 TYP 400 V/mV
+    // (J/A/S grades; K/B/T and C print MIN 200 TYP 400 -- TYP 400 in every grade, so the
+    // bare id carries it). Used as `openLoopGain: 400000`. The sheet's frequency row reads
+    // 'Small Signal Bandwidth 3.0 MIN 4.0 TYP MHz' with no closed-loop gain stated and never
+    // uses the term gain-bandwidth, so no GBW figure is transcribed (see
+    // `opampGainBandwidthAbsent`). Pinout: 'pinned out in a standard op amp configuration'
+    // (dual DIP-8 order, same pin-numbered role convention as the LM833 entry above).
+    {
+        "partIds": [
+            "AD712"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "OUT_A_pin1"
+            ],
+            [
+                "INVERTING_A_pin2"
+            ],
+            [
+                "NONINVERTING_A_pin3"
+            ],
+            [
+                "V_MINUS_pin4"
+            ],
+            [
+                "NONINVERTING_B_pin5"
+            ],
+            [
+                "INVERTING_B_pin6"
+            ],
+            [
+                "OUT_B_pin7"
+            ],
+            [
+                "V_PLUS_pin8"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "pinout": [
+                "OUT_A",
+                "IN_A_MINUS",
+                "IN_A_PLUS",
+                "VEE",
+                "IN_B_PLUS",
+                "IN_B_MINUS",
+                "OUT_B",
+                "VCC"
+            ],
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 400000
+                    },
+                    "terminals": [
+                        2,
+                        1,
+                        0
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 400000
+                    },
+                    "terminals": [
+                        4,
+                        5,
+                        6
+                    ]
+                }
+            ]
+        }
+    },
+    // TI LF347 quad JFET-input op-amp, from SLOS013C (Mar 1987, rev Mar 2016):
+    // 6.5 AVD 'Large signal differential voltage, VO = +-10 V, RL = 2 kOhm, 25C: MIN 25
+    // TYP 100 V/mV' (6.6 LF347B: MIN 50 TYP 100). Used as `openLoopGain: 100000`.
+    // LF347N is the PDIP-14 of the LF347 grade. Pinout: the sheet's own Pin Functions
+    // table (1 1OUT, 2 1IN-, 3 1IN+, 4 VCC+, 5 2IN+, 6 2IN-, 7 2OUT, 8 3OUT, 9 3IN-,
+    // 10 3IN+, 11 VCC-, 12 4IN+, 13 4IN-, 14 4OUT) -- the standard quad order.
+    {
+        "partIds": [
+            "LF347",
+            "LF347N"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "OUT_A_pin1"
+            ],
+            [
+                "INVERTING_A_pin2"
+            ],
+            [
+                "NONINVERTING_A_pin3"
+            ],
+            [
+                "V_PLUS_pin4"
+            ],
+            [
+                "NONINVERTING_B_pin5"
+            ],
+            [
+                "INVERTING_B_pin6"
+            ],
+            [
+                "OUT_B_pin7"
+            ],
+            [
+                "OUT_C_pin8"
+            ],
+            [
+                "INVERTING_C_pin9"
+            ],
+            [
+                "NONINVERTING_C_pin10"
+            ],
+            [
+                "V_MINUS_pin11"
+            ],
+            [
+                "NONINVERTING_D_pin12"
+            ],
+            [
+                "INVERTING_D_pin13"
+            ],
+            [
+                "OUT_D_pin14"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "pinout": [
+                "OUT_A",
+                "IN_A_MINUS",
+                "IN_A_PLUS",
+                "VCC",
+                "IN_B_PLUS",
+                "IN_B_MINUS",
+                "OUT_B",
+                "OUT_C",
+                "IN_C_MINUS",
+                "IN_C_PLUS",
+                "VEE",
+                "IN_D_PLUS",
+                "IN_D_MINUS",
+                "OUT_D"
+            ],
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 100000
+                    },
+                    "terminals": [
+                        2,
+                        1,
+                        0
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 100000
+                    },
+                    "terminals": [
+                        4,
+                        5,
+                        6
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 100000
+                    },
+                    "terminals": [
+                        9,
+                        8,
+                        7
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 100000
+                    },
+                    "terminals": [
+                        11,
+                        12,
+                        13
+                    ]
+                }
+            ]
+        }
+    },
+    // National Semiconductor LF351 single JFET-input op-amp, from DS005648 Rev. 3 (1998):
+    // AVOL 'Large Signal Voltage Gain, VS = +-15 V, TA = 25C, VO = +-10 V, RL = 2 kOhm:
+    // MIN 25 TYP 100 V/mV'. Used as `openLoopGain: 100000`. LF351N is the DIP orderable
+    // (NS Package N08E, sheet p11 'Order Number LF351M or LF351N'). Pinout: 'pin compatible
+    // with the standard LM741' (single DIP-8: IN+ pin3, IN- pin2, OUT pin6), the same
+    // three-terminal capture as the TL061 entry above.
+    {
+        "partIds": [
+            "LF351",
+            "LF351N"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "vin+",
+                "in+",
+                "pin3"
+            ],
+            [
+                "vin-",
+                "in-",
+                "pin2"
+            ],
+            [
+                "vout",
+                "out",
+                "pin6"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 100000
+                    },
+                    "terminals": [
+                        0,
+                        1,
+                        2
+                    ]
+                }
+            ],
+            "pinout": [
+                "vin+",
+                "vin-",
+                "vout"
+            ]
+        }
+    },
+    // SGS-THOMSON L272 dual power op-amp, from the L272 datasheet (Jan 1995):
+    // ELECTRICAL CHARACTERISTICS (Vs = 24 V, Tamb = 25C): 'Gv | O. L. Voltage Gain |
+    // f = 100 Hz | MIN 60 TYP 70 dB' (f = 1 kHz TYP 50 dB). Used as
+    // `openLoopGain: decibelGain(70)` = 3162.2776601683795. Pinout: the sheet's PIN
+    // CONNECTIONS are diagrams only (no text pin table could be extracted), so this entry
+    // asserts NO pin order (neutral null pinout, M5218 precedent) and serves
+    // section-grouped declarations; a packet study must verify the order before pin
+    // positions are typed. One family table for L272/L272M/L272D.
+    {
+        "partIds": [
+            "L272",
+            "L272M",
+            "L272D"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [],
+        "model": {
+            "kind": "sections",
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 3162.2776601683795
+                    },
+                    "terminals": [
+                        2,
+                        1,
+                        0
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 3162.2776601683795
+                    },
+                    "terminals": [
+                        4,
+                        5,
+                        6
+                    ]
+                }
+            ],
+            "pinout": [
+                null,
+                null,
+                null,
+                null,
+                null,
+                null,
+                null,
+                null
+            ]
+        }
+    },
+    // TI TL074 quad JFET-input op-amp, from SLOS080W (Sep 1978, rev Jul 2025):
+    // 5.8 DC (VS = +-15 V, TA = 25C, VO = 0 V): 'AOL | Open-loop voltage gain | TL07xC |
+    // MIN 25 TYP 200 V/mV' (full-range row MIN-only 15; AC/BC 50/200, M 35/200, I MIN-only
+    // 25 -- the I grade is not covered). Used as `openLoopGain: 200000`. TL074CN (PDIP-N)
+    // and TL074CD (SOIC-D) are C-grade 'all other devices' for the 5.25 MHz GBW row.
+    // Pinout: the sheet's own Table 4-6 Pin Functions TL074x (1 1OUT, 2 1IN-, 3 1IN+,
+    // 4 VCC+, 5 2IN+, 6 2IN-, 7 2OUT, 8 3OUT, 9 3IN-, 10 3IN+, 11 VCC-, 12 4IN+,
+    // 13 4IN-, 14 4OUT).
+    {
+        "partIds": [
+            "TL074",
+            "TL074CN",
+            "TL074CD"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "OUT_A_pin1"
+            ],
+            [
+                "INVERTING_A_pin2"
+            ],
+            [
+                "NONINVERTING_A_pin3"
+            ],
+            [
+                "V_PLUS_pin4"
+            ],
+            [
+                "NONINVERTING_B_pin5"
+            ],
+            [
+                "INVERTING_B_pin6"
+            ],
+            [
+                "OUT_B_pin7"
+            ],
+            [
+                "OUT_C_pin8"
+            ],
+            [
+                "INVERTING_C_pin9"
+            ],
+            [
+                "NONINVERTING_C_pin10"
+            ],
+            [
+                "V_MINUS_pin11"
+            ],
+            [
+                "NONINVERTING_D_pin12"
+            ],
+            [
+                "INVERTING_D_pin13"
+            ],
+            [
+                "OUT_D_pin14"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "pinout": [
+                "OUT_A",
+                "IN_A_MINUS",
+                "IN_A_PLUS",
+                "VCC",
+                "IN_B_PLUS",
+                "IN_B_MINUS",
+                "OUT_B",
+                "OUT_C",
+                "IN_C_MINUS",
+                "IN_C_PLUS",
+                "VEE",
+                "IN_D_PLUS",
+                "IN_D_MINUS",
+                "OUT_D"
+            ],
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 200000
+                    },
+                    "terminals": [
+                        2,
+                        1,
+                        0
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 200000
+                    },
+                    "terminals": [
+                        4,
+                        5,
+                        6
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 200000
+                    },
+                    "terminals": [
+                        9,
+                        8,
+                        7
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 200000
+                    },
+                    "terminals": [
+                        11,
+                        12,
+                        13
+                    ]
+                }
+            ]
+        }
+    },
+    // Wave 2 (JED): TI CD4016B quad bilateral switch. Its own entry (NOT an alias of the
+    // CD4066 entry above): the 4016 is the high-Ron predecessor and the 4066 its
+    // pin-compatible low-Ron replacement (onsemi MC14066B: 'designed to be pin-for-pin
+    // compatible with the MC14016B, but has much lower ON resistance'; ST HCF4066B: 'pin
+    // for pin compatible with HCF4016B, but exhibits a much lower ON resistance').
+    // On-resistance from TI CD4016B SCHS026D Rev. E (Aug 2024), Features p1: '280 Ohm
+    // typical on-state resistance for 15 V operation' (switch matching 'within 10 Ohm typ
+    // over 15 V signal-input range'). The 4.5 table's at-rail TYP at 15 V is 200 Ohm
+    // (MAX 400; mid-supply worst-case MAX-only 850) -- the 280 headline is the over-range
+    // figure and is the transcribed value. offOhms/thresholdVolts repeat the 4066 entry
+    // (not newly cited). Only the ids the TI sheet owns: the unbuffered CD4016, HEF/HCF/MC
+    // variants are not covered (Nexperia's HEF4016B specs a different test: 115 Ohm
+    // peak-typ at 15 V, 100 uA, sharing no figure with this row).
+    {
+        "partIds": [
+            "4016B",
+            "CD4016B"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "switch_a",
+                "in",
+                "a",
+                "sig_in",
+                "inout1",
+                "1in/out",
+                "in/out"
+            ],
+            [
+                "switch_b",
+                "out",
+                "b",
+                "sig_out",
+                "inout2",
+                "1out/in",
+                "out/in"
+            ],
+            [
+                "control",
+                "ctrl",
+                "c",
+                "gate",
+                "ctl",
+                "1control"
+            ],
+            [
+                "vcc",
+                "vdd",
+                "vplus",
+                "v+"
+            ],
+            [
+                "vss",
+                "gnd",
+                "vminus",
+                "v-",
+                "ground"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "sections": [
+                {
+                    "law": {
+                        "kind": "analog-switch",
+                        "onOhms": 280,
+                        "offOhms": 1000000000,
+                        "thresholdVolts": 2
+                    },
+                    "terminals": [
+                        0,
+                        1,
+                        2
+                    ]
+                }
+            ],
+            "pinout": [
+                "switch_a",
+                "switch_b",
+                "control",
+                "vcc",
+                "vss"
+            ]
+        }
+    },
+    // Wave 2 (JED): Cabintech CT3101 BBD clock generator. Its own entry mirroring the
+    // MN3101 above (same 8-pin DIL footprint, same terminal order), NOT an unsourced alias:
+    // the CT3101's own datasheet ('CT3101 BBD Clock Generator - Datasheet', Rev 1,
+    // Aug 2023, Cabintech Global LLC, https://cabintechglobal.com/pdf/CABINTECH_CT3101.pdf)
+    // states it 'is pin-for-pin compatible with the discontinued Panasonic MN3101' and 'can
+    // be used as a drop-in replacement for the MN3101', with the pin table 1 GND, 2 CP1,
+    // 3 Vdd (-3 V to -18 V), 4 CP2, 5 OX3, 6 OX2, 7 OX1, 8 Vgg (14/15 Vdd output).
+    // No quiescentSupplyAmps: the sheet says only 'about 1/2 of MN3101' (no figure).
+    // It is a hybrid module (CD4047-based), not a monolithic second source.
+    {
+        "partIds": [
+            "CT3101"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "gnd",
+                "v-",
+                "vss",
+                "pin1",
+                "gndpin1"
+            ],
+            [
+                "cp1",
+                "clk1",
+                "clock1",
+                "phi1",
+                "pin2",
+                "cp1pin2"
+            ],
+            [
+                "vdd",
+                "v+",
+                "vcc",
+                "pin3",
+                "vddpin3"
+            ],
+            [
+                "cp2",
+                "clk2",
+                "clock2",
+                "phi2",
+                "pin4",
+                "cp2pin4"
+            ],
+            [
+                "ox3",
+                "osc3",
+                "oscctrl",
+                "pin5",
+                "ox3pin5"
+            ],
+            [
+                "ox2",
+                "osc2",
+                "oscout",
+                "pin6",
+                "ox2pin6"
+            ],
+            [
+                "ox1",
+                "osc1",
+                "oscin",
+                "osc",
+                "pin7",
+                "ox1pin7"
+            ],
+            [
+                "vgg",
+                "vggout",
+                "pin8",
+                "vggoutpin8"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "sections": [
+                {
+                    "law": {
+                        "kind": "clock-driver",
+                        "defaultFrequency": 10000
+                    },
+                    "terminals": [
+                        1,
+                        3,
+                        7,
+                        2,
+                        6,
+                        0
+                    ]
+                }
+            ],
+            "pinout": [
+                null,
+                null,
+                null,
+                null,
+                null,
+                null,
+                null,
+                null
+            ]
+        }
+    },
+    ...zenerRegistryRecords.map((record) => zenerLaw(record)),
+    // Wave-1 discrete fill: bjt, diode-forward, mosfet and jfet-channel records become
+    // law entries through the builders above -- one list per class, so the entries cannot
+    // drift from the records. 2SK30A rides the same generic path as every other JFET: its
+    // record carries only gateSaturationCurrent, so the builder gap-fills the class channel
+    // and the stamp is byte-identical to the bespoke mapping this replaces.
+    ...bjtRegistryRecords.map((record) => bjtLawEntry(record)),
+    ...diodeRegistryRecords.map((record) => diodeLawEntry(record)),
+    ...mosfetRegistryRecords.map((record) => fetLawEntry(record, "mosfet")),
+    ...jfetRegistryRecords.map((record) => fetLawEntry(record, "jfet")),
+];
+// --- Op-amp gain-bandwidth product: stamped from the data registry ------------------------------
+/**
+ * Merge a stamped row's `community`-basis parameters into the entry's provisional arm.
+ * A row whose parameters are all better-sourced adds nothing, and an entry with no
+ * provisional value keeps the field absent rather than gaining an empty one.
+ */
+function withRowProvisional(entry, row) {
+    const merged = [...(entry.provisionalParams ?? [])];
+    row.params.forEach((param, index) => {
+        if (param?.basis !== "community" || typeof param.url !== "string")
+            return;
+        const name = row.names[index];
+        if (!merged.some((held) => held.name === name)) {
+            merged.push({ name, url: param.url });
+        }
+    });
+    return merged.length === 0 ? {} : { provisionalParams: merged };
+}
+//
+// The figures live in `registry-data/opamp.ts` as cited values (datasheet TYP rows, quoted).
+// This pass stamps each record's product onto the op-amp sections of exactly the ids it
+// covers. An entry whose ids have different products (or none) is split into one entry per
+// product, keeping every other field, so no id changes behaviour except by gaining its own
+// figure.
+//
+// Loud on any mismatch, as before: a record or absent id the catalog holds no op-amp entry
+// for, an id in both lists, or an id in two records is a table error and throws at load
+// rather than being silently skipped.
+function withDatasheetGainBandwidth(base) {
+    const rowOf = new Map();
+    for (const row of opampRegistryRecords) {
+        if (row.gainBandwidthHz === undefined)
+            continue;
+        for (const id of row.partIds) {
+            const folded = foldPartId(id);
+            if (rowOf.has(folded))
+                throw new Error(`gain-bandwidth table names ${id} twice`);
+            rowOf.set(folded, row);
+        }
+    }
+    const absent = new Set();
+    for (const { partIds } of opampGainBandwidthAbsent) {
+        for (const id of partIds) {
+            const folded = foldPartId(id);
+            if (rowOf.has(folded))
+                throw new Error(`${id} is both given a gain-bandwidth figure and listed absent`);
+            absent.add(folded);
+        }
+    }
+    const seen = new Set();
+    const out = [];
+    for (const entry of base) {
+        const sections = entry.model.kind === "sections" ? entry.model.sections : null;
+        const isOpamp = sections !== null && sections.length > 0 && sections.every((section) => section.law.kind === "ideal-opamp");
+        if (!isOpamp || sections === null || entry.model.kind !== "sections") {
+            out.push(entry);
+            continue;
+        }
+        const groups = new Map();
+        for (const id of entry.partIds) {
+            const folded = foldPartId(id);
+            seen.add(folded);
+            const row = rowOf.get(folded) ?? null;
+            const group = groups.get(row);
+            if (group === undefined)
+                groups.set(row, [id]);
+            else
+                group.push(id);
+        }
+        const model = entry.model;
+        for (const [row, partIds] of groups) {
+            if (row === null) {
+                out.push(groups.size === 1 ? entry : { ...entry, partIds });
+                continue;
+            }
+            const hertz = row.gainBandwidthHz?.value;
+            if (hertz === undefined || !(hertz > 0)) {
+                throw new Error(`${partIds.join(",")}: gain-bandwidth record states no positive product`);
+            }
+            out.push({
+                ...entry,
+                partIds,
+                ...withRowProvisional(entry, {
+                    params: [row.gainBandwidthHz],
+                    names: ["gainBandwidthHz"],
+                }),
+                model: {
+                    ...model,
+                    sections: model.sections.map((section) => section.law.kind === "ideal-opamp"
+                        ? { ...section, law: { ...section.law, gainBandwidthHz: hertz } }
+                        : section),
+                },
+            });
+        }
+    }
+    for (const folded of [...rowOf.keys(), ...absent]) {
+        if (!seen.has(folded))
+            throw new Error(`gain-bandwidth table names ${folded}, which no op-amp entry holds`);
+    }
+    return out;
+}
+// --- Op-amp output swing: stamped from the data registry -------------------------------------------------
+//
+// The same rules as the gain-bandwidth pass above. A record states the drop from each rail at
+// the printed condition; `translation` is how that pair is carried to a pedal on another supply:
+//   "constant"      the printed drops are applied as printed (a headroom independent of the supply);
+//   "proportional"  both are multiplied by the op-amp's supply span over `supplyVolts`.
+// The datasheet states neither: it is the owner's reading, recorded per record, and the table does not
+// say it is shown right. Only the OP07 reading has a held-out hardware test behind it (T-a1, row 16),
+// and a test of a rule written first is not a measurement of the rule.
+/**
+ * The catalog's op-amp entries with each registry record's swing pair stamped onto the sections
+ * of exactly the ids it covers. An entry whose ids have different rows (or none) is split into
+ * one entry per row, keeping every other field, so no id changes behaviour except by gaining
+ * its own pair.
+ *
+ * Loud on any mismatch, as `withDatasheetGainBandwidth` is: a record or absent id the catalog
+ * holds no op-amp entry for, an id in both lists, an id in two records, a base entry that
+ * already carries a swing field (every figure comes through the registry), or a record whose
+ * numbers do not validate (`opampOutputSwingOf`) throws at load.
+ */
+export function withDatasheetOutputSwing(base, rows = opampRegistryRecords, absentRows = opampOutputSwingAbsent) {
+    const rowOf = new Map();
+    for (const row of rows) {
+        const high = row.outputSwingDropHighVolts;
+        const low = row.outputSwingDropLowVolts;
+        const printed = row.outputSwingPrinted;
+        if (high === undefined && low === undefined && printed === undefined)
+            continue;
+        if (high === undefined || low === undefined || printed === undefined) {
+            throw new Error(`${row.partIds.join(",")}: an op-amp swing record states a half pair (high ${high === undefined ? "absent" : "present"}, low ${low === undefined ? "absent" : "present"}, printed ${printed === undefined ? "absent" : "present"})`);
+        }
+        for (const id of row.partIds) {
+            const folded = foldPartId(id);
+            if (rowOf.has(folded))
+                throw new Error(`output-swing table names ${id} twice`);
+            rowOf.set(folded, row);
+        }
+    }
+    const absent = new Set();
+    for (const { partIds, reason } of absentRows) {
+        if (reason.length === 0)
+            throw new Error(`output-swing absent row for ${partIds.join(",")} states no reason`);
+        for (const id of partIds) {
+            const folded = foldPartId(id);
+            if (rowOf.has(folded))
+                throw new Error(`${id} is both given an output-swing pair and listed absent`);
+            absent.add(folded);
+        }
+    }
+    const seen = new Set();
+    const out = [];
+    for (const entry of base) {
+        const sections = entry.model.kind === "sections" ? entry.model.sections : null;
+        const isOpamp = sections !== null && sections.length > 0 && sections.every((section) => section.law.kind === "ideal-opamp");
+        if (!isOpamp || sections === null || entry.model.kind !== "sections") {
+            out.push(entry);
+            continue;
+        }
+        for (const section of sections) {
+            const law = section.law;
+            if (law.kind === "ideal-opamp" &&
+                (law.outputSwingDropHighVolts !== undefined ||
+                    law.outputSwingDropLowVolts !== undefined ||
+                    law.outputSwingPrinted !== undefined)) {
+                throw new Error(`${entry.partIds.join(",")}: an op-amp entry states an output swing in place; it must come through the registry`);
+            }
+        }
+        const groups = new Map();
+        for (const id of entry.partIds) {
+            const folded = foldPartId(id);
+            seen.add(folded);
+            const row = rowOf.get(folded) ?? null;
+            const group = groups.get(row);
+            if (group === undefined)
+                groups.set(row, [id]);
+            else
+                group.push(id);
+        }
+        const model = entry.model;
+        for (const [row, partIds] of groups) {
+            if (row === null) {
+                out.push(groups.size === 1 ? entry : { ...entry, partIds });
+                continue;
+            }
+            const high = row.outputSwingDropHighVolts?.value;
+            const low = row.outputSwingDropLowVolts?.value;
+            const printed = row.outputSwingPrinted;
+            if (high === undefined || low === undefined || printed === undefined) {
+                throw new Error(`${partIds.join(",")}: an op-amp swing record states a half pair`);
+            }
+            const stamped = {
+                ...entry,
+                partIds,
+                ...withRowProvisional(entry, {
+                    params: [row.outputSwingDropHighVolts, row.outputSwingDropLowVolts],
+                    names: ["outputSwingDropHighVolts", "outputSwingDropLowVolts"],
+                }),
+                model: {
+                    ...model,
+                    sections: model.sections.map((section) => section.law.kind === "ideal-opamp"
+                        ? {
+                            ...section,
+                            law: {
+                                ...section.law,
+                                outputSwingDropHighVolts: high,
+                                outputSwingDropLowVolts: low,
+                                outputSwingPrinted: {
+                                    supplyVolts: printed.supplyVolts,
+                                    loadOhms: printed.loadOhms,
+                                    translation: printed.translation,
+                                },
+                            },
+                        }
+                        : section),
+                },
+            };
+            // A malformed record (a non-positive figure, an unknown translation) throws here, naming the ids.
+            for (const section of stamped.model.kind === "sections" ? stamped.model.sections : []) {
+                if (section.law.kind === "ideal-opamp")
+                    opampOutputSwingOf(section.law, partIds.join(","));
+            }
+            out.push(stamped);
+        }
+    }
+    for (const folded of [...rowOf.keys(), ...absent]) {
+        if (!seen.has(folded))
+            throw new Error(`output-swing table names ${folded}, which no op-amp entry holds`);
+    }
+    return out;
+}
+/**
+ * Every part id whose `fet` entry refines the gate term only, folded for comparison.
+ * Derived from the jfet registry records that state NO channel parameter (a record that
+ * states thresholdVolts or transconductance carries a full channel and is not gate-only):
+ * such an entry keeps its avowed class channel, which is never graded against the database's
+ * beta/lambda/Vp the way a transcribed channel would be. Mirrors `zenerCatalogPartIds`.
+ */
+const GATE_ONLY_EXCLUDED_PARAMS = new Set([
+    "thresholdVolts",
+    "transconductance",
+    "channelLengthModulation",
+    "subthresholdVolts",
+]);
+export const gateOnlyFetPartIds = new Set(jfetRegistryRecords
+    .filter((record) => Object.keys(record.params).every((name) => !GATE_ONLY_EXCLUDED_PARAMS.has(name)))
+    .flatMap((record) => [
+    ...record.partIds,
+    ...(record.aliases ?? []),
+])
+    .map((id) => foldPartId(id)));
+/**
+ * The catalog the corpus-facing scripts inject.
+ */
+export const pedalPartCatalog = {
+    entries: withDatasheetOutputSwing(withDatasheetGainBandwidth(entries)),
+};
 //# sourceMappingURL=part-catalog.js.map