@vessel-dsp/compiler 0.17.0 → 0.18.1

package/dist/part-catalog.js

@@ -51,8 +51,8 @@
 // reason and states no swing. Nearly every printed row is at +-15 V and nearly every pedal
 // runs at 9 V, so the carry is a named choice, and `opamp-law-default-parameters` names
 // every device it was carried for.
-import { foldPartId, opampOutputSwingOf } from "./registry.js";
-import { bjtRegistryRecords, chargePumpRegistryRecords, diodeRegistryRecords, findPartRegistryData, jfetRegistryRecords, ledRegistryRecords, mosfetRegistryRecords, opampGainBandwidthAbsent, opampOutputSwingAbsent, opampRegistryRecords, regulatorRegistryRecords, ujtRegistryRecords, zenerRegistryRecords, communityProvenanceOf, } from "./registry-data/index.js";
+import { foldPartId, opampOutputSwingOf, validatePackagePinNumbers } from "./registry.js";
+import { bjtRegistryRecords, chargePumpRegistryRecords, diodeRegistryRecords, findPartRegistryData, jfetRegistryRecords, ledRegistryRecords, mosfetRegistryRecords, opampGainBandwidthAbsent, opampOutputSwingAbsent, opampRegistryRecords, powerAmpRegistryRecords, regulatorRegistryRecords, ujtRegistryRecords, zenerRegistryRecords, communityProvenanceOf, } from "./registry-data/index.js";
 // The absent lists and the merged op-amp records live in `registry-data/opamp.ts` and are
 // re-exported here so their existing import sites keep working.
 export { opampGainBandwidthAbsent, opampOutputSwingAbsent, opampRegistryRecords, } from "./registry-data/index.js";
@@ -629,6 +629,86 @@ for (const key of Object.keys(chargePumpStructureFor)) {
         throw new Error(`charge-pump wiring skeleton for ${key} is consumed by no registry record`);
     }
 }
+/**
+ * A power-amp record's sections entry: one power-amp section spanning all eight pins.
+ *
+ * Pin order is the datasheet pin order both sheets agree on (TI Table 5-1, NJM p5-1):
+ * 1 GAIN, 2 -INPUT, 3 +INPUT, 4 GND, 5 OUT, 6 VS, 7 BYPASS, 8 GAIN. The terminal role
+ * groups accept the schematic symbol spellings (`gain1`, `vin-`, `vin+`, `gnd`, `vout`,
+ * `vs`, `bypass`, `gain8`, as drawn in the core schx catalog), the DipTrace library
+ * spellings (`IN-`, `IN+`, `OUT`, `POWER +`, `POWER -` -- folding makes the sign vanish,
+ * so those fall through to the pinout guard, which is exactly what it is for), plain
+ * `pin1`..`pin8`, and unambiguous functional aliases. A document the entry was not
+ * written against refuses by name instead of mis-wiring the gain network.
+ *
+ * The law carries the record's five printed resistors, the derived gain-bandwidth
+ * product where the record states one (absent stays absent and lowers to a `null` stamp,
+ * which the compile names), and the house ideal-opamp open-loop gain of the output
+ * follower (100000, the class default -- not a part figure, disclosed here and in the
+ * report with its error bound). Rails are the pedal's, substituted at lowering like
+ * every other railed section. The entry states no swing pair (no printable per-side
+ * figure exists) and no quiescent draw (TI/NJR TYP conflict, unneeded for the gain).
+ */
+export function powerAmpEntry(record) {
+    if (record.class !== "power-amp") {
+        throw new Error(`${record.partIds.join(",")}: a power-amp entry needs class "power-amp", not "${record.class}"`);
+    }
+    for (const name of [
+        "feedbackOhms",
+        "gainSetOhms",
+        "degenerationOhms",
+        "inputShuntOhms",
+        "bypassUpperOhms",
+    ]) {
+        if (citedValueOf(record, name) === undefined) {
+            throw new Error(`${record.partIds.join(",")}: a power-amp record states no ${name}`);
+        }
+    }
+    const gainBandwidthHz = citedValueOf(record, "gainBandwidthHz");
+    return {
+        partIds: entryIdsOf(record),
+        declaredTypes: [],
+        terminalRoleGroups: [
+            ["gain1", "g1", "pin1", "power"],
+            ["vin-", "vinminus", "in-", "inminus", "inverting", "minus", "inm", "pin2"],
+            ["vin+", "vinplus", "in+", "inplus", "noninverting", "plus", "inp", "pin3"],
+            ["gnd", "ground", "vee", "pin4", "power"],
+            ["vout", "out", "output", "pin5"],
+            ["vs", "vcc", "vplus", "v+", "supply", "pin6", "power"],
+            ["bypass", "pin7", "power"],
+            ["gain8", "g8", "pin8"],
+        ],
+        ...provisionalArmOf(record),
+        ...citedArmOf(record),
+        model: {
+            kind: "sections",
+            sections: [
+                {
+                    law: {
+                        kind: "power-amp",
+                        railHigh: null,
+                        railLow: null,
+                        openLoopGain: 100000,
+                        feedbackOhms: citedValueOf(record, "feedbackOhms"),
+                        gainSetOhms: citedValueOf(record, "gainSetOhms"),
+                        degenerationOhms: citedValueOf(record, "degenerationOhms"),
+                        inputShuntOhms: citedValueOf(record, "inputShuntOhms"),
+                        bypassUpperOhms: citedValueOf(record, "bypassUpperOhms"),
+                        ...(gainBandwidthHz === undefined ? {} : { gainBandwidthHz }),
+                    },
+                    terminals: [0, 1, 2, 3, 4, 5, 6, 7],
+                },
+            ],
+            pinout: ["gain1", "inverting", "noninverting", "gnd", "out", "vcc", "bypass", "gain8"],
+            packagePinNumbers: {
+                numbers: ["1", "2", "3", "4", "5", "6", "7", "8"],
+                source: "TI LM386 SNAS545D Rev D pin functions (equivalent schematic p1, Table 5-1: " +
+                    "1 GAIN, 2 -INPUT, 3 +INPUT, 4 GND, 5 OUT, 6 VS, 7 BYPASS, 8 GAIN) and NJR NJM386 " +
+                    "databook p5-1 Equivalent Circuit, identically placed",
+            },
+        },
+    };
+}
 const entries = [
     // uPC4558, from the artifacts library's own vendored copy:
     // `parts/op-amps/UPC4558/datasheets/renesas-upc258-upc4558.pdf` (Renesas `UPC258, UPC4558`,
@@ -669,6 +749,19 @@ const entries = [
                 "vcc",
                 "vee"
             ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "1",
+                    "2",
+                    "3",
+                    "7",
+                    "6",
+                    "5",
+                    "8",
+                    "4"
+                ],
+                "source": "Renesas R03DS0145EJ0200 Rev.2.00 PIN CONFIGURATION (Top View), UPC4558G2: 1 OUT1, 2 -II1, 3 +IN1, 4 V-, 5 IN2, 6 II2, 7 OUT2, 8 V+"
+            },
             "sections": [
                 {
                     "law": {
@@ -773,6 +866,19 @@ const entries = [
                 "OUT_B",
                 "VCC"
             ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8"
+                ],
+                "source": "Nisshinbo NJM4558 datasheet PIN CONFIGURATION (Top View) + PIN FUNCTION: 1 A OUTPUT, 2 A -INPUT, 3 A +INPUT, 4 V-, 5 B +INPUT, 6 B -INPUT, 7 B OUTPUT, 8 V+"
+            },
             "sections": [
                 {
                     "law": {
@@ -837,6 +943,19 @@ const entries = [
                 "OUT_A",
                 "VCC"
             ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "7",
+                    "6",
+                    "5",
+                    "4",
+                    "3",
+                    "2",
+                    "1",
+                    "8"
+                ],
+                "source": "TI SLOS078N Fig. 5-2 TL062x D/JG/P/PS/PW 8-pin (Top View): 1OUT-1, 1IN-minus-2, 1IN-plus-3, VCC-minus-4, 2IN-plus-5, 2IN-minus-6, 2OUT-7, VCC-plus-8"
+            },
             "sections": [
                 {
                     "law": {
@@ -949,6 +1068,19 @@ const entries = [
                 "OUT_A",
                 "VCC"
             ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "7",
+                    "6",
+                    "5",
+                    "4",
+                    "3",
+                    "2",
+                    "1",
+                    "8"
+                ],
+                "source": "TI SLOS080W Fig. 4-5 / Table 4-3 Pin Functions TL072x: 1OUT-1, 1IN-minus-2, 1IN-plus-3, VCC-minus-4, 2IN-plus-5, 2IN-minus-6, 2OUT-7, VCC-plus-8"
+            },
             "sections": [
                 {
                     "law": {
@@ -1200,7 +1332,20 @@ const entries = [
                 null,
                 null,
                 null
-            ]
+            ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8"
+                ],
+                "source": "TI SLOS076 TL022C D/P package TOP VIEW (popular dual pinout): 1OUT-1, 1IN-minus-2, 2OUT-7, VCC-8 with 1IN-plus-3, GND-4, 2IN-plus-5, 2IN-minus-6"
+            }
         }
     },
     // Harris CA1458, in "CA741, CA741C, CA1458, CA1558, LM741, LM741C, LM1458, LM1558 - High Gain
@@ -2611,6 +2756,34 @@ const entries = [
                 "lpf1out",
                 "lpf1in"
             ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8",
+                    "9",
+                    "10",
+                    "11",
+                    "12",
+                    "13",
+                    "14",
+                    "15",
+                    "16"
+                ],
+                "source": "Princeton PT2399 datasheet V1.9 (Mar 2022) PIN DESCRIPTION p3: " +
+                    "1 VCC, 2 REF, 3 AGND, 4 DGND, 5 CLK_O, 6 VCO, 7 CC1, 8 CC0, " +
+                    "9 OP1-OUT, 10 OP1-IN, 11 OP2-IN, 12 OP2-OUT, 13 LPF2-IN, " +
+                    "14 LPF2-OUT, 15 LPF1-OUT, 16 LPF1-IN; PIN CONFIGURATION figure p3 " +
+                    "shows the same order (left 1-8 VCC..CC0, right 16-9 LPF1-IN..OP1-OUT); " +
+                    "ORDER INFORMATION p3 covers PT2399 (16-pin DIP 300mil), PT2399S " +
+                    "(16-pin SOP 300mil) and PT2399-SN (16-pin SOP 150mil) under the " +
+                    "one configuration"
+            },
             "sections": [
                 {
                     "law": {
@@ -3562,11 +3735,82 @@ const entries = [
     // registry-data record (`registry-data/opamp.ts`), which types the printed +-12.8 V (RL = 2 kOhm, VS = +-15 V)
     // as a `proportional` pair for OP07CP, OP07DP and OP07DN, and lists the bare `OP07` id absent (the
     // sheet's characteristics apply to the C and D grades only).
+    // The pin table below is cited per id: the bare OP07 from the ADI OP07 Rev. G sheet (family
+    // title; epoxy 8-lead PDIP), OP07CP/OP07DP from TI SLOS099H (PDIP orderables in the
+    // addendum, DIP pinout in Table 5-1). OP07DN is printed in no quotable sheet and rides
+    // the table-less entry after this one.
     {
         "partIds": [
             "OP07",
             "OP07CP",
-            "OP07DP",
+            "OP07DP"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "vin+",
+                "in+",
+                "pin3"
+            ],
+            [
+                "vin-",
+                "in-",
+                "pin2"
+            ],
+            [
+                "vout",
+                "out",
+                "pin6"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 100000
+                    },
+                    "terminals": [
+                        0,
+                        1,
+                        2
+                    ]
+                }
+            ],
+            "pinout": [
+                "vin+",
+                "vin-",
+                "vout"
+            ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "3",
+                    "2",
+                    "6"
+                ],
+                "packagePins": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8"
+                ],
+                "source": "ADI OP07 Rev. G (2002-2011) PIN CONFIGURATION Figure 1 p1: VOS TRIM 1, -IN 2, +IN 3, V- 4, NC 5, OUT 6, V+ 7, VOS TRIM 8 (epoxy 8-lead PDIP; family title OP07); TI SLOS099H Rev. H (Sept 1983, rev Mar 2023) Table 5-1 Pin Functions p3: IN+ 3, IN- 2, OUT 6, V- 4, V+ 7 (OFFSET N1 1, N2 8, NC 5) + Package Option Addendum p12: OP07CP, OP07DP PDIP (P) 8"
+            }
+        }
+    },
+    // OP07DN: same law data as the entry above, verbatim, but no pin table. OP07DN is printed
+    // in no sheet quotable here (TI SLOS099H Rev. H names OP07CP and OP07DP in its addendum
+    // but not OP07DN; the ADI Rev. G sheet grades are E and C only), so no table may claim
+    // it. A numbered OP07DN package keeps refusing, exactly as before.
+    {
+        "partIds": [
             "OP07DN"
         ],
         "declaredTypes": [],
@@ -3617,19 +3861,23 @@ const entries = [
     // 'LM741CN/NOPB | Active | Production | PDIP (P) | 8', part marking 'LM 741CN'.
     // The specs sit under the LM741C column family; open-loop gain stays the house
     // 100000 and no GBW row is quoted (see opampGainBandwidthAbsent).
+    // The pin table below is cited per id: LM741 and LM741CN from the National LM741
+    // Aug 2000 DS009341 Dual-In-Line diagram (caption names LM741J/LM741J/883/LM741CN);
+    // TL071 from ST TL071 Sept 2008 Rev 3 (N DIP8); TL071CP from TI SLOS080W Rev. W
+    // Table 4-1 (P PDIP column) plus the p36 addendum orderable; NJM5534D/NJM5534M from
+    // the NJR NJM5534 sheet (JRC databook folio 4-235; shared D/M diagram); NE5534 from
+    // TI SLOS070D Rev. D Pin Functions (P PDIP). UA741, uA741, TL071CN, bare NJM5534 and
+    // JRC5534 are printed on no quotable sheet and ride the table-less entry after this
+    // one. All tables agree: signal pins 2/3/6 of the 8-pin DIP; aux pins (offset null,
+    // balance, compensation, NC) stay unmodelled, exactly as for role-named documents.
     {
         "partIds": [
             "LM741",
-            "UA741",
-            "uA741",
             "TL071",
             "TL071CP",
-            "TL071CN",
-            "NJM5534",
             "NJM5534D",
             "NE5534",
             "NJM5534M",
-            "JRC5534",
             "LM741CN"
         ],
         "declaredTypes": [],
@@ -3650,6 +3898,79 @@ const entries = [
                 "pin6"
             ]
         ],
+        "model": {
+            "kind": "sections",
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 100000
+                    },
+                    "terminals": [
+                        0,
+                        1,
+                        2
+                    ]
+                }
+            ],
+            "pinout": [
+                "vin+",
+                "vin-",
+                "vout"
+            ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "3",
+                    "2",
+                    "6"
+                ],
+                "packagePins": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8"
+                ],
+                "source": "National LM741 Aug 2000 DS009341 Connection Diagrams Dual-In-Line (Order Number LM741J, LM741J/883, LM741CN) p1: 1 OFFSET NULL, 2 INVERTING INPUT, 3 NON-INVERTING INPUT, 4 V-, 5 OFFSET NULL, 6 OUTPUT, 7 V+, 8 NC; ST TL071 Sept 2008 Rev 3 Pin connections Top view N DIP8 p1: 1 Offset null 1, 2 Inverting input, 3 Non-inverting input, 4 VCC-, 5 Offset null 2, 6 Output, 7 VCC+, 8 N.C.; TI SLOS080W Rev. W Table 4-1 Pin Functions TL071x P PDIP column p3: IN- 2, IN+ 3, OUT 6, VCC- 4, VCC+ 7 (NC 1, 5, 8) + Addendum p36: TL071CP PDIP (P) 8; NJR NJM5534 (JRC databook folio 4-235) PIN CONFIGURATION NJM5534D/NJM5534M + PIN FUNCTION: 1 BALANCE, 2 -INPUT, 3 +INPUT, 4 V-, 5 COMPENSATION, 6 OUTPUT, 7 V+, 8 BALANCE/COMPENSATION; TI SLOS070D Rev. D Pin Functions p3 (P PDIP): BALANCE 1, IN- 2, IN+ 3, VCC- 4, COMP 5, OUT 6, VCC+ 7, COMP/BAL 8 (title ids NE5534/SA5534)"
+            }
+        }
+    },
+    // Single-op-amp ids with no quotable pin sheet: UA741/uA741 (no uA741-family sheet on
+    // this box), TL071CN (printed nowhere in TI SLOS080W), bare NJM5534 (the NJR sheet's
+    // diagram names only NJM5534D/NJM5534M) and JRC5534 (no owner decision extends the
+    // JRC4558D marking precedent to it). Same law data as the entry above, verbatim, but
+    // no table: a numbered package of these ids keeps refusing, exactly as before.
+    {
+        "partIds": [
+            "UA741",
+            "uA741",
+            "TL071CN",
+            "NJM5534",
+            "JRC5534"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "vin+",
+                "in+",
+                "pin3"
+            ],
+            [
+                "vin-",
+                "in-",
+                "pin2"
+            ],
+            [
+                "vout",
+                "out",
+                "pin6"
+            ]
+        ],
         "model": {
             "kind": "sections",
             "sections": [
@@ -3947,7 +4268,12 @@ const entries = [
             "CD4013",
             "CD4013BE",
             "uPD4013C",
-            "CD4013B"
+            "CD4013B",
+            // Motorola second source, same 4013 die: `boss-oc-2` IC6/IC7 are marked
+            // MC14013BCP on the Taiwan 1999 specimen (same precedent as SCL4013A
+            // riding the shared 4013 entry below).
+            "MC14013BCP",
+            "MC14013B"
         ],
         "declaredTypes": [],
         "terminalRoleGroups": [],
@@ -3955,26 +4281,40 @@ const entries = [
             "kind": "sections",
             "sections": [
                 {
+                    // One D-type flip-flop with asynchronous set/reset (4013 pin
+                    // order: 1 Q1, 2 Q1-bar, 3 CLOCK1, 4 RESET1, 5 DATA1, 6 SET1,
+                    // 7 VSS, 8 SET2, 9 DATA2, 10 RESET2, 11 CLOCK2, 12 Q2-bar,
+                    // 13 Q2, 14 VDD). Section terminals are pin indices in
+                    // canonical law order: clock, d, set, reset, q, q_bar, vdd,
+                    // vss. The supply pins ride the stamp so the output high and
+                    // the input threshold follow the pedal's own supply instead
+                    // of a constant.
                     "law": {
-                        "kind": "logic-divider",
-                        "thresholdVolts": 2,
-                        "highVolts": 5
+                        "kind": "d-flip-flop"
                     },
                     "terminals": [
                         2,
+                        4,
+                        5,
+                        3,
                         0,
+                        1,
+                        13,
                         6
                     ]
                 },
                 {
                     "law": {
-                        "kind": "logic-divider",
-                        "thresholdVolts": 2,
-                        "highVolts": 5
+                        "kind": "d-flip-flop"
                     },
                     "terminals": [
                         10,
+                        8,
+                        7,
+                        9,
                         12,
+                        11,
+                        13,
                         6
                     ]
                 }
@@ -3988,8 +4328,9 @@ const entries = [
                 "1set",
                 "gnd",
                 "2set",
-                "2reset",
+                // Pin order verified against the CD4013B datasheet (TI CD4013B, ON MC14013B: 1 Q1, 2 Q1-bar, 3 CLOCK1, 4 RESET1, 5 DATA1, 6 SET1, 7 VSS, 8 SET2, 9 DATA2, 10 RESET2, 11 CLOCK2, 12 Q2-bar, 13 Q2, 14 VDD). Positions 9 and 10 were transposed here; fixed 2026-10-26 because boss-oc-2 drives exactly that pair (D2 low at pin 9, R2 via R35 at pin 10).
                 "2data",
+                "2reset",
                 "2clock",
                 "2q_bar",
                 "2q",
@@ -5940,6 +6281,115 @@ const entries = [
             ]
         }
     },
+    // --- MC33178 dual 8-pin package entry (MXR Badass Modified U1, ARM overdrive U2) -----------
+    //
+    // The entry above stays untouched: it serves the mxr-carbon-copy per-half 5-terminal
+    // splits. This second entry carries the same ids with the 8-pin dual pinout, so
+    // `registryEntryFor` picks it for 8-terminal documents (pinout length 8) and the old
+    // entry for the 5-terminal ones. The MXRmod U2A 4-terminal declined split is out of
+    // scope and keeps refusing.
+    // From the Motorola MC33178/D Rev 0 (1996) sheet: PIN CONNECTIONS DUAL P SUFFIX
+    // PLASTIC PACKAGE CASE 626 / D SUFFIX PLASTIC PACKAGE CASE 751 (Top View), p1:
+    // 1 Output 1, 2-3 Inputs 1, 4 VEE, 5-6 Inputs 2, 7 Output 2, 8 VCC. The ORDERING
+    // INFORMATION prints MC33178D (SO-8) and MC33178P (Plastic DIP); the bare MC33178 is
+    // the family root in the title -- one dual pinout for all three ids.
+    // Law: OPEN-LOOP gain from the sheet's own DC ELECTRICAL CHARACTERISTICS table p2
+    // (VCC = +15 V, VEE = -15 V, TA = 25C): 'Large Signal Voltage Gain (VO = -10 V to
+    // +10 V, RL = 600 Ohm) AVOL, TA = +25C: MIN 50k TYP 200k' -- used as
+    // `openLoopGain: 200000`, NOT the old entry's unsourced 100000. GBW and swing stay
+    // untyped although the sheet prints TYP figures (AC table p3: GBW MIN 2.5 TYP 5.0 MHz;
+    // DC table p2: VO+ TYP +12 V / VO- TYP -12 V at RL = 300 Ohm, VCC = +15 V, VEE = -15 V):
+    // the three ids are shared with the 5-terminal entry, so registry typing would restamp
+    // mxr-carbon-copy's halves and move a canonical packet. The ids already sit in
+    // `opampGainBandwidthAbsent` / `opampOutputSwingAbsent`, left byte-identical here.
+    {
+        "partIds": [
+            "MC33178",
+            "MC33178P",
+            "MC33178D"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "OUT_A_pin1"
+            ],
+            [
+                "INVERTING_A_pin2"
+            ],
+            [
+                "NONINVERTING_A_pin3"
+            ],
+            [
+                "V_MINUS_pin4"
+            ],
+            [
+                "NONINVERTING_B_pin5"
+            ],
+            [
+                "INVERTING_B_pin6"
+            ],
+            [
+                "OUT_B_pin7"
+            ],
+            [
+                "V_PLUS_pin8"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "pinout": [
+                "OUT_A",
+                "IN_A_MINUS",
+                "IN_A_PLUS",
+                "VEE",
+                "IN_B_PLUS",
+                "IN_B_MINUS",
+                "OUT_B",
+                "VCC"
+            ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8"
+                ],
+                "source": "Motorola MC33178/D Rev 0 (1996) PIN CONNECTIONS DUAL P SUFFIX PLASTIC PACKAGE CASE 626 / D SUFFIX PLASTIC PACKAGE CASE 751 (Top View) p1: 1 Output 1, 2 Inputs 1 -, 3 Inputs 1 +, 4 VEE, 5 Inputs 2 +, 6 Inputs 2 -, 7 Output 2, 8 VCC"
+            },
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 200000
+                    },
+                    "terminals": [
+                        2,
+                        1,
+                        0
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 200000
+                    },
+                    "terminals": [
+                        4,
+                        5,
+                        6
+                    ]
+                }
+            ]
+        }
+    },
     // --- RCA/TI CD4047 gatable astable multivibrator, BBD clock (mxr-carbon-copy) ------------------
     //
     // `mxr-carbon-copy.vdsp`'s U6 declares 14 terminals in strict pin order with the CD4047's
@@ -6016,26 +6466,40 @@ const entries = [
             "kind": "sections",
             "sections": [
                 {
+                    // One D-type flip-flop with asynchronous set/reset (4013 pin
+                    // order: 1 Q1, 2 Q1-bar, 3 CLOCK1, 4 RESET1, 5 DATA1, 6 SET1,
+                    // 7 VSS, 8 SET2, 9 DATA2, 10 RESET2, 11 CLOCK2, 12 Q2-bar,
+                    // 13 Q2, 14 VDD). Section terminals are pin indices in
+                    // canonical law order: clock, d, set, reset, q, q_bar, vdd,
+                    // vss. The supply pins ride the stamp so the output high and
+                    // the input threshold follow the pedal's own supply instead
+                    // of a constant.
                     "law": {
-                        "kind": "logic-divider",
-                        "thresholdVolts": 2,
-                        "highVolts": 5
+                        "kind": "d-flip-flop"
                     },
                     "terminals": [
                         2,
+                        4,
+                        5,
+                        3,
                         0,
+                        1,
+                        13,
                         6
                     ]
                 },
                 {
                     "law": {
-                        "kind": "logic-divider",
-                        "thresholdVolts": 2,
-                        "highVolts": 5
+                        "kind": "d-flip-flop"
                     },
                     "terminals": [
                         10,
+                        8,
+                        7,
+                        9,
                         12,
+                        11,
+                        13,
                         6
                     ]
                 }
@@ -6083,26 +6547,37 @@ const entries = [
             "kind": "sections",
             "sections": [
                 {
+                    // Same D-type flip-flop law; indices are in this entry's
+                    // section-order pinout (1Q, 1QBAR, 1CLK, 1D, 1RESET, 1SET,
+                    // 2Q, 2QBAR, 2CLK, 2D, 2RESET, 2SET, VDD, VSS), still in
+                    // canonical law order: clock, d, set, reset, q, q_bar,
+                    // vdd, vss.
                     "law": {
-                        "kind": "logic-divider",
-                        "thresholdVolts": 2,
-                        "highVolts": 5
+                        "kind": "d-flip-flop"
                     },
                     "terminals": [
                         2,
+                        3,
+                        5,
+                        4,
                         0,
+                        1,
+                        12,
                         13
                     ]
                 },
                 {
                     "law": {
-                        "kind": "logic-divider",
-                        "thresholdVolts": 2,
-                        "highVolts": 5
+                        "kind": "d-flip-flop"
                     },
                     "terminals": [
                         8,
-                        6,
+                        9,
+                        11,
+                        10,
+                        6,
+                        7,
+                        12,
                         13
                     ]
                 }
@@ -7258,6 +7733,19 @@ const entries = [
                 "OUT_B",
                 "VCC"
             ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8"
+                ],
+                "source": "TI SLOS481B Pin Functions table p3 (D/SOIC, DGK/MSOP, P/PDIP): 1 OUT1, 2 IN1-minus, 3 IN1-plus, 4 VCC-minus, 5 IN2-plus, 6 IN2-minus, 7 OUT2, 8 VCC-plus"
+            },
             "sections": [
                 {
                     "law": {
@@ -7307,11 +7795,15 @@ const entries = [
     // 2026-10-15: the NJR/JRC marking rides the NJM sheet). GBW is not in this entry: it
     // lives in the data-registry row (TYP 15 MHz at f = 10 kHz), stamped by the pass below.
     {
+        // Wave 8: the bare transcribed number-portion "4580" (Azusa Driver U2, 8 pins)
+        // rides this entry (same die family per the owner JRC-rides-NJM decision above);
+        // it carries no GBW figure (see `opampGainBandwidthAbsent`).
         "partIds": [
             "JRC4580D",
             "JRC4580",
             "NJM4580D",
-            "NJM4580"
+            "NJM4580",
+            "4580"
         ],
         "declaredTypes": [],
         "terminalRoleGroups": [
@@ -7352,6 +7844,19 @@ const entries = [
                 "OUT_B",
                 "VCC"
             ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8"
+                ],
+                "source": "NJR NJM4580D sheet Ver.2012-09-14 PIN FUNCTION table p1 (DIP-8 TOP VIEW): 1 A OUTPUT, 2 A -INPUT, 3 A +INPUT, 4 V-, 5 B +INPUT, 6 B -INPUT, 7 B OUTPUT, 8 V+"
+            },
             "sections": [
                 {
                     "law": {
@@ -7438,6 +7943,19 @@ const entries = [
                 "OUT_B",
                 "VCC"
             ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8"
+                ],
+                "source": "TI SBOS058B Table 4-1 Pin Functions OPA2134 p3 (D/SOIC and P/PDIP, Fig. 4-2): OUT A-1, -IN A-2, +IN A-3, V-minus-4, +IN B-5, -IN B-6, OUT B-7, V-plus-8"
+            },
             "sections": [
                 {
                     "law": {
@@ -7528,6 +8046,19 @@ const entries = [
                 "OUT_B",
                 "VCC"
             ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8"
+                ],
+                "source": "TI SNOSBU4D Fig. 2 Connection Diagram Dual-In-Line Package (Top View) p1: 1 OUTPUT A, 2 INVERTING INPUT A, 3 NON-INVERTING INPUT A, 4 V-, 5 NON-INVERTING INPUT B, 6 INVERTING INPUT B, 7 OUTPUT B, 8 V+"
+            },
             "sections": [
                 {
                     "law": {
@@ -7694,6 +8225,25 @@ const entries = [
                 "IN_D_MINUS",
                 "OUT_D"
             ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8",
+                    "9",
+                    "10",
+                    "11",
+                    "12",
+                    "13",
+                    "14"
+                ],
+                "source": "TI SLOS066AE Table 5-1 Pin Functions N (PDIP) p3, standard quad order: 1OUT-1, 1IN-minus-2, 1IN-plus-3, VCC-plus-4, 2IN-plus-5, 2IN-minus-6, 2OUT-7, 3OUT-8, 3IN-minus-9, 3IN-plus-10, VCC-minus-11, 4IN-plus-12, 4IN-minus-13, 4OUT-14"
+            },
             "sections": [
                 {
                     "law": {
@@ -7816,8 +8366,11 @@ const entries = [
     // (1OUT, 1IN-, 1IN+, VDD-/GND, 2IN+, 2IN-, 2OUT, VDD+), same A/B convention as the
     // LM833 entry above.
     {
+        // Wave 8: the C-suffix spelling rides here -- the quoted table IS the TLC2262C
+        // operating characteristics (MXR Badass 78 U2). Same row as the GBW alias.
         "partIds": [
-            "TLC2262"
+            "TLC2262",
+            "TLC2262C"
         ],
         "declaredTypes": [],
         "terminalRoleGroups": [
@@ -7858,6 +8411,19 @@ const entries = [
                 "OUT_B",
                 "VCC"
             ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8"
+                ],
+                "source": "TI SLOS177D (Feb 1997, rev Mar 2001) TLC2262C D, P, or PW PACKAGE (TOP VIEW) p3: 1 1OUT, 2 1IN-, 3 1IN+, 4 VDD-/GND, 5 2IN+, 6 2IN-, 7 2OUT, 8 VDD+"
+            },
             "sections": [
                 {
                     "law": {
@@ -7963,6 +8529,25 @@ const entries = [
                 "IN_D_MINUS",
                 "OUT_D"
             ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8",
+                    "9",
+                    "10",
+                    "11",
+                    "12",
+                    "13",
+                    "14"
+                ],
+                "source": "onsemi MC33171/D Rev.14 PIN CONNECTIONS quad diagram p2 incl. PDIP-14, standard quad order: Output 1-1, Inputs 1, VCC, Inputs 2, Output 2, Output 3, Inputs 3, VEE, Inputs 4, Output 4"
+            },
             "sections": [
                 {
                     "law": {
@@ -8073,6 +8658,19 @@ const entries = [
                 "OUT_B",
                 "VCC"
             ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8"
+                ],
+                "source": "TI SLOS080W Table 4-3 Pin Functions TL072x: 1OUT-1, 1IN-minus-2, 1IN-plus-3, VCC-minus-4, 2IN-plus-5, 2IN-minus-6, 2OUT-7, VCC-plus-8"
+            },
             "sections": [
                 {
                     "law": {
@@ -8153,6 +8751,19 @@ const entries = [
                 "OUT_B",
                 "VCC"
             ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8"
+                ],
+                "source": "TI SBOS855E section 5 Pin Functions OPA1678: OUT A-1, -IN A-2, +IN A-3, V-minus-4, +IN B-5, -IN B-6, OUT B-7, V-plus-8"
+            },
             "sections": [
                 {
                     "law": {
@@ -8297,14 +8908,17 @@ const entries = [
     // transcribed (the gain-bandwidth product lives in `registry-data/opamp.ts`, stamped by
     // the passes below; the swing pair stays absent per the D4 freeze). GBW rows and catalog
     // entries are 1:1 by part id, so no entry splits.
-    // ADI AD712 dual precision BiFET op-amp, from the ADI AD712 datasheet Rev. B
-    // (SPECIFICATIONS at VS = +-15 V @ TA = +25C): OPEN-LOOP GAIN MIN 150 TYP 400 V/mV
-    // (J/A/S grades; K/B/T and C print MIN 200 TYP 400 -- TYP 400 in every grade, so the
-    // bare id carries it). Used as `openLoopGain: 400000`. The sheet's frequency row reads
+    // ADI AD712 dual precision BiFET op-amp, from the ADI AD712 datasheet Rev. I
+    // (SPECIFICATIONS at VS = +-15 V @ TA = +25C, p4): OPEN-LOOP GAIN
+    // VOUT = -10 V to +10 V: MIN 150 TYP 400 V/mV (first grade group) and MIN 200
+    // TYP 400 (second group) -- TYP 400 in every grade, so the bare id carries it. Used as `openLoopGain: 400000`. The sheet's frequency row reads
     // 'Small Signal Bandwidth 3.0 MIN 4.0 TYP MHz' with no closed-loop gain stated and never
     // uses the term gain-bandwidth, so no GBW figure is transcribed (see
-    // `opampGainBandwidthAbsent`). Pinout: 'pinned out in a standard op amp configuration'
-    // (dual DIP-8 order, same pin-numbered role convention as the LM833 entry above).
+    // `opampGainBandwidthAbsent`). Pinout: the CONNECTION DIAGRAM Figure 1 below (AMP
+    // NO. 1: 1 OUTPUT, 2 INVERTING, 3 NONINVERTING; AMP NO. 2: 5 NONINVERTING,
+    // 6 INVERTING, 7 OUTPUT; 4 V-, 8 V+) covers the 8-Lead PDIP (N), SOIC_N (R) and
+    // CERDIP (Q) packages with one diagram -- grades differ in specs, not in the package.
+    // The bare AD712 is the family name in the sheet title.
     {
         "partIds": [
             "AD712"
@@ -8348,6 +8962,19 @@ const entries = [
                 "OUT_B",
                 "VCC"
             ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8"
+                ],
+                "source": "ADI AD712 datasheet Rev. I (1986-2018) CONNECTION DIAGRAM Figure 1 (8-Lead PDIP N-Suffix, SOIC_N R-Suffix, CERDIP Q-Suffix) p1: 1 OUTPUT, 2 INVERTING INPUT, 3 NONINVERTING INPUT, 4 V-, 5 NONINVERTING INPUT, 6 INVERTING INPUT, 7 OUTPUT, 8 V+"
+            },
             "sections": [
                 {
                     "law": {
@@ -8452,6 +9079,25 @@ const entries = [
                 "IN_D_MINUS",
                 "OUT_D"
             ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8",
+                    "9",
+                    "10",
+                    "11",
+                    "12",
+                    "13",
+                    "14"
+                ],
+                "source": "TI SLOS013C Pin Functions table, standard quad order: 1OUT-1, 1IN-minus-2, 1IN-plus-3, VCC-plus-4, 2IN-plus-5, 2IN-minus-6, 2OUT-7, 3OUT-8, 3IN-minus-9, 3IN-plus-10, VCC-minus-11, 4IN-plus-12, 4IN-minus-13, 4OUT-14"
+            },
             "sections": [
                 {
                     "law": {
@@ -8696,6 +9342,25 @@ const entries = [
                 "IN_D_MINUS",
                 "OUT_D"
             ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8",
+                    "9",
+                    "10",
+                    "11",
+                    "12",
+                    "13",
+                    "14"
+                ],
+                "source": "TI SLOS080W Table 4-6 Pin Functions TL074x, standard quad order: 1OUT-1, 1IN-minus-2, 1IN-plus-3, VCC-plus-4, 2IN-plus-5, 2IN-minus-6, 2OUT-7, 3OUT-8, 3IN-minus-9, 3IN-plus-10, VCC-minus-11, 4IN-plus-12, 4IN-minus-13, 4OUT-14"
+            },
             "sections": [
                 {
                     "law": {
@@ -8942,6 +9607,504 @@ const entries = [
             ]
         }
     },
+    // Wave 8 (opamp batch, corpus-driven): sections whose open-loop gain is the sheet's
+    // own TYP AOL transcribed (the gain-bandwidth product lives in
+    // `registry-data/opamp.ts`, stamped by the passes below; the swing pair stays absent
+    // per the D4 freeze). GBW rows and catalog entries are 1:1 by part id, so no entry
+    // splits; AOL-only and generic-name ids below carry sections with no GBW row.
+    // TI TL081 single JFET-input op-amp, from SLOS081O (Feb 1977, rev Sept 2025) 5.8 DC:
+    // 'AOL | Open-loop voltage | VO = 0 V | TL08xC | MIN 25 TYP 200 V/mV'. Used as
+    // `openLoopGain: 200000` (bare id takes the commercial C-grade column, disclosed;
+    // TL072C precedent). No GBW figure (package/grade split; see
+    // `opampGainBandwidthAbsent`). Single-DIP shape mirrors the LM741/TL071 entry.
+    // Pin table from the ST TL081 sheet below (June 2008 Rev 3): signal pins 2/3/6 of
+    // the 8-pin DIP; offset-null pins and NC stay unmodelled.
+    {
+        "partIds": [
+            "TL081"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "vin+",
+                "in+",
+                "pin3"
+            ],
+            [
+                "vin-",
+                "in-",
+                "pin2"
+            ],
+            [
+                "vout",
+                "out",
+                "pin6"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 200000
+                    },
+                    "terminals": [
+                        0,
+                        1,
+                        2
+                    ]
+                }
+            ],
+            "pinout": [
+                "vin+",
+                "vin-",
+                "vout"
+            ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "3",
+                    "2",
+                    "6"
+                ],
+                "packagePins": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8"
+                ],
+                "source": "ST TL081 June 2008 Rev 3 Pin connections (top view) N DIP8 p1: 1 Offset null 1, 2 Inverting input, 3 Non-inverting input, 4 VCC-, 5 Offset null 2, 6 Output, 7 VCC+, 8 N.C. (title covers TL081, TL081A, TL081B)"
+            }
+        }
+    },
+    // TI MC1458P dual general-purpose op-amp, from SLOS069C (Feb 1971, rev Aug 2010),
+    // electrical characteristics at VCC+- = +-15 V: 'Large-signal differential voltage
+    // amplification, RL >= 2 kOhm, VO = +-10 V, 25C: MIN 20 (MC1458) / 50 (MC1558) TYP 200
+    // V/mV'. Used as `openLoopGain: 200000` (both grades share the TYP). MC1458P is the
+    // PDIP orderable named on the title block. GBW TYP 1 MHz lives in the data-registry row.
+    {
+        "partIds": [
+            "MC1458P"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "OUT_A_pin1"
+            ],
+            [
+                "INVERTING_A_pin2"
+            ],
+            [
+                "NONINVERTING_A_pin3"
+            ],
+            [
+                "V_MINUS_pin4"
+            ],
+            [
+                "NONINVERTING_B_pin5"
+            ],
+            [
+                "INVERTING_B_pin6"
+            ],
+            [
+                "OUT_B_pin7"
+            ],
+            [
+                "V_PLUS_pin8"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "pinout": [
+                "OUT_A",
+                "IN_A_MINUS",
+                "IN_A_PLUS",
+                "VEE",
+                "IN_B_PLUS",
+                "IN_B_MINUS",
+                "OUT_B",
+                "VCC"
+            ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8"
+                ],
+                "source": "TI SLOS069C (Feb 1971, rev Aug 2010) MC1458 D, P, or PS PACKAGE (TOP VIEW) p1: 1 1OUT, 2 1IN-, 3 1IN+, 4 VCC-, 5 2IN+, 6 2IN-, 7 2OUT, 8 VCC+"
+            },
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 200000
+                    },
+                    "terminals": [
+                        2,
+                        1,
+                        0
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 200000
+                    },
+                    "terminals": [
+                        4,
+                        5,
+                        6
+                    ]
+                }
+            ]
+        }
+    },
+    // Renesas CA3240EZ dual BiMOS op-amp, from FN1050 Rev 6.00 (Mar 2005) guaranteed table
+    // (VSUPPLY = +-15 V, TA = 25C): 'Large-Signal Voltage Gain AOL, VO = 26VP-P, RL = 2 kOhm
+    // (Note 3): MIN 20 TYP 100 kV/V' both grades. Used as `openLoopGain: 100000`. CA3240EZ
+    // is the 8 Ld PDIP orderable. GBW TYP 4.5 MHz lives in the data-registry row.
+    {
+        "partIds": [
+            "CA3240EZ"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "OUT_A_pin1"
+            ],
+            [
+                "INVERTING_A_pin2"
+            ],
+            [
+                "NONINVERTING_A_pin3"
+            ],
+            [
+                "V_MINUS_pin4"
+            ],
+            [
+                "NONINVERTING_B_pin5"
+            ],
+            [
+                "INVERTING_B_pin6"
+            ],
+            [
+                "OUT_B_pin7"
+            ],
+            [
+                "V_PLUS_pin8"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "pinout": [
+                "OUT_A",
+                "IN_A_MINUS",
+                "IN_A_PLUS",
+                "VEE",
+                "IN_B_PLUS",
+                "IN_B_MINUS",
+                "OUT_B",
+                "VCC"
+            ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8"
+                ],
+                "source": "Renesas FN1050 Rev 6.00 (Mar 4, 2005) Pinout CA3240, CA3240A (PDIP) TOP VIEW p1: 1 OUTPUT (A), 2 INV. INPUT (A), 3 NON-INV. INPUT (A), 4 V-, 5 NON-INV. INPUT (B), 6 INV. INPUT (B), 7 OUTPUT (B), 8 V+"
+            },
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 100000
+                    },
+                    "terminals": [
+                        2,
+                        1,
+                        0
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 100000
+                    },
+                    "terminals": [
+                        4,
+                        5,
+                        6
+                    ]
+                }
+            ]
+        }
+    },
+    // ON Semi LM301AN single non-compensated op-amp, from LM301A/D Rev. 12 (July 2025)
+    // ELECTRICAL CHARACTERISTICS (TA = +25C; LM301A column, +-5 to +-15 V supply range):
+    // 'Large Signal Voltage Gain AV: MIN 50 (LM201A) / 25 (LM301A) TYP 160 V/mV' both grades
+    // share the TYP. Used as `openLoopGain: 160000`. LM301AN is the PDIP-8 orderable. No GBW
+    // row exists (see `opampGainBandwidthAbsent`; same AOL-only shape as LM308).
+    // Single-DIP shape mirrors the LM741/TL071 entry. Pin table: the onsemi PIN
+    // CONNECTIONS prints pins 1 Balance, 2-3 Inputs, 4 VEE, 5 Balance, 6 Output, 7 VCC,
+    // 8 Compensation with the PDIP-8 N marking LMx01AN (x = 2 or 3); the 2/3 polarity
+    // (2 inverting, 3 non-inverting) is read off TI SNOSBS0D Fig. 49 (CDIP/PDIP). Balance,
+    // compensation and NC stay unmodelled.
+    {
+        "partIds": [
+            "LM301AN"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "vin+",
+                "in+",
+                "pin3"
+            ],
+            [
+                "vin-",
+                "in-",
+                "pin2"
+            ],
+            [
+                "vout",
+                "out",
+                "pin6"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 160000
+                    },
+                    "terminals": [
+                        0,
+                        1,
+                        2
+                    ]
+                }
+            ],
+            "pinout": [
+                "vin+",
+                "vin-",
+                "vout"
+            ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "3",
+                    "2",
+                    "6"
+                ],
+                "packagePins": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8"
+                ],
+                "source": "onsemi LM301A/D Rev. 12 (July 2025) PIN CONNECTIONS (Top View) p1: 1 Balance, 2 Inputs, 3 Inputs, 4 VEE, 5 Balance, 6 Output, 7 VCC, 8 Compensation (PDIP-8 N SUFFIX CASE 626 marking LMx01AN, x = 2 or 3); TI SNOSBS0D (Sept 1979, rev Mar 2013) Figure 49 CDIP and PDIP Packages p17: 1 BALANCE/COMPENSATION, 2 INPUT (-), 3 INPUT (+), 4 V-, 5 BALANCE, 6 OUTPUT, 7 V+, 8 COMPENSATION"
+            }
+        }
+    },
+    // Renesas CA3130EZ single BiMOS op-amp, from FN817 Rev 6.00 (Aug 2005) Table 1
+    // (TA = 25C, V+ = 15 V, V- = 0 V): 'Large-Signal Voltage Gain AOL, VO = 10VP-P, RL = 2
+    // kOhm: MIN 50 TYP 320 kV/V' both grades. Used as `openLoopGain: 320000`. CA3130EZ is
+    // the 8 Ld PDIP orderable. No GBW figure (compensation-dependent fT; see
+    // `opampGainBandwidthAbsent`). Single-DIP shape mirrors the LM741/TL071 entry.
+    // Pin table from the same FN817 sheet: signal pins 2/3/6; offset-null pins and
+    // strobe stay unmodelled.
+    {
+        "partIds": [
+            "CA3130EZ"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "vin+",
+                "in+",
+                "pin3"
+            ],
+            [
+                "vin-",
+                "in-",
+                "pin2"
+            ],
+            [
+                "vout",
+                "out",
+                "pin6"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 320000
+                    },
+                    "terminals": [
+                        0,
+                        1,
+                        2
+                    ]
+                }
+            ],
+            "pinout": [
+                "vin+",
+                "vin-",
+                "vout"
+            ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "3",
+                    "2",
+                    "6"
+                ],
+                "packagePins": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8"
+                ],
+                "source": "Renesas FN817 Rev. 6.00 (Aug 1, 2005) Pinout CA3130, CA3130A (PDIP, SOIC) TOP VIEW p1: 1 OFFSET NULL, 2 INV. INPUT, 3 NON-INV. INPUT, 4 V-, 5 OFFSET NULL, 6 OUTPUT, 7 V+, 8 STROBE (Ordering Information: CA3130EZ 8 Ld PDIP)"
+            }
+        }
+    },
+    // Bare "4559" dual (Mojo Rook IC1, 8 pins): the JRC NJM4558/NJM4559 sheet below
+    // prints NJM4559D (DIP8) and NJM4559M (DMP8) under one shared Top View diagram with
+    // the PIN FUNCTION list transcribed in the table -- pin numbering identical for both
+    // (suffix is package). The bare "4559" id itself is NOT a printed orderable: it is the
+    // family number, carried the way the bare TLC2262 rides its family sheet. The SIP8
+    // NJM4559L uses a different diagram (excluded; the corpus doc is 8-terminal DIP 1..8).
+    // A Raytheon-marked 4559 is not covered by this JRC sheet. The sections carry the
+    // house 100000, disclosed as unsourced (TL062/LM741-single precedent), with no
+    // GBW figure (see `opampGainBandwidthAbsent`; same verdict as bare 4558). Standard dual
+    // order, same pin-numbered role convention as the NJM4580 entry.
+    {
+        "partIds": [
+            "4559"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "OUT_A_pin1"
+            ],
+            [
+                "INVERTING_A_pin2"
+            ],
+            [
+                "NONINVERTING_A_pin3"
+            ],
+            [
+                "V_MINUS_pin4"
+            ],
+            [
+                "NONINVERTING_B_pin5"
+            ],
+            [
+                "INVERTING_B_pin6"
+            ],
+            [
+                "OUT_B_pin7"
+            ],
+            [
+                "V_PLUS_pin8"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "pinout": [
+                "OUT_A",
+                "IN_A_MINUS",
+                "IN_A_PLUS",
+                "VEE",
+                "IN_B_PLUS",
+                "IN_B_MINUS",
+                "OUT_B",
+                "VCC"
+            ],
+            "packagePinNumbers": {
+                "numbers": [
+                    "1",
+                    "2",
+                    "3",
+                    "4",
+                    "5",
+                    "6",
+                    "7",
+                    "8"
+                ],
+                "source": "JRC NJM4558/NJM4559 Ver.2013-11-05 (New Japan Radio Co., Ltd.) PIN CONFIGURATION (Top View) + PIN FUNCTION p1: 1 A OUTPUT, 2 A -INPUT, 3 A +INPUT, 4 V-, 5 B +INPUT, 6 B -INPUT, 7 B OUTPUT, 8 V+"
+            },
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 100000
+                    },
+                    "terminals": [
+                        2,
+                        1,
+                        0
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 100000
+                    },
+                    "terminals": [
+                        4,
+                        5,
+                        6
+                    ]
+                }
+            ]
+        }
+    },
     ...zenerRegistryRecords.map((record) => zenerLaw(record)),
     // Wave-1 discrete fill: bjt, diode-forward, mosfet and jfet-channel records become
     // law entries through the builders above -- one list per class, so the entries cannot
@@ -8954,6 +10117,12 @@ const entries = [
     ...mosfetRegistryRecords.map((record) => fetLawEntry(record, "mosfet")),
     ...jfetRegistryRecords.map((record) => fetLawEntry(record, "jfet")),
     ...ujtRegistryRecords.map((record) => ujtLawEntry(record)),
+    // LM386-family fixed-gain power amps: the printed resistor networks plus the derived
+    // gain-bandwidth product become sections entries through the builder above -- one row
+    // per maker sheet, so the entries cannot drift from the records. Bare LM386 rides the
+    // TI row on the sheet's family title (owner ruling 2026-10-28); JRC386D rides the NJR row
+    // as the owner-decided marking of the NJM386D (2026-10-28; the sheet does not print it).
+    ...powerAmpRegistryRecords.map((record) => powerAmpEntry(record)),
 ];
 // --- Op-amp gain-bandwidth product: stamped from the data registry ------------------------------
 /**
@@ -9212,4 +10381,7 @@ export const gateOnlyFetPartIds = new Set(jfetRegistryRecords
 export const pedalPartCatalog = {
     entries: withDatasheetOutputSwing(withDatasheetGainBandwidth(entries)),
 };
+// A stated package pin table that is not a whole-digit bijection as long as its pinout would
+// bind packages wrongly rather than refuse them: loud at load, naming the entry.
+validatePackagePinNumbers(pedalPartCatalog.entries);
 //# sourceMappingURL=part-catalog.js.map