@vessel-dsp/compiler 0.16.0 → 0.18.0

package/dist/part-catalog.d.ts.map

@@ -1 +1 @@
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+{"version":3,"file":"part-catalog.d.ts","sourceRoot":"","sources":["../src/part-catalog.ts"],"names":[],"mappings":"AAsDA,OAAO,KAAK,EAAE,SAAS,EAAE,YAAY,EAAE,MAAM,YAAY,CAAC;AAG1D,OAAO,EAeN,KAAK,UAAU,EACf,KAAK,mBAAmB,EACxB,KAAK,aAAa,EAClB,MAAM,iBAAiB,CAAC;AACzB,OAAO,KAAK,EAAE,aAAa,EAAE,MAAM,wBAAwB,CAAC;AAI5D,OAAO,EACN,wBAAwB,EACxB,sBAAsB,EACtB,oBAAoB,EACpB,KAAK,mBAAmB,EACxB,KAAK,iBAAiB,GACtB,MAAM,iBAAiB,CAAC;AACzB,YAAY,EAAE,UAAU,EAAE,aAAa,EAAE,aAAa,EAAE,CAAC;AAoIzD,6FAA6F;AAC7F,wBAAgB,WAAW,CAAC,MAAM,EAAE,aAAa,GAAG,SAAS,CA+B5D;AAED;;;;;;GAMG;AACH,wBAAgB,aAAa,CAAC,MAAM,EAAE,aAAa,GAAG,SAAS,CAkC9D;AAED;;;;;;;;;;GAUG;AACH,wBAAgB,WAAW,CAAC,MAAM,EAAE,aAAa,GAAG,SAAS,CAkC5D;AAED;;;;;GAKG;AACH,wBAAgB,WAAW,CAC1B,MAAM,EAAE,aAAa,EACrB,GAAG,EAAE,MAAM,GAAG,QAAQ,GACpB,SAAS,CAkEX;AAED;;;;;GAKG;AACH,wBAAgB,WAAW,CAAC,MAAM,EAAE,aAAa,GAAG,SAAS,CA6B5D;AA+BD,eAAO,MAAM,mBAAmB,EAAE,WAAW,CAAC,MAAM,CAInD,CAAC;AAklSF;;;;;;;;;;GAUG;AACH,wBAAgB,wBAAwB,CACvC,IAAI,EAAE,SAAS,SAAS,EAAE,EAC1B,IAAI,GAAE,SAAS,mBAAmB,EAAyB,EAC3D,UAAU,GAAE,aAAa,CAAC;IAAE,QAAQ,CAAC,OAAO,EAAE,SAAS,MAAM,EAAE,CAAC;IAAC,QAAQ,CAAC,MAAM,EAAE,MAAM,CAAA;CAAE,CAA0B,GAClH,SAAS,SAAS,EAAE,CAgHtB;AAeD,eAAO,MAAM,kBAAkB,EAAE,WAAW,CAAC,MAAM,CAUlD,CAAC;AAEF;;GAEG;AACH,eAAO,MAAM,gBAAgB,EAAE,YAE9B,CAAC"}

package/dist/part-catalog.js

@@ -3947,7 +3947,12 @@ const entries = [
             "CD4013",
             "CD4013BE",
             "uPD4013C",
-            "CD4013B"
+            "CD4013B",
+            // Motorola second source, same 4013 die: `boss-oc-2` IC6/IC7 are marked
+            // MC14013BCP on the Taiwan 1999 specimen (same precedent as SCL4013A
+            // riding the shared 4013 entry below).
+            "MC14013BCP",
+            "MC14013B"
         ],
         "declaredTypes": [],
         "terminalRoleGroups": [],
@@ -3955,26 +3960,40 @@ const entries = [
             "kind": "sections",
             "sections": [
                 {
+                    // One D-type flip-flop with asynchronous set/reset (4013 pin
+                    // order: 1 Q1, 2 Q1-bar, 3 CLOCK1, 4 RESET1, 5 DATA1, 6 SET1,
+                    // 7 VSS, 8 SET2, 9 DATA2, 10 RESET2, 11 CLOCK2, 12 Q2-bar,
+                    // 13 Q2, 14 VDD). Section terminals are pin indices in
+                    // canonical law order: clock, d, set, reset, q, q_bar, vdd,
+                    // vss. The supply pins ride the stamp so the output high and
+                    // the input threshold follow the pedal's own supply instead
+                    // of a constant.
                     "law": {
-                        "kind": "logic-divider",
-                        "thresholdVolts": 2,
-                        "highVolts": 5
+                        "kind": "d-flip-flop"
                     },
                     "terminals": [
                         2,
+                        4,
+                        5,
+                        3,
                         0,
+                        1,
+                        13,
                         6
                     ]
                 },
                 {
                     "law": {
-                        "kind": "logic-divider",
-                        "thresholdVolts": 2,
-                        "highVolts": 5
+                        "kind": "d-flip-flop"
                     },
                     "terminals": [
                         10,
+                        8,
+                        7,
+                        9,
                         12,
+                        11,
+                        13,
                         6
                     ]
                 }
@@ -3988,8 +4007,9 @@ const entries = [
                 "1set",
                 "gnd",
                 "2set",
-                "2reset",
+                // Pin order verified against the CD4013B datasheet (TI CD4013B, ON MC14013B: 1 Q1, 2 Q1-bar, 3 CLOCK1, 4 RESET1, 5 DATA1, 6 SET1, 7 VSS, 8 SET2, 9 DATA2, 10 RESET2, 11 CLOCK2, 12 Q2-bar, 13 Q2, 14 VDD). Positions 9 and 10 were transposed here; fixed 2026-10-26 because boss-oc-2 drives exactly that pair (D2 low at pin 9, R2 via R35 at pin 10).
                 "2data",
+                "2reset",
                 "2clock",
                 "2q_bar",
                 "2q",
@@ -6016,26 +6036,40 @@ const entries = [
             "kind": "sections",
             "sections": [
                 {
+                    // One D-type flip-flop with asynchronous set/reset (4013 pin
+                    // order: 1 Q1, 2 Q1-bar, 3 CLOCK1, 4 RESET1, 5 DATA1, 6 SET1,
+                    // 7 VSS, 8 SET2, 9 DATA2, 10 RESET2, 11 CLOCK2, 12 Q2-bar,
+                    // 13 Q2, 14 VDD). Section terminals are pin indices in
+                    // canonical law order: clock, d, set, reset, q, q_bar, vdd,
+                    // vss. The supply pins ride the stamp so the output high and
+                    // the input threshold follow the pedal's own supply instead
+                    // of a constant.
                     "law": {
-                        "kind": "logic-divider",
-                        "thresholdVolts": 2,
-                        "highVolts": 5
+                        "kind": "d-flip-flop"
                     },
                     "terminals": [
                         2,
+                        4,
+                        5,
+                        3,
                         0,
+                        1,
+                        13,
                         6
                     ]
                 },
                 {
                     "law": {
-                        "kind": "logic-divider",
-                        "thresholdVolts": 2,
-                        "highVolts": 5
+                        "kind": "d-flip-flop"
                     },
                     "terminals": [
                         10,
+                        8,
+                        7,
+                        9,
                         12,
+                        11,
+                        13,
                         6
                     ]
                 }
@@ -6083,26 +6117,37 @@ const entries = [
             "kind": "sections",
             "sections": [
                 {
+                    // Same D-type flip-flop law; indices are in this entry's
+                    // section-order pinout (1Q, 1QBAR, 1CLK, 1D, 1RESET, 1SET,
+                    // 2Q, 2QBAR, 2CLK, 2D, 2RESET, 2SET, VDD, VSS), still in
+                    // canonical law order: clock, d, set, reset, q, q_bar,
+                    // vdd, vss.
                     "law": {
-                        "kind": "logic-divider",
-                        "thresholdVolts": 2,
-                        "highVolts": 5
+                        "kind": "d-flip-flop"
                     },
                     "terminals": [
                         2,
+                        3,
+                        5,
+                        4,
                         0,
+                        1,
+                        12,
                         13
                     ]
                 },
                 {
                     "law": {
-                        "kind": "logic-divider",
-                        "thresholdVolts": 2,
-                        "highVolts": 5
+                        "kind": "d-flip-flop"
                     },
                     "terminals": [
                         8,
+                        9,
+                        11,
+                        10,
                         6,
+                        7,
+                        12,
                         13
                     ]
                 }
@@ -7307,11 +7352,15 @@ const entries = [
     // 2026-10-15: the NJR/JRC marking rides the NJM sheet). GBW is not in this entry: it
     // lives in the data-registry row (TYP 15 MHz at f = 10 kHz), stamped by the pass below.
     {
+        // Wave 8: the bare transcribed number-portion "4580" (Azusa Driver U2, 8 pins)
+        // rides this entry (same die family per the owner JRC-rides-NJM decision above);
+        // it carries no GBW figure (see `opampGainBandwidthAbsent`).
         "partIds": [
             "JRC4580D",
             "JRC4580",
             "NJM4580D",
-            "NJM4580"
+            "NJM4580",
+            "4580"
         ],
         "declaredTypes": [],
         "terminalRoleGroups": [
@@ -7816,8 +7865,11 @@ const entries = [
     // (1OUT, 1IN-, 1IN+, VDD-/GND, 2IN+, 2IN-, 2OUT, VDD+), same A/B convention as the
     // LM833 entry above.
     {
+        // Wave 8: the C-suffix spelling rides here -- the quoted table IS the TLC2262C
+        // operating characteristics (MXR Badass 78 U2). Same row as the GBW alias.
         "partIds": [
-            "TLC2262"
+            "TLC2262",
+            "TLC2262C"
         ],
         "declaredTypes": [],
         "terminalRoleGroups": [
@@ -8942,6 +8994,397 @@ const entries = [
             ]
         }
     },
+    // Wave 8 (opamp batch, corpus-driven): sections whose open-loop gain is the sheet's
+    // own TYP AOL transcribed (the gain-bandwidth product lives in
+    // `registry-data/opamp.ts`, stamped by the passes below; the swing pair stays absent
+    // per the D4 freeze). GBW rows and catalog entries are 1:1 by part id, so no entry
+    // splits; AOL-only and generic-name ids below carry sections with no GBW row.
+    // TI TL081 single JFET-input op-amp, from SLOS081O (Feb 1977, rev Sept 2025) 5.8 DC:
+    // 'AOL | Open-loop voltage | VO = 0 V | TL08xC | MIN 25 TYP 200 V/mV'. Used as
+    // `openLoopGain: 200000` (bare id takes the commercial C-grade column, disclosed;
+    // TL072C precedent). No GBW figure (package/grade split; see
+    // `opampGainBandwidthAbsent`). Single-DIP shape mirrors the LM741/TL071 entry.
+    {
+        "partIds": [
+            "TL081"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "vin+",
+                "in+",
+                "pin3"
+            ],
+            [
+                "vin-",
+                "in-",
+                "pin2"
+            ],
+            [
+                "vout",
+                "out",
+                "pin6"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 200000
+                    },
+                    "terminals": [
+                        0,
+                        1,
+                        2
+                    ]
+                }
+            ],
+            "pinout": [
+                "vin+",
+                "vin-",
+                "vout"
+            ]
+        }
+    },
+    // TI MC1458P dual general-purpose op-amp, from SLOS069C (Feb 1971, rev Aug 2010),
+    // electrical characteristics at VCC+- = +-15 V: 'Large-signal differential voltage
+    // amplification, RL >= 2 kOhm, VO = +-10 V, 25C: MIN 20 (MC1458) / 50 (MC1558) TYP 200
+    // V/mV'. Used as `openLoopGain: 200000` (both grades share the TYP). MC1458P is the
+    // PDIP orderable named on the title block. GBW TYP 1 MHz lives in the data-registry row.
+    {
+        "partIds": [
+            "MC1458P"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "OUT_A_pin1"
+            ],
+            [
+                "INVERTING_A_pin2"
+            ],
+            [
+                "NONINVERTING_A_pin3"
+            ],
+            [
+                "V_MINUS_pin4"
+            ],
+            [
+                "NONINVERTING_B_pin5"
+            ],
+            [
+                "INVERTING_B_pin6"
+            ],
+            [
+                "OUT_B_pin7"
+            ],
+            [
+                "V_PLUS_pin8"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "pinout": [
+                "OUT_A",
+                "IN_A_MINUS",
+                "IN_A_PLUS",
+                "VEE",
+                "IN_B_PLUS",
+                "IN_B_MINUS",
+                "OUT_B",
+                "VCC"
+            ],
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 200000
+                    },
+                    "terminals": [
+                        2,
+                        1,
+                        0
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 200000
+                    },
+                    "terminals": [
+                        4,
+                        5,
+                        6
+                    ]
+                }
+            ]
+        }
+    },
+    // Renesas CA3240EZ dual BiMOS op-amp, from FN1050 Rev 6.00 (Mar 2005) guaranteed table
+    // (VSUPPLY = +-15 V, TA = 25C): 'Large-Signal Voltage Gain AOL, VO = 26VP-P, RL = 2 kOhm
+    // (Note 3): MIN 20 TYP 100 kV/V' both grades. Used as `openLoopGain: 100000`. CA3240EZ
+    // is the 8 Ld PDIP orderable. GBW TYP 4.5 MHz lives in the data-registry row.
+    {
+        "partIds": [
+            "CA3240EZ"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "OUT_A_pin1"
+            ],
+            [
+                "INVERTING_A_pin2"
+            ],
+            [
+                "NONINVERTING_A_pin3"
+            ],
+            [
+                "V_MINUS_pin4"
+            ],
+            [
+                "NONINVERTING_B_pin5"
+            ],
+            [
+                "INVERTING_B_pin6"
+            ],
+            [
+                "OUT_B_pin7"
+            ],
+            [
+                "V_PLUS_pin8"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "pinout": [
+                "OUT_A",
+                "IN_A_MINUS",
+                "IN_A_PLUS",
+                "VEE",
+                "IN_B_PLUS",
+                "IN_B_MINUS",
+                "OUT_B",
+                "VCC"
+            ],
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 100000
+                    },
+                    "terminals": [
+                        2,
+                        1,
+                        0
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 100000
+                    },
+                    "terminals": [
+                        4,
+                        5,
+                        6
+                    ]
+                }
+            ]
+        }
+    },
+    // ON Semi LM301AN single non-compensated op-amp, from LM301A/D Rev. 12 (July 2025)
+    // ELECTRICAL CHARACTERISTICS (TA = +25C; LM301A column, +-5 to +-15 V supply range):
+    // 'Large Signal Voltage Gain AV: MIN 50 (LM201A) / 25 (LM301A) TYP 160 V/mV' both grades
+    // share the TYP. Used as `openLoopGain: 160000`. LM301AN is the PDIP-8 orderable. No GBW
+    // row exists (see `opampGainBandwidthAbsent`; same AOL-only shape as LM308).
+    // Single-DIP shape mirrors the LM741/TL071 entry.
+    {
+        "partIds": [
+            "LM301AN"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "vin+",
+                "in+",
+                "pin3"
+            ],
+            [
+                "vin-",
+                "in-",
+                "pin2"
+            ],
+            [
+                "vout",
+                "out",
+                "pin6"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 160000
+                    },
+                    "terminals": [
+                        0,
+                        1,
+                        2
+                    ]
+                }
+            ],
+            "pinout": [
+                "vin+",
+                "vin-",
+                "vout"
+            ]
+        }
+    },
+    // Renesas CA3130EZ single BiMOS op-amp, from FN817 Rev 6.00 (Aug 2005) Table 1
+    // (TA = 25C, V+ = 15 V, V- = 0 V): 'Large-Signal Voltage Gain AOL, VO = 10VP-P, RL = 2
+    // kOhm: MIN 50 TYP 320 kV/V' both grades. Used as `openLoopGain: 320000`. CA3130EZ is
+    // the 8 Ld PDIP orderable. No GBW figure (compensation-dependent fT; see
+    // `opampGainBandwidthAbsent`). Single-DIP shape mirrors the LM741/TL071 entry.
+    {
+        "partIds": [
+            "CA3130EZ"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "vin+",
+                "in+",
+                "pin3"
+            ],
+            [
+                "vin-",
+                "in-",
+                "pin2"
+            ],
+            [
+                "vout",
+                "out",
+                "pin6"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 320000
+                    },
+                    "terminals": [
+                        0,
+                        1,
+                        2
+                    ]
+                }
+            ],
+            "pinout": [
+                "vin+",
+                "vin-",
+                "vout"
+            ]
+        }
+    },
+    // Bare "4559" dual (Mojo Rook IC1, 8 pins): no 4559-family sheet cited, so the sections
+    // carry the house 100000, disclosed as unsourced (TL062/LM741-single precedent), with no
+    // GBW figure (see `opampGainBandwidthAbsent`; same verdict as bare 4558). Standard dual
+    // order, same pin-numbered role convention as the NJM4580 entry.
+    {
+        "partIds": [
+            "4559"
+        ],
+        "declaredTypes": [],
+        "terminalRoleGroups": [
+            [
+                "OUT_A_pin1"
+            ],
+            [
+                "INVERTING_A_pin2"
+            ],
+            [
+                "NONINVERTING_A_pin3"
+            ],
+            [
+                "V_MINUS_pin4"
+            ],
+            [
+                "NONINVERTING_B_pin5"
+            ],
+            [
+                "INVERTING_B_pin6"
+            ],
+            [
+                "OUT_B_pin7"
+            ],
+            [
+                "V_PLUS_pin8"
+            ]
+        ],
+        "model": {
+            "kind": "sections",
+            "pinout": [
+                "OUT_A",
+                "IN_A_MINUS",
+                "IN_A_PLUS",
+                "VEE",
+                "IN_B_PLUS",
+                "IN_B_MINUS",
+                "OUT_B",
+                "VCC"
+            ],
+            "sections": [
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 100000
+                    },
+                    "terminals": [
+                        2,
+                        1,
+                        0
+                    ]
+                },
+                {
+                    "law": {
+                        "kind": "ideal-opamp",
+                        "railHigh": null,
+                        "railLow": null,
+                        "openLoopGain": 100000
+                    },
+                    "terminals": [
+                        4,
+                        5,
+                        6
+                    ]
+                }
+            ]
+        }
+    },
     ...zenerRegistryRecords.map((record) => zenerLaw(record)),
     // Wave-1 discrete fill: bjt, diode-forward, mosfet and jfet-channel records become
     // law entries through the builders above -- one list per class, so the entries cannot