@vcad/mcp 0.9.4-main.72 → 0.9.4-main.74

package/README.md

@@ -6,4 +6,4 @@ vcad's MCP server as a self-contained bundle (server + BRep kernel WASM).
 { "mcpServers": { "vcad": { "command": "npx", "args": ["-y", "@vcad/mcp"] } } }
 ```
 
-Built from 150875476b916d4e772bdeb33726c543ccf2756d at 2026-08-17T03:05:59.733Z. Source: https://github.com/ecto/vcad
+Built from cad60a705d41503617de2b556150aaeae3e893c8 at 2026-08-19T15:53:22.260Z. Source: https://github.com/ecto/vcad

package/index.mjs

@@ -225,6 +225,10 @@ __export(vcad_kernel_wasm_exports, {
   op_shell: () => op_shell,
   op_sweep_helix: () => op_sweep_helix,
   op_sweep_line: () => op_sweep_line,
+  parseAltiumAsciiPcb: () => parseAltiumAsciiPcb,
+  parseAltiumPcbDoc: () => parseAltiumPcbDoc,
+  parseAltiumPcbLib: () => parseAltiumPcbLib,
+  parseEagleBrd: () => parseEagleBrd,
   parseKicadPcb: () => parseKicadPcb,
   parseVCode: () => parseVCode,
   parseVcadFile: () => parseVcadFile,
@@ -2443,6 +2447,42 @@ function op_sweep_line(profile_json, start, end, twist_angle, scale_start, scale
   }
   return Solid.__wrap(ret[0]);
 }
+function parseAltiumAsciiPcb(content) {
+  const ptr0 = passStringToWasm0(content, wasm.__wbindgen_malloc, wasm.__wbindgen_realloc);
+  const len0 = WASM_VECTOR_LEN;
+  const ret = wasm.parseAltiumAsciiPcb(ptr0, len0);
+  if (ret[2]) {
+    throw takeFromExternrefTable0(ret[1]);
+  }
+  return takeFromExternrefTable0(ret[0]);
+}
+function parseAltiumPcbDoc(bytes) {
+  const ptr0 = passArray8ToWasm0(bytes, wasm.__wbindgen_malloc);
+  const len0 = WASM_VECTOR_LEN;
+  const ret = wasm.parseAltiumPcbDoc(ptr0, len0);
+  if (ret[2]) {
+    throw takeFromExternrefTable0(ret[1]);
+  }
+  return takeFromExternrefTable0(ret[0]);
+}
+function parseAltiumPcbLib(bytes) {
+  const ptr0 = passArray8ToWasm0(bytes, wasm.__wbindgen_malloc);
+  const len0 = WASM_VECTOR_LEN;
+  const ret = wasm.parseAltiumPcbLib(ptr0, len0);
+  if (ret[2]) {
+    throw takeFromExternrefTable0(ret[1]);
+  }
+  return takeFromExternrefTable0(ret[0]);
+}
+function parseEagleBrd(content) {
+  const ptr0 = passStringToWasm0(content, wasm.__wbindgen_malloc, wasm.__wbindgen_realloc);
+  const len0 = WASM_VECTOR_LEN;
+  const ret = wasm.parseEagleBrd(ptr0, len0);
+  if (ret[2]) {
+    throw takeFromExternrefTable0(ret[1]);
+  }
+  return takeFromExternrefTable0(ret[0]);
+}
 function parseKicadPcb(content) {
   const ptr0 = passStringToWasm0(content, wasm.__wbindgen_malloc, wasm.__wbindgen_realloc);
   const len0 = WASM_VECTOR_LEN;
@@ -10874,6 +10914,46 @@ async function parseKicadPcb2(content) {
     return null;
   }
 }
+function importBindings(wasm3) {
+  const mod = wasm3;
+  const bind = (name) => {
+    const fn = mod[name];
+    if (typeof fn !== "function") {
+      throw new Error(`Altium import is unavailable: this kernel WASM build predates ${name}. Rebuild the kernel WASM (npm run build -w vcad-kernel-wasm) or update @vcad/mcp.`);
+    }
+    return fn;
+  };
+  return {
+    parseAltiumAsciiPcb: (content) => bind("parseAltiumAsciiPcb")(content),
+    parseAltiumPcbDoc: (bytes) => bind("parseAltiumPcbDoc")(bytes),
+    parseAltiumPcbLib: (bytes) => bind("parseAltiumPcbLib")(bytes),
+    parseEagleBrd: (content) => bind("parseEagleBrd")(content)
+  };
+}
+async function parseEagleBrd2(content) {
+  const wasm3 = await loadEcadWasm();
+  if (!wasm3)
+    return null;
+  return importBindings(wasm3).parseEagleBrd(content);
+}
+async function parseAltiumAsciiPcb2(content) {
+  const wasm3 = await loadEcadWasm();
+  if (!wasm3)
+    return null;
+  return importBindings(wasm3).parseAltiumAsciiPcb(content);
+}
+async function parseAltiumPcbDoc2(bytes) {
+  const wasm3 = await loadEcadWasm();
+  if (!wasm3)
+    return null;
+  return importBindings(wasm3).parseAltiumPcbDoc(bytes);
+}
+async function parseAltiumPcbLib2(bytes) {
+  const wasm3 = await loadEcadWasm();
+  if (!wasm3)
+    return null;
+  return importBindings(wasm3).parseAltiumPcbLib(bytes);
+}
 async function exportKicadPcb2(pcb) {
   const wasm3 = await loadEcadWasm();
   if (!wasm3)
@@ -11719,7 +11799,11 @@ __export(dist_exports, {
   mountingHolesFromPcb: () => mountingHolesFromPcb,
   netContinuity: () => netContinuity,
   outlineAabb: () => outlineAabb,
+  parseAltiumAsciiPcb: () => parseAltiumAsciiPcb2,
+  parseAltiumPcbDoc: () => parseAltiumPcbDoc2,
+  parseAltiumPcbLib: () => parseAltiumPcbLib2,
   parseBindingKey: () => parseBindingKey,
+  parseEagleBrd: () => parseEagleBrd2,
   parseExpression: () => parse,
   parseKicadPcb: () => parseKicadPcb2,
   parseXyz: () => parseXyz,
@@ -41547,6 +41631,45 @@ var init_CHANGELOG = __esm({
     CHANGELOG_default = {
       $schema: "./changelog.schema.json",
       entries: [
+        {
+          id: "2026-08-19-loon-modules-and-root-cache",
+          version: "0.9.4",
+          date: "2026-08-19",
+          category: "feat",
+          title: "Loon lib path and a content-addressed evaluation cache",
+          summary: "[use] modules resolve next to the file then on $VCAD_LOON_PATH, identically in vcad, vcad-render and MCP; evaluated root meshes are cached on disk keyed by expression + kernel build.",
+          features: [
+            "loon",
+            "modules",
+            "cache",
+            "cli",
+            "render"
+          ],
+          mcpTools: [
+            "load_document",
+            "create_cad_loon"
+          ]
+        },
+        {
+          id: "2026-08-17-altium-pcb-import",
+          version: "0.9.4",
+          date: "2026-08-17",
+          category: "feat",
+          title: "Altium and Eagle PCB import",
+          summary: "Import Altium .PcbDoc boards (native binary or ASCII) and .PcbLib libraries, plus Eagle .brd boards, straight into a live session.",
+          features: [
+            "pcb",
+            "import",
+            "ecad",
+            "altium",
+            "eagle"
+          ],
+          mcpTools: [
+            "import_altium",
+            "import_altium_library",
+            "import_eagle"
+          ]
+        },
         {
           id: "2026-08-16-render-z-up",
           version: "0.9.4",
@@ -41559,6 +41682,48 @@ var init_CHANGELOG = __esm({
             "rendering"
           ]
         },
+        {
+          id: "2026-08-16-render-hidden-lines",
+          version: "0.9.4",
+          date: "2026-08-16",
+          category: "fix",
+          title: "SVG renders draw complete, actually-dashed hidden lines",
+          summary: "Hidden edges on curved features were mostly deleted and the survivors drew solid, leaving a stray line across the part; they now run the full occluded length as proper dashes.",
+          features: [
+            "rendering",
+            "drafting"
+          ]
+        },
+        {
+          id: "2026-08-16-render-annotation-scaling",
+          version: "0.9.4",
+          date: "2026-08-16",
+          category: "fix",
+          title: "Render overlays stay readable at any size",
+          summary: "The axes gizmo, part labels and dimensions now scale with the canvas instead of staying 1024px-sized, dimension lines clear round parts, and labels no longer land on the geometry they name.",
+          features: [
+            "rendering",
+            "drafting"
+          ],
+          mcpTools: [
+            "render_view"
+          ]
+        },
+        {
+          id: "2026-08-16-render-aa-and-depth-cue",
+          version: "0.9.4",
+          date: "2026-08-16",
+          category: "fix",
+          title: "Smoother renders: anti-aliasing and a per-pixel depth cue",
+          summary: "Isometric renders anti-alias their silhouettes and linework, flat faces no longer break into hard tonal wedges at triangle boundaries, and edge strokes sit on their geometry instead of half a stroke off.",
+          features: [
+            "rendering",
+            "tessellation"
+          ],
+          mcpTools: [
+            "render_view"
+          ]
+        },
         {
           id: "2026-08-16-loon-sheet-metal-bindings",
           version: "0.9.4",
@@ -41578,6 +41743,20 @@ var init_CHANGELOG = __esm({
             "flat_pattern_from_solid"
           ]
         },
+        {
+          id: "2026-08-16-cli-sheet-metal-fold",
+          version: "0.9.4",
+          date: "2026-08-16",
+          category: "fix",
+          title: "Sheet-metal parts export from the CLI again",
+          summary: "vcad info/export and vcad-render now fold sheet-metal chains \u2014 including jogs and bend relief \u2014 instead of reporting zero triangles, and a root that fails to evaluate says why.",
+          features: [
+            "sheet-metal",
+            "cli",
+            "loon",
+            "export"
+          ]
+        },
         {
           id: "2026-08-16-cli-loon-input-everywhere",
           version: "0.9.4",
@@ -50057,7 +50236,7 @@ var init_source_provenance = __esm({
 
 // src/tools/loon.ts
 import { readFileSync as readFileSync3 } from "node:fs";
-import { isAbsolute as isAbsolute2, join as join2, resolve as resolve2, sep as sep2 } from "node:path";
+import { delimiter, isAbsolute as isAbsolute2, join as join2, resolve as resolve2, sep as sep2 } from "node:path";
 function composeLoonProgram(input) {
   const { source, use_loons, loons } = input;
   const names = [
@@ -50088,12 +50267,18 @@ function readModule(base, name) {
   }
   return null;
 }
+function loonLibDirs(env = process.env) {
+  const raw = env.VCAD_LOON_PATH;
+  if (!raw) return [];
+  return raw.split(delimiter).filter((d) => d.length > 0);
+}
 function composeLoonModules(input) {
   const { source, loons, modules, base_dir } = input;
   const map = {};
   for (const m of loons ?? []) map[m.name] = m.source;
   Object.assign(map, modules ?? {});
-  if (base_dir) {
+  const dirs = [...base_dir ? [base_dir] : [], ...loonLibDirs()];
+  if (dirs.length) {
     const pending2 = [
       ...importedNames(source),
       ...Object.values(map).flatMap(importedNames)
@@ -50103,7 +50288,11 @@ function composeLoonModules(input) {
       const name = pending2.pop();
       if (seen.has(name) || map[name]) continue;
       seen.add(name);
-      const src = readModule(base_dir, name);
+      let src = null;
+      for (const dir of dirs) {
+        src = readModule(dir, name);
+        if (src !== null) break;
+      }
       if (src === null) continue;
       map[name] = src;
       pending2.push(...importedNames(src));
@@ -55478,6 +55667,8 @@ var init_tool_metadata = __esm({
       import_step: { title: "Import STEP", annotations: RW },
       import_urdf: { title: "Import URDF", annotations: RW },
       import_kicad: { title: "Import KiCad", annotations: RW },
+      import_altium: { title: "Import Altium", annotations: RW },
+      import_altium_library: { title: "Import Altium Library", annotations: RO },
       import_eagle: { title: "Import EAGLE", annotations: RW },
       open_in_browser: { title: "Open in Browser", annotations: RW },
       // ── Physics gym ────────────────────────────────────────────────────────
@@ -78484,10 +78675,72 @@ function readSource(input, label) {
   }
   throw new Error("Provide either `filename` or `content_base64`");
 }
+function readSourceBytes(input, label) {
+  const { filename, content_base64 } = input;
+  if (content_base64) {
+    const buf = Buffer.from(content_base64, "base64");
+    if (buf.length === 0) throw new Error("content_base64 decoded to zero bytes");
+    if (buf.length > MAX_PCB_BYTES) {
+      throw new Error(`${label} content exceeds the ${MAX_PCB_BYTES} byte limit`);
+    }
+    return buf;
+  }
+  if (filename) {
+    if (isRemoteDeployment()) {
+      throw new Error(
+        `This hosted server has no filesystem access \u2014 pass the ${label} contents as \`content_base64\` instead of \`filename\`.`
+      );
+    }
+    const filepath = resolveWithinRoot(
+      filename,
+      process.env.VCAD_MCP_EXPORT_DIR ?? process.cwd()
+    );
+    if (!existsSync5(filepath)) throw new Error(`${label} file not found`);
+    const stat = statSync3(filepath);
+    if (!stat.isFile()) throw new Error(`${label} path is not a regular file`);
+    if (stat.size > MAX_PCB_BYTES) {
+      throw new Error(`${label} file exceeds the ${MAX_PCB_BYTES} byte limit`);
+    }
+    return readFileSync8(filepath);
+  }
+  throw new Error("Provide either `filename` or `content_base64`");
+}
+function registerBoard(pcb, name) {
+  const doc = createDocument();
+  doc.nodes["1"] = {
+    id: 1,
+    name,
+    // eslint-disable-next-line @typescript-eslint/no-explicit-any
+    op: { type: "PcbBoard", board: pcb }
+  };
+  doc.roots.push({ root: 1, material: "__pcb_fr4__" });
+  doc.materials["__pcb_fr4__"] = {
+    name: "__pcb_fr4__",
+    color: [0.05, 0.35, 0.15],
+    roughness: 0.6,
+    metallic: 0
+  };
+  return registerSession(doc);
+}
+function boardSummary(pcb) {
+  return {
+    footprints: pcb.footprints.length,
+    nets: pcb.nets.length,
+    outline_vertices: pcb.outline?.vertices?.length ?? 0,
+    traces: pcb.traces.length,
+    vias: pcb.vias.length,
+    zones: pcb.zones.length,
+    design_rules: {
+      trace_width: pcb.rules?.defaultRules?.traceWidth,
+      clearance: pcb.rules?.defaultRules?.clearance,
+      via_diameter: pcb.rules?.defaultRules?.viaDiameter
+    }
+  };
+}
 function boardName(input) {
   if (input.name) return input.name;
   if (input.filename) {
-    return input.filename.replace(/^.*[/\\]/, "").replace(/\.kicad_pcb$/i, "");
+    return input.filename.replace(/^.*[/\\]/, "").replace(/\.(kicad_pcb|pcbdoc|pcblib|brd)$/i, "");
   }
   return "Imported board";
 }
@@ -78512,21 +78765,7 @@ async function importKicad(input) {
       "KiCad parsing is unavailable (kernel WASM is missing parseKicadPcb) or the file produced no board."
     );
   }
-  const doc = createDocument();
-  doc.nodes["1"] = {
-    id: 1,
-    name: boardName(args),
-    // eslint-disable-next-line @typescript-eslint/no-explicit-any
-    op: { type: "PcbBoard", board: pcb }
-  };
-  doc.roots.push({ root: 1, material: "__pcb_fr4__" });
-  doc.materials["__pcb_fr4__"] = {
-    name: "__pcb_fr4__",
-    color: [0.05, 0.35, 0.15],
-    roughness: 0.6,
-    metallic: 0
-  };
-  const documentId = registerSession(doc);
+  const documentId = registerBoard(pcb, boardName(args));
   const onlyPlacement = pcb.traces.length === 0 && pcb.vias.length === 0;
   return {
     content: [
@@ -78535,19 +78774,7 @@ async function importKicad(input) {
         text: JSON.stringify({
           success: true,
           document_id: documentId,
-          summary: {
-            footprints: pcb.footprints.length,
-            nets: pcb.nets.length,
-            outline_vertices: pcb.outline?.vertices?.length ?? 0,
-            traces: pcb.traces.length,
-            vias: pcb.vias.length,
-            zones: pcb.zones.length,
-            design_rules: {
-              trace_width: pcb.rules?.defaultRules?.traceWidth,
-              clearance: pcb.rules?.defaultRules?.clearance,
-              via_diameter: pcb.rules?.defaultRules?.viaDiameter
-            }
-          },
+          summary: boardSummary(pcb),
           ...onlyPlacement ? {
             note: "Placement + netlist only \u2014 the file carried no routed copper."
           } : {}
@@ -78556,12 +78783,138 @@ async function importKicad(input) {
     ]
   };
 }
-function importEagle(_input) {
-  return importError(
-    "Eagle (.brd) import is not yet supported. Export your board from Eagle as KiCad (File > Export > KiCad .kicad_pcb) and use import_kicad instead."
-  );
+function isCompoundFile(bytes) {
+  return bytes.length >= 8 && bytes.subarray(0, 8).equals(Buffer.from([208, 207, 17, 224, 161, 177, 26, 225]));
 }
-var MAX_PCB_BYTES, importKicadSchema, importEagleSchema, toolDefs46;
+async function importAltium(input) {
+  const args = input ?? {};
+  let bytes;
+  try {
+    bytes = readSourceBytes(args, "Altium");
+  } catch (e) {
+    return importError(e instanceof Error ? e.message : String(e));
+  }
+  const binary = isCompoundFile(bytes);
+  let pcb;
+  try {
+    pcb = binary ? await parseAltiumPcbDoc2(new Uint8Array(bytes)) : await parseAltiumAsciiPcb2(bytes.toString("utf8"));
+  } catch (e) {
+    return importError(
+      `Could not parse the Altium ${binary ? "binary" : "ASCII"} .PcbDoc: ` + (e instanceof Error ? e.message : String(e))
+    );
+  }
+  if (!pcb) {
+    return importError(
+      "Altium parsing is unavailable (kernel WASM is missing parseAltiumPcbDoc)."
+    );
+  }
+  const documentId = registerBoard(pcb, boardName(args));
+  const onlyPlacement = pcb.traces.length === 0 && pcb.vias.length === 0;
+  return {
+    content: [
+      {
+        type: "text",
+        text: JSON.stringify({
+          success: true,
+          document_id: documentId,
+          source_format: binary ? "PcbDoc (binary)" : "PcbDoc (ASCII)",
+          summary: boardSummary(pcb),
+          ...onlyPlacement ? { note: "Placement + netlist only \u2014 the file carried no routed copper." } : {},
+          ...binary ? {
+            note_binary: "Binary .PcbDoc record layouts are reconstructed, not specified by Altium, and are validated against real open-hardware projects. Geometry that decoded implausibly fails the import outright rather than importing wrong, but spot-check with render_pcb before fabricating. Copper pours and text are not imported."
+          } : {}
+        })
+      }
+    ]
+  };
+}
+async function importAltiumLibrary(input) {
+  const args = input ?? {};
+  let bytes;
+  try {
+    bytes = readSourceBytes(args, "Altium library");
+  } catch (e) {
+    return importError(e instanceof Error ? e.message : String(e));
+  }
+  let lib;
+  try {
+    lib = await parseAltiumPcbLib2(new Uint8Array(bytes));
+  } catch (e) {
+    return importError(
+      `Could not parse the Altium .PcbLib: ${e instanceof Error ? e.message : String(e)}`
+    );
+  }
+  if (!lib) {
+    return importError(
+      "Altium parsing is unavailable (kernel WASM is missing parseAltiumPcbLib)."
+    );
+  }
+  return {
+    content: [
+      {
+        type: "text",
+        text: JSON.stringify({
+          success: true,
+          footprint_count: lib.footprints.length,
+          footprints: lib.footprints.map((f) => ({
+            name: f.name,
+            pad_count: f.pads.length,
+            pads: f.pads.map((p) => ({
+              number: p.number,
+              type: p.pad_type,
+              position: p.position,
+              rotation: p.rotation,
+              drill: p.drill?.diameter ?? null
+            }))
+          }))
+        })
+      }
+    ]
+  };
+}
+async function importEagle(input) {
+  const args = input ?? {};
+  let content;
+  try {
+    content = readSource(args, "Eagle");
+  } catch (e) {
+    return importError(e instanceof Error ? e.message : String(e));
+  }
+  if (!content.includes("<eagle") && !content.includes("<board")) {
+    return importError(
+      "This does not look like an Eagle XML .brd file. Eagle 5 and earlier wrote a binary .brd \u2014 open it in Eagle 6+ (which converts it to XML) and save, then import that."
+    );
+  }
+  let pcb;
+  try {
+    pcb = await parseEagleBrd2(content);
+  } catch (e) {
+    return importError(
+      `Could not parse the Eagle .brd: ${e instanceof Error ? e.message : String(e)}`
+    );
+  }
+  if (!pcb) {
+    return importError(
+      "Eagle parsing is unavailable (kernel WASM is missing parseEagleBrd)."
+    );
+  }
+  const documentId = registerBoard(pcb, boardName(args));
+  const onlyPlacement = pcb.traces.length === 0 && pcb.vias.length === 0;
+  return {
+    content: [
+      {
+        type: "text",
+        text: JSON.stringify({
+          success: true,
+          document_id: documentId,
+          summary: boardSummary(pcb),
+          ...onlyPlacement ? { note: "Placement + netlist only \u2014 the file carried no routed copper." } : {}
+        })
+      }
+    ]
+  };
+}
+var MAX_PCB_BYTES, importKicadSchema, importAltiumSchema, importAltiumLibrarySchema, importEagleSchema, toolDefs46;
 var init_import_pcb = __esm({
   "src/tools/import-pcb.ts"() {
     "use strict";
@@ -78589,16 +78942,50 @@ var init_import_pcb = __esm({
         }
       }
     };
+    importAltiumSchema = {
+      type: "object",
+      properties: {
+        filename: {
+          type: "string",
+          description: "Path to a .PcbDoc file on the server filesystem (relative to VCAD_MCP_EXPORT_DIR or cwd). Native binary and ASCII exports are both accepted. On hosted servers pass content_base64 instead."
+        },
+        content_base64: {
+          type: "string",
+          description: "Base64-encoded .PcbDoc contents (preferred for hosted servers)."
+        },
+        name: {
+          type: "string",
+          description: "Board name for display (default: filename without extension)."
+        }
+      }
+    };
+    importAltiumLibrarySchema = {
+      type: "object",
+      properties: {
+        filename: {
+          type: "string",
+          description: "Path to a .PcbLib footprint library (binary or ASCII)."
+        },
+        content_base64: {
+          type: "string",
+          description: "Base64-encoded .PcbLib contents."
+        }
+      }
+    };
     importEagleSchema = {
       type: "object",
       properties: {
         filename: {
           type: "string",
-          description: "Path to a .brd file (Eagle XML format)."
+          description: "Path to a .brd file (Eagle XML, Eagle 6+)."
         },
         content_base64: {
           type: "string",
-          description: "Base64-encoded .brd contents."
+          description: "Base64-encoded .brd contents (preferred for hosted servers)."
+        },
+        name: {
+          type: "string",
+          description: "Board name for display (default: filename without extension)."
         }
       }
     };
@@ -78611,13 +78998,29 @@ var init_import_pcb = __esm({
         handler: async (a) => await importKicad(a),
         behavior: behavior({ writesDoc: true, geometry: true })
       },
+      {
+        name: "import_altium",
+        pack: "ecad",
+        description: "Import an Altium .PcbDoc board into a live session \u2014 board outline, footprints with pads + nets, design rules, and any routed traces/vias. Accepts both the native binary file and an ASCII export (detected automatically). Returns a document_id ready for render_pcb, run_drc, get_pad_positions, route_nets, and export_gerber. The binary path fails closed on record layouts it cannot decode rather than importing a partially-correct board. Pass content_base64 on hosted servers.",
+        inputSchema: importAltiumSchema,
+        handler: async (a) => await importAltium(a),
+        behavior: behavior({ writesDoc: true, geometry: true })
+      },
+      {
+        name: "import_altium_library",
+        pack: "ecad",
+        description: "Read an Altium .PcbLib footprint library (binary or ASCII) and return its footprint patterns with pads, shapes, and drills. A library is not a board, so no document_id is minted.",
+        inputSchema: importAltiumLibrarySchema,
+        handler: async (a) => await importAltiumLibrary(a),
+        behavior: behavior({})
+      },
       {
         name: "import_eagle",
         pack: "ecad",
-        description: "Import an Eagle .brd file (not yet supported). Export your board from Eagle as KiCad (.kicad_pcb) and use import_kicad instead.",
+        description: "Import an Eagle .brd board (XML, Eagle 6+) into a live session \u2014 board outline, packages placed as footprints with pads, signals as nets, and any hand-routed traces/vias. Returns a document_id ready for render_pcb, run_drc, get_pad_positions, route_nets, and export_gerber. Pass content_base64 on hosted servers.",
         inputSchema: importEagleSchema,
-        handler: (a) => importEagle(a),
-        behavior: behavior({})
+        handler: async (a) => await importEagle(a),
+        behavior: behavior({ writesDoc: true, geometry: true })
       }
     ];
   }
@@ -83649,8 +84052,8 @@ var init_server3 = __esm({
     init_order_feed();
     init_animate();
     PKG_VERSION = (() => {
-      if ("0.9.4-main.72") {
-        return "0.9.4-main.72";
+      if ("0.9.4-main.74") {
+        return "0.9.4-main.74";
       }
       try {
         const req = createRequire2(import.meta.url);
@@ -83659,8 +84062,8 @@ var init_server3 = __esm({
         return "0.0.0";
       }
     })();
-    BUILD_SHA = "150875476b916d4e772bdeb33726c543ccf2756d";
-    BUILD_TIME = "2026-08-17T03:05:59.733Z";
+    BUILD_SHA = "cad60a705d41503617de2b556150aaeae3e893c8";
+    BUILD_TIME = "2026-08-19T15:53:22.260Z";
     SHORT_SHA = BUILD_SHA === "unknown" ? "unknown" : BUILD_SHA.slice(0, 7);
     VERSION_WITH_BUILD = SHORT_SHA === "unknown" ? PKG_VERSION : `${PKG_VERSION}+${SHORT_SHA}`;
     INSTANCE_ID = randomUUID7().slice(0, 8);
@@ -83856,6 +84259,8 @@ var init_server3 = __esm({
       "import_step",
       "import_urdf",
       "import_kicad",
+      "import_altium",
+      "import_altium_library",
       "import_eagle",
       "open_in_browser",
       // ── Physics gym ────────────────────────────────────────────

package/package.json

@@ -1,6 +1,6 @@
 {
   "name": "@vcad/mcp",
-  "version": "0.9.4-main.72",
+  "version": "0.9.4-main.74",
   "description": "vcad MCP server — parametric CAD + PCB design tools for AI agents (self-contained: bundled server + kernel WASM)",
   "license": "MIT",
   "type": "module",
@@ -19,7 +19,7 @@
   },
   "homepage": "https://vcad.io",
   "vcadBuild": {
-    "sha": "150875476b916d4e772bdeb33726c543ccf2756d",
-    "builtAt": "2026-08-17T03:05:59.733Z"
+    "sha": "cad60a705d41503617de2b556150aaeae3e893c8",
+    "builtAt": "2026-08-19T15:53:22.260Z"
   }
 }