@vcad/mcp 0.9.4-main.18 → 0.9.4-main.19

package/README.md

@@ -6,4 +6,4 @@ vcad's MCP server as a self-contained bundle (server + BRep kernel WASM).
 { "mcpServers": { "vcad": { "command": "npx", "args": ["-y", "@vcad/mcp"] } } }
 ```
 
-Built from 48276771946e67b08cb31a66d123bdc2d7af926d at 2026-07-24T22:30:13.865Z. Source: https://github.com/ecto/vcad
+Built from 7f18700be295061f294b748d3d7aa957f34ddd1c at 2026-07-25T13:19:21.672Z. Source: https://github.com/ecto/vcad

package/index.mjs

@@ -245,6 +245,7 @@ __export(vcad_kernel_wasm_exports, {
   sectionMesh: () => sectionMesh,
   sheetMetalFoldedStep: () => sheetMetalFoldedStep,
   sheetMetalSequence: () => sheetMetalSequence,
+  simulateFlow: () => simulateFlow,
   simulateStrikeKernel: () => simulateStrikeKernel,
   sketchCircleSegments: () => sketchCircleSegments,
   sketchHitTest: () => sketchHitTest,
@@ -2797,6 +2798,17 @@ function sheetMetalSequence(chain_json) {
     wasm.__wbindgen_free(deferred2_0, deferred2_1, 1);
   }
 }
+function simulateFlow(spec_json, options_json, include_fields) {
+  const ptr0 = passStringToWasm0(spec_json, wasm.__wbindgen_malloc, wasm.__wbindgen_realloc);
+  const len0 = WASM_VECTOR_LEN;
+  const ptr1 = passStringToWasm0(options_json, wasm.__wbindgen_malloc, wasm.__wbindgen_realloc);
+  const len1 = WASM_VECTOR_LEN;
+  const ret = wasm.simulateFlow(ptr0, len0, ptr1, len1, include_fields);
+  if (ret[2]) {
+    throw takeFromExternrefTable0(ret[1]);
+  }
+  return takeFromExternrefTable0(ret[0]);
+}
 function simulateStrikeKernel(input_json) {
   let deferred3_0;
   let deferred3_1;
@@ -10249,6 +10261,25 @@ async function tryRunDrc(pcb) {
     return { ok: false, reason: "error", message: e instanceof Error ? e.message : String(e) };
   }
 }
+async function runFabPrep(pcb, options) {
+  const wasm3 = await loadEcadWasm();
+  if (!wasm3) {
+    return { ok: false, reason: "unavailable", message: "ECAD kernel WASM not loaded" };
+  }
+  if (typeof wasm3.ecadFabPrep !== "function") {
+    return {
+      ok: false,
+      reason: "unavailable",
+      message: "kernel WASM predates ecadFabPrep"
+    };
+  }
+  try {
+    const out = wasm3.ecadFabPrep(JSON.stringify(pcb), options ? JSON.stringify(options) : void 0);
+    return { ok: true, value: out };
+  } catch (e) {
+    return { ok: false, reason: "error", message: e instanceof Error ? e.message : String(e) };
+  }
+}
 async function runPcbDfm(pcb, profile, rulePackToml) {
   const wasm3 = await loadEcadWasm();
   if (!wasm3 || typeof wasm3.ecadDfmCheck !== "function")
@@ -11275,6 +11306,7 @@ __export(dist_exports, {
   runDrc: () => runDrc,
   runDrcInRegion: () => runDrcInRegion,
   runErc: () => runErc,
+  runFabPrep: () => runFabPrep,
   runPcbDfm: () => runPcbDfm,
   sampleSequence: () => sampleSequence,
   sampleTrackValue: () => sampleTrackValue,
@@ -40816,6 +40848,20 @@ var init_CHANGELOG = __esm({
     CHANGELOG_default = {
       $schema: "./changelog.schema.json",
       entries: [
+        {
+          id: "2026-07-24-visionos-app",
+          version: "0.9.4",
+          date: "2026-07-24",
+          category: "feat",
+          title: "vcad for Apple Vision Pro",
+          summary: "The full native editor ported to visionOS: documents float in a volume with the feature tree, inspector, tool palette, and AI composer around them.",
+          features: [
+            "native",
+            "visionos",
+            "assembly",
+            "patterns"
+          ]
+        },
         {
           id: "2026-07-24-router-keepout-edge-clearance",
           version: "0.9.4",
@@ -40834,6 +40880,24 @@ var init_CHANGELOG = __esm({
             "validate_for_fab"
           ]
         },
+        {
+          id: "2026-07-24-router-drill-aware-vias-pad-layer-stubs",
+          version: "0.9.4",
+          date: "2026-07-24",
+          category: "fix",
+          title: "Router vias clear drills; stubs leave pads on the pad's layer",
+          summary: "The routing oracle now checks hole-to-hole spacing across layer spans (two vias on disjoint spans no longer collide in the drill file), probes a via barrel on every layer it spans, and can pin a connection's terminals so stubs leave a pad on a layer the pad is actually on instead of floating on an inner layer.",
+          features: [
+            "pcb",
+            "autorouter",
+            "drc"
+          ],
+          mcpTools: [
+            "route_nets",
+            "run_drc",
+            "validate_for_fab"
+          ]
+        },
         {
           id: "2026-07-24-lattice-gauge-mcp",
           version: "0.9.4",
@@ -40865,6 +40929,26 @@ var init_CHANGELOG = __esm({
             "simulate_flow"
           ]
         },
+        {
+          id: "2026-07-24-fab-prep-drc-delta-receipt",
+          version: "0.9.4",
+          date: "2026-07-24",
+          category: "feat",
+          title: "One-command fab prep with a DRC-delta receipt",
+          summary: "vcad fab-prep (and the fab_prep MCP tool) takes a routed board to a complete Gerber package in one call: opt-in logged rule calibration, verdict ladder, strip-and-re-route fix loop, dangling-copper prune, and a receipt that separates route-attributable violations from the board's own baseline.",
+          features: [
+            "pcb",
+            "drc",
+            "autorouter",
+            "fabrication",
+            "cli"
+          ],
+          mcpTools: [
+            "fab_prep",
+            "validate_for_fab",
+            "export_gerber"
+          ]
+        },
         {
           id: "2026-07-23-router-post-route-legalization",
           version: "0.9.4",
@@ -51968,6 +52052,7 @@ var init_tool_metadata = __esm({
         annotations: RW,
         outputSchema: objectOut({ export_kicad: { type: "object" } })
       },
+      fab_prep: { title: "Fab Prep", annotations: RW },
       validate_for_fab: { title: "Validate for Fab", annotations: RO },
       calc_impedance: { title: "Calc Impedance", annotations: RO },
       size_impedance: { title: "Size Impedance", annotations: RO },
@@ -59534,6 +59619,85 @@ function detectUnsupportedFeatures(pcb) {
   }
   return out;
 }
+async function fabPrep(args) {
+  const ctx = resolveDocInput(args);
+  const pcb = getDocPcb2(ctx.doc);
+  if (!pcb) {
+    return ecadError(
+      "Document has no PCB \u2014 run place_components first (or open a document that has a board)"
+    );
+  }
+  if (!await isEcadAvailable2()) {
+    return ecadError(
+      "fab_prep requires the kernel DRC/routing engine (ECAD WASM unavailable) \u2014 refusing to report an unverifiable fab-readiness verdict"
+    );
+  }
+  const dryRun = Boolean(args.dry_run);
+  const options = {
+    calibrate_rules: Boolean(args.calibrate_rules),
+    route_remaining: args.route_remaining === void 0 ? true : Boolean(args.route_remaining),
+    prune_dangling: args.prune_dangling === void 0 ? true : Boolean(args.prune_dangling),
+    max_rounds: Math.max(0, Math.round(Number(args.max_rounds ?? 8))),
+    accept_rules: Array.isArray(args.accept_rules) ? args.accept_rules : [],
+    verdict: {
+      budget: Math.max(1, Math.round(Number(args.budget ?? 5e6))),
+      max_cluster: Math.max(1, Math.round(Number(args.max_cluster ?? 6)))
+    }
+  };
+  const out = await runFabPrep(pcb, options);
+  if (!out.ok) {
+    return ecadError(`fab_prep could not run: ${out.message}`);
+  }
+  const { report, pcb: fixed } = out.value;
+  if (!dryRun) {
+    pcb.traces = fixed.traces;
+    pcb.traceArcs = fixed.traceArcs;
+    pcb.vias = fixed.vias;
+    pcb.rules = fixed.rules;
+  }
+  const payload = {
+    success: true,
+    ...dryRun ? { dry_run: true } : {},
+    converged: report.converged,
+    ...report.blocker ? { blocker: report.blocker } : {},
+    headline: fabPrepHeadline(report),
+    // Both numbers, always. A caller that sees only one of them is being told
+    // something other than what this run established.
+    drc_delta: {
+      baseline_total: report.delta.baseline_total,
+      final_total: report.delta.final_total,
+      route_attributable_total: report.delta.route_attributable_total,
+      route_attributable_blocking: report.delta.route_attributable_fixable,
+      route_attributable_accepted: report.delta.route_attributable_accepted,
+      by_rule: report.delta.rules,
+      baseline_note: "baseline = this same board with every trace and via stripped, checked under the same rules. It is not zero on an imported fixture and is not supposed to be; the router is answerable for the difference, not the total."
+    },
+    connectivity: report.connectivity,
+    ...report.accepted_rules.length > 0 ? { accepted_rules: report.accepted_rules } : {},
+    calibration: {
+      requested: report.calibration_requested,
+      applied: report.calibration.applied,
+      refused: report.calibration.refused
+    },
+    initial_verdict: report.initial_verdict,
+    rounds: report.rounds,
+    pruned: { traces: report.pruned_traces, vias: report.pruned_vias },
+    // Cap the offender list: a non-converging run on a dense board can name
+    // thousands, and the full list lives in the board's own DRC.
+    offenders: report.delta.offenders.slice(0, 25),
+    offender_count: report.delta.offenders.length,
+    next_action: report.converged ? "export_gerber (the clean-DRC gate will now pass)" : "resolve the offenders above (fix_drc / route_nets / set_placement), then re-run fab_prep",
+    ...docResultPayload(ctx)
+  };
+  return { content: [{ type: "text", text: JSON.stringify(payload) }] };
+}
+function fabPrepHeadline(report) {
+  if (!report.converged) {
+    return `NOT FAB-READY \u2014 ${report.delta.route_attributable_fixable} route-attributable violation(s) remain (${report.blocker ?? "loop did not converge"})`;
+  }
+  const waived = report.delta.route_attributable_accepted > 0 ? `, ${report.delta.route_attributable_accepted} waived under ${report.accepted_rules.join("+")}` : "";
+  return `zero route-attributable violations${waived} \u2014 ${report.delta.final_total} on the finished board, ${report.delta.baseline_total} on the same board stripped of all routing`;
+}
 async function validateForFab(args) {
   const ctx = resolveDocInput(args);
   const pcb = getDocPcb2(ctx.doc);
@@ -64784,7 +64948,7 @@ async function fixDrc(args) {
   };
   return { content: [{ type: "text", text: JSON.stringify(payload) }] };
 }
-var PCB_LAYER_SET, COPPER_LAYERS, COPPER_LAYER_SET, POSITION_TOLERANCE, PIN_SEP, pinKey, createSchematicSchema, docInputProperties, placeComponentsSchema, routeNetsSchema, runDrcSchema, runErcSchema, critiqueRouteSchema, routeDiffPairSchema, lengthMatchTracesSchema, exportGerberSchema, validateForFabSchema, exportKicadSchema, addCoilSchema, boardFromSolidSchema, addCoilArraySchema, windingLayoutSchema, calcImpedanceSchema, sizeImpedanceSchema, sizePdnSchema, calcCoilSchema, sizeCoilSchema, calcRfSchema, COIL_GEOMETRY, MU0, RAIL_PIN_NAMES, PIN_TYPES, CHIP_SIZE_CODES, CONNECTIVITY_GUARD_MAX_NETS, POWER_NET_RE, DRC_CATEGORY, DRC_DELTA_SAMPLE_CAP, DRC_DELTA_FULL_BOARD_MAX, LINT_CRYSTAL_MAX_MM, LINT_DECAP_MAX_MM, LINT_CONNECTOR_EDGE_MAX_MM, LINT_HIGH_CURRENT_SEP_MIN_MM, LINT_GROUND_NET_RE, LINT_SUPPLY_NET_RE, SENSITIVE_NET_RE, HIGH_CURRENT_CLASS_RE, refPrefix, dist2d, round2, sumSq, round33, vec2Schema, setBoardOutlineSchema, FOOTPRINT_FAMILIES, listFootprintsSchema, searchFootprintsSchema, getPadPositionsSchema, getFootprintSchema, ROTATION_CONVENTION, describePcbSchema, DESCRIBE_NET_NAME_CAP, addTraceSchema, addViaSchema, OZ_TO_MM, setStackupSchema, setPlacementSchema, addZoneSchema, deleteElementProps, deleteZoneSchema, deleteTraceSchema, deleteViaSchema, COPPER_KINDS, GET_COPPER_CAP, getCopperSchema, TIE_POSITION_TOL, addNetTieSchema, deleteNetTieSchema, undoSchema, setDesignRulesSchema, sizeTraceForCurrentSchema, addViaArraySchema, MAX_VIA_ARRAY, addMotorWindingSchema, calcMotorSchema, sig6, BEARING_FRICTION_MNM, checkSelfStartSchema, solidFromBoardSchema, FR4_DENSITY_KG_M3, COPPER_DENSITY_KG_M3, DEFAULT_COPPER_THICKNESS_MM, loopArea, MOUNTING_FP_RE, KEEPOUT_ECHO_CAP, INLINE_DOC_ECHO_CAP, searchElectronicPartsSchema, resolvePartSchema, findAlternativesSchema, verifySubstitutionSchema, buildReceiptSchema, verifyReceiptSchema, FIX_EPS, FIX_DRC_NEVER, fixDrcSchema, toolDefs20;
+var PCB_LAYER_SET, COPPER_LAYERS, COPPER_LAYER_SET, POSITION_TOLERANCE, PIN_SEP, pinKey, createSchematicSchema, docInputProperties, placeComponentsSchema, routeNetsSchema, runDrcSchema, runErcSchema, critiqueRouteSchema, routeDiffPairSchema, lengthMatchTracesSchema, exportGerberSchema, validateForFabSchema, fabPrepSchema, exportKicadSchema, addCoilSchema, boardFromSolidSchema, addCoilArraySchema, windingLayoutSchema, calcImpedanceSchema, sizeImpedanceSchema, sizePdnSchema, calcCoilSchema, sizeCoilSchema, calcRfSchema, COIL_GEOMETRY, MU0, RAIL_PIN_NAMES, PIN_TYPES, CHIP_SIZE_CODES, CONNECTIVITY_GUARD_MAX_NETS, POWER_NET_RE, DRC_CATEGORY, DRC_DELTA_SAMPLE_CAP, DRC_DELTA_FULL_BOARD_MAX, LINT_CRYSTAL_MAX_MM, LINT_DECAP_MAX_MM, LINT_CONNECTOR_EDGE_MAX_MM, LINT_HIGH_CURRENT_SEP_MIN_MM, LINT_GROUND_NET_RE, LINT_SUPPLY_NET_RE, SENSITIVE_NET_RE, HIGH_CURRENT_CLASS_RE, refPrefix, dist2d, round2, sumSq, round33, vec2Schema, setBoardOutlineSchema, FOOTPRINT_FAMILIES, listFootprintsSchema, searchFootprintsSchema, getPadPositionsSchema, getFootprintSchema, ROTATION_CONVENTION, describePcbSchema, DESCRIBE_NET_NAME_CAP, addTraceSchema, addViaSchema, OZ_TO_MM, setStackupSchema, setPlacementSchema, addZoneSchema, deleteElementProps, deleteZoneSchema, deleteTraceSchema, deleteViaSchema, COPPER_KINDS, GET_COPPER_CAP, getCopperSchema, TIE_POSITION_TOL, addNetTieSchema, deleteNetTieSchema, undoSchema, setDesignRulesSchema, sizeTraceForCurrentSchema, addViaArraySchema, MAX_VIA_ARRAY, addMotorWindingSchema, calcMotorSchema, sig6, BEARING_FRICTION_MNM, checkSelfStartSchema, solidFromBoardSchema, FR4_DENSITY_KG_M3, COPPER_DENSITY_KG_M3, DEFAULT_COPPER_THICKNESS_MM, loopArea, MOUNTING_FP_RE, KEEPOUT_ECHO_CAP, INLINE_DOC_ECHO_CAP, searchElectronicPartsSchema, resolvePartSchema, findAlternativesSchema, verifySubstitutionSchema, buildReceiptSchema, verifyReceiptSchema, FIX_EPS, FIX_DRC_NEVER, fixDrcSchema, toolDefs20;
 var init_ecad2 = __esm({
   "src/tools/ecad.ts"() {
     "use strict";
@@ -65150,6 +65314,46 @@ var init_ecad2 = __esm({
       },
       required: []
     };
+    fabPrepSchema = {
+      type: "object",
+      properties: {
+        ...docInputProperties,
+        calibrate_rules: {
+          type: "boolean",
+          description: "Derive and apply design-rule calibration from the board's OWN declared via classes and pre-existing footprint holes (default FALSE). Imported boards routinely carry global minima that forbid the via class they themselves declare \u2014 e.g. a 0.21/0.12mm class under a 0.2mm minDrill, which flags every via on the board. Calibration only ever relaxes a rule to the point where the board's own GIVEN geometry stops being illegal, is floored at laser-microvia limits, and records every change with its derivation in the receipt. Off by default because silently relaxing DRC rules to make a board pass is how an unbuildable board ships."
+        },
+        route_remaining: {
+          type: "boolean",
+          description: "Route or certify the connections the board arrived without, before the fix loop (default TRUE). Each unrouted connection ends as Routed, ProvedInfeasible (with a bottleneck-cut certificate), or an honest unknown \u2014 never silently dropped."
+        },
+        max_rounds: {
+          type: "number",
+          description: "Maximum strip-and-re-route rounds (default 8). Each round censuses the violations the ROUTING is answerable for, strips those nets, and hands them back to the session-probed router."
+        },
+        budget: {
+          type: "number",
+          description: "Per-cluster search budget in node expansions for the complete router (default 5,000,000). Lower is faster and yields more honest unknowns."
+        },
+        max_cluster: {
+          type: "number",
+          description: "Maximum connections coalesced into one joint search window (default 6)."
+        },
+        prune_dangling: {
+          type: "boolean",
+          description: "Remove copper that reaches no pad or pour of its net before the final DRC (default TRUE)."
+        },
+        accept_rules: {
+          type: "array",
+          items: { type: "string" },
+          description: 'DRC rule names whose route-attributable violations are ACCEPTED rather than fixed (e.g. ["MinTraceWidth"]). Real fab packages ship with real, named exceptions; the difference between that and a footgun is whether the exception is written down. Waived violations are still counted, still listed, and the waiver is named in the receipt \u2014 it stops blocking the verdict, it does not hide anything. An unrecognised rule name refuses the run rather than silently accepting nothing.'
+        },
+        dry_run: {
+          type: "boolean",
+          description: "Compute the receipt without writing the fixed board back to the session."
+        }
+      },
+      required: []
+    };
     exportKicadSchema = {
       type: "object",
       properties: {
@@ -66766,6 +66970,14 @@ var init_ecad2 = __esm({
         handler: (a) => exportKicad(a),
         behavior: behavior({})
       },
+      {
+        name: "fab_prep",
+        pack: "ecad",
+        description: "Take a routed board to fab-ready in one call, and return the DRC-delta receipt that says what was actually achieved. Runs the whole pipeline: optional rule calibration (opt-in, every change logged with its derivation), the verdict ladder over unrouted connections (each ends Routed / ProvedInfeasible / honest-unknown), then a strip-and-re-route fix loop until the violations the ROUTING is answerable for reach zero, then a dangling-copper prune. Mutates the session document. THE RECEIPT IS THE POINT: on an imported fixture absolute zero is not achievable \u2014 the same board stripped of all routing already violates its own rules \u2014 so the report always gives BOTH numbers (stripped-board baseline and finished board) and charges only the difference to the router. Fails closed: a loop that does not converge returns `converged:false` with the remaining offenders and does not pretend otherwise, and `export_gerber`'s clean-DRC gate still stands \u2014 this is the supported way to GET clean, not a way around it.",
+        inputSchema: fabPrepSchema,
+        handler: (a) => fabPrep(a),
+        behavior: behavior({ writesDoc: true, geometry: true, mount: true })
+      },
       {
         name: "validate_for_fab",
         pack: "ecad",
@@ -77719,8 +77931,8 @@ var init_server3 = __esm({
     init_order_feed();
     init_animate();
     PKG_VERSION = (() => {
-      if ("0.9.4-main.18") {
-        return "0.9.4-main.18";
+      if ("0.9.4-main.19") {
+        return "0.9.4-main.19";
       }
       try {
         const req = createRequire2(import.meta.url);
@@ -77729,8 +77941,8 @@ var init_server3 = __esm({
         return "0.0.0";
       }
     })();
-    BUILD_SHA = "48276771946e67b08cb31a66d123bdc2d7af926d";
-    BUILD_TIME = "2026-07-24T22:30:13.865Z";
+    BUILD_SHA = "7f18700be295061f294b748d3d7aa957f34ddd1c";
+    BUILD_TIME = "2026-07-25T13:19:21.672Z";
     SHORT_SHA = BUILD_SHA === "unknown" ? "unknown" : BUILD_SHA.slice(0, 7);
     VERSION_WITH_BUILD = SHORT_SHA === "unknown" ? PKG_VERSION : `${PKG_VERSION}+${SHORT_SHA}`;
     INSTANCE_ID = randomUUID6().slice(0, 8);
@@ -77990,6 +78202,7 @@ var init_server3 = __esm({
       "run_erc",
       "export_gerber",
       "export_kicad",
+      "fab_prep",
       "validate_for_fab",
       "calc_impedance",
       "size_impedance",

package/package.json

@@ -1,6 +1,6 @@
 {
   "name": "@vcad/mcp",
-  "version": "0.9.4-main.18",
+  "version": "0.9.4-main.19",
   "description": "vcad MCP server — parametric CAD + PCB design tools for AI agents (self-contained: bundled server + kernel WASM)",
   "license": "MIT",
   "type": "module",
@@ -19,7 +19,7 @@
   },
   "homepage": "https://vcad.io",
   "vcadBuild": {
-    "sha": "48276771946e67b08cb31a66d123bdc2d7af926d",
-    "builtAt": "2026-07-24T22:30:13.865Z"
+    "sha": "7f18700be295061f294b748d3d7aa957f34ddd1c",
+    "builtAt": "2026-07-25T13:19:21.672Z"
   }
 }