@typecad/framework-zephyr 1.0.0-alpha.13 → 1.0.0-alpha.14

package/README.md

@@ -35,7 +35,19 @@ fix (`pip install west`, set `ZEPHYR_BASE`, or activate the venv).
   symbols for the lowered peripherals). Both are regenerated idempotently —
   only rewritten when their content changes, so Ninja's incremental build is
   preserved.
-- The MVP target is the **Seeed Studio XIAO nRF52840** (`xiao_ble` board).
+- Supported board targets: **Seeed Studio XIAO nRF52840** (`xiao_ble`),
+  **ESP32 DevKit** (`esp32_devkitc`), **ESP32-S3 DevKit** (`esp32s3_devkitc`),
+  **ESP32-C3 DevKitM** (`esp32c3_devkitm/esp32c3`), **ESP32-C6 DevKitC**
+  (`esp32c6_devkitc/esp32c6/hpcore` — the qualified form is required, the
+  board also ships an lpcore variant), **Raspberry Pi Pico** (`rpi_pico`),
+  **Pico 2** (`rpi_pico2/rp2350a/m33`), and **WeAct Black Pill V2.0**
+  (`blackpill_f411ce/stm32f411xe` — the first STM32 target; flashed over USB
+  via the ROM DFU bootloader). The rpi_pico, esp32c3, esp32c6, and blackpill
+  boards resolve their chip data from the board packages' `zephyr` field (see
+  `resolveChipFromBoard`) rather than the hardcoded chip registry; the
+  qualified Pico 2 target selects the Cortex-M33 cpucluster (Zephyr 4.3+
+  rejects the bare `rpi_pico2` because the board also ships a Hazard3 variant
+  with no default).
 
 ## Installation
 

package/dist/chips/controllers.d.ts

@@ -1,4 +1,4 @@
-import type { ZephyrChipDescriptor } from './types.js';
+import type { ZephyrChipDescriptor, ZephyrGpioController } from './types.js';
 /**
  * Resolve the devicetree nodelabel of the GPIO controller that owns `pin`.
  *
@@ -9,13 +9,33 @@ import type { ZephyrChipDescriptor } from './types.js';
  */
 export declare function controllerNodelabelForPin(chip: ZephyrChipDescriptor, pin: number): string;
 /**
- * Emit the C++ source for a runtime pin → GPIO-device dispatcher.
+ * The owning controller range for a HAL pin, if the chip declares a split.
+ */
+export declare function controllerRangeForPin(chip: ZephyrChipDescriptor, pin: number): ZephyrGpioController | undefined;
+/**
+ * The PORT-RELATIVE pin index for the raw gpio_pin_*_raw() API — the Zephyr
+ * raw calls address the index WITHIN the controller, not the global HAL pin
+ * number. For split SoCs each controller's `minPin` is its base (STM32:
+ * gpiob minPin 16, so PB12 = pin 28 → raw 12); single-controller SoCs have
+ * no offset. Emitting the global number against a port driver would address
+ * a nonexistent port bit (STM32 gpiob is 0–15) and fail at runtime.
+ */
+export declare function controllerRawPinForPin(chip: ZephyrChipDescriptor, pin: number): number;
+/**
+ * Emit the C++ source for runtime pin → GPIO-device / port-relative-index
+ * dispatchers.
+ *
+ * Returns lines defining:
+ *  - `static inline const struct device* __tc_gpio_dev(uint32_t pin)` — the
+ *    owning controller's device, resolved via DEVICE_DT_GET(DT_NODELABEL(...))
+ *    at compile time (the macro is evaluated per branch, so it is always
+ *    statically valid); only `pin` is runtime.
+ *  - `static inline gpio_pin_t __tc_gpio_pin(uint32_t pin)` — the
+ *    port-relative index for gpio_pin_*_raw() (see controllerRawPinForPin).
+ *    The runtime shim paths (UI pin-watch, safety voters) take a runtime pin,
+ *    so they cannot bake the offset in at emit time.
  *
- * Returns lines defining `static inline const struct device* __tc_gpio_dev(uint32_t pin)`.
- * Each branch resolves its controller via `DEVICE_DT_GET(DT_NODELABEL(...))` at
- * compile time (the macro is evaluated per branch, so it is always statically
- * valid); only `pin` is runtime. For a single-controller SoC this collapses to
- * a one-liner returning that controller, so the existing XIAO nRF52840 behavior
- * is byte-for-byte unchanged.
+ * For a single-controller SoC both collapse to one-liners, so the existing
+ * XIAO nRF52840 behavior is byte-for-byte unchanged.
  */
 export declare function emitGpioDevDispatcher(chip: ZephyrChipDescriptor): string[];

package/dist/chips/controllers.js

@@ -27,23 +27,47 @@
  * for out-of-range pins (e.g. the manifest probe's synthetic pin 0).
  */
 export function controllerNodelabelForPin(chip, pin) {
+    const hit = controllerRangeForPin(chip, pin);
+    return hit ? hit.nodelabel : chip.gpioController;
+}
+/**
+ * The owning controller range for a HAL pin, if the chip declares a split.
+ */
+export function controllerRangeForPin(chip, pin) {
     const ranges = chip.gpioControllers;
     if (ranges && ranges.length > 0) {
-        const hit = ranges.find((r) => pin >= r.minPin && pin <= r.maxPin);
-        if (hit)
-            return hit.nodelabel;
+        return ranges.find((r) => pin >= r.minPin && pin <= r.maxPin);
     }
-    return chip.gpioController;
+    return undefined;
 }
 /**
- * Emit the C++ source for a runtime pin → GPIO-device dispatcher.
+ * The PORT-RELATIVE pin index for the raw gpio_pin_*_raw() API — the Zephyr
+ * raw calls address the index WITHIN the controller, not the global HAL pin
+ * number. For split SoCs each controller's `minPin` is its base (STM32:
+ * gpiob minPin 16, so PB12 = pin 28 → raw 12); single-controller SoCs have
+ * no offset. Emitting the global number against a port driver would address
+ * a nonexistent port bit (STM32 gpiob is 0–15) and fail at runtime.
+ */
+export function controllerRawPinForPin(chip, pin) {
+    const hit = controllerRangeForPin(chip, pin);
+    return pin - (hit?.minPin ?? 0);
+}
+/**
+ * Emit the C++ source for runtime pin → GPIO-device / port-relative-index
+ * dispatchers.
+ *
+ * Returns lines defining:
+ *  - `static inline const struct device* __tc_gpio_dev(uint32_t pin)` — the
+ *    owning controller's device, resolved via DEVICE_DT_GET(DT_NODELABEL(...))
+ *    at compile time (the macro is evaluated per branch, so it is always
+ *    statically valid); only `pin` is runtime.
+ *  - `static inline gpio_pin_t __tc_gpio_pin(uint32_t pin)` — the
+ *    port-relative index for gpio_pin_*_raw() (see controllerRawPinForPin).
+ *    The runtime shim paths (UI pin-watch, safety voters) take a runtime pin,
+ *    so they cannot bake the offset in at emit time.
  *
- * Returns lines defining `static inline const struct device* __tc_gpio_dev(uint32_t pin)`.
- * Each branch resolves its controller via `DEVICE_DT_GET(DT_NODELABEL(...))` at
- * compile time (the macro is evaluated per branch, so it is always statically
- * valid); only `pin` is runtime. For a single-controller SoC this collapses to
- * a one-liner returning that controller, so the existing XIAO nRF52840 behavior
- * is byte-for-byte unchanged.
+ * For a single-controller SoC both collapse to one-liners, so the existing
+ * XIAO nRF52840 behavior is byte-for-byte unchanged.
  */
 export function emitGpioDevDispatcher(chip) {
     const ranges = chip.gpioControllers;
@@ -53,14 +77,27 @@ export function emitGpioDevDispatcher(chip) {
             `    (void)pin;`,
             `    return DEVICE_DT_GET(DT_NODELABEL(${chip.gpioController}));`,
             '}',
+            'static inline gpio_pin_t __tc_gpio_pin(uint32_t pin) {',
+            `    return (gpio_pin_t)pin;`,
+            '}',
         ];
     }
     const lines = [
         'static inline const struct device* __tc_gpio_dev(uint32_t pin) {',
     ];
+    const pinLines = [
+        'static inline gpio_pin_t __tc_gpio_pin(uint32_t pin) {',
+    ];
     for (const r of ranges) {
         lines.push(`    if (pin >= ${r.minPin} && pin <= ${r.maxPin}) { return DEVICE_DT_GET(DT_NODELABEL(${r.nodelabel})); }`);
+        if (r.minPin === 0) {
+            pinLines.push(`    if (pin >= ${r.minPin} && pin <= ${r.maxPin}) { return (gpio_pin_t)pin; }`);
+        }
+        else {
+            pinLines.push(`    if (pin >= ${r.minPin} && pin <= ${r.maxPin}) { return (gpio_pin_t)(pin - ${r.minPin}); }`);
+        }
     }
     lines.push(`    return DEVICE_DT_GET(DT_NODELABEL(${chip.gpioController}));`, '}');
-    return lines;
+    pinLines.push(`    return (gpio_pin_t)pin;`, '}');
+    return [...lines, ...pinLines];
 }

package/dist/chips/resolve.js

@@ -81,18 +81,35 @@ export function resolveChipFromBoard(bc) {
     const pwmSpecs = collectIndexed(bc, 'zephyr.pwm.specs', (m, i) => {
         const pin = m.get(`zephyr.pwm.specs.${i}.pin`);
         const dtSpec = m.get(`zephyr.pwm.specs.${i}.dtSpec`);
-        if (pin != null && dtSpec)
-            return { pin, dtSpec };
-        return null;
+        const controller = m.get(`zephyr.pwm.specs.${i}.controller`);
+        const channel = m.get(`zephyr.pwm.specs.${i}.channel`);
+        const periodNs = m.get(`zephyr.pwm.specs.${i}.periodNs`);
+        const polarity = m.get(`zephyr.pwm.specs.${i}.polarity`);
+        // Board-shipped alias form (dtSpec) or synthesized form (controller +
+        // channel → overlay-generated alias) — at least one, else drop the entry.
+        if (pin == null || !(dtSpec || (controller && channel != null)))
+            return null;
+        return {
+            pin,
+            ...(dtSpec ? { dtSpec } : {}),
+            ...(controller ? { controller } : {}),
+            ...(channel != null ? { channel } : {}),
+            ...(periodNs != null ? { periodNs } : {}),
+            ...(polarity ? { polarity } : {}),
+        };
     });
     const adcNodeLabel = bc.get('zephyr.adc.nodeLabel');
     const adcResolution = bc.get('zephyr.adc.resolution');
     const adcVref = bc.get('zephyr.adc.vrefMv');
+    const adcGain = bc.get('zephyr.adc.gain');
+    const adcReference = bc.get('zephyr.adc.reference');
     const adcChannels = collectIndexed(bc, 'zephyr.adc.channels', (m, i) => {
         const pin = m.get(`zephyr.adc.channels.${i}.pin`);
         const channel = m.get(`zephyr.adc.channels.${i}.channel`);
-        if (pin != null && channel != null)
-            return { pin, channel };
+        const pinctrl = m.get(`zephyr.adc.channels.${i}.pinctrl`);
+        if (pin != null && channel != null) {
+            return { pin, channel, ...(pinctrl ? { pinctrl } : {}) };
+        }
         return null;
     });
     const wdtNodeLabel = bc.get('zephyr.wdt.nodeLabel');
@@ -113,7 +130,16 @@ export function resolveChipFromBoard(bc) {
         ...(uartControllers.length > 0 ? { uart: { controllers: uartControllers } } : {}),
         ...(pwmSpecs.length > 0 ? { pwm: { specs: pwmSpecs } } : {}),
         ...(adcNodeLabel || adcResolution != null || adcVref != null || adcChannels.length > 0
-            ? { adc: { nodeLabel: adcNodeLabel ?? 'adc', resolution: adcResolution ?? 12, vrefMv: adcVref ?? 3000, channels: adcChannels } }
+            ? {
+                adc: {
+                    nodeLabel: adcNodeLabel ?? 'adc',
+                    resolution: adcResolution ?? 12,
+                    vrefMv: adcVref ?? 3000,
+                    channels: adcChannels,
+                    ...(adcGain ? { gain: adcGain } : {}),
+                    ...(adcReference ? { reference: adcReference } : {}),
+                },
+            }
             : {}),
         ...(wdtNodeLabel ? { wdt: { nodeLabel: wdtNodeLabel } } : {}),
         ...(wifiSupported ? { wifi: { supported: true } } : {}),

package/dist/chips/types.d.ts

@@ -47,14 +47,37 @@ export interface ZephyrBusController {
 /**
  * A PWM channel described as a devicetree spec.
  *
- * Emitted as `struct pwm_dt_spec __tc_pwm<N> = PWM_DT_SPEC_GET(DT_ALIAS(<dtSpec>))`.
- * `pwm_set_pulse_dt(&__tc_pwm<N>, pulse_ns)` honors the spec's period/polarity.
+ * Two forms, mutually exclusive:
+ * - **Board-shipped alias:** `dtSpec` names a DT alias the board's own DTS
+ *   already defines (e.g. the XIAO's `pwm-led0`). Emitted as
+ *   `PWM_DT_SPEC_GET(DT_ALIAS(<dtSpec>))`.
+ * - **Synthesized** (controller + channel): the board DTS enables a PWM
+ *   controller node (e.g. `pwm4`) but defines no alias for it. The overlay
+ *   generator synthesizes a `pwm-leds` consumer node + a `tc-pwm<pin>` alias
+ *   in `<board>.overlay`; the lowering emits
+ *   `PWM_DT_SPEC_GET(DT_ALIAS(tc-pwm<pin>))`. Both sides derive the alias
+ *   name from the pin, so they always agree.
+ *
+ * `pwm_set_pulse_dt(&spec, pulse_ns)` honors the spec's period/polarity.
  */
 export interface ZephyrPwmSpec {
     /** GPIO number (matches the HAL op `pin` field). */
     readonly pin: number;
-    /** Devicetree alias, e.g. 'pwm-led0'. */
-    readonly dtSpec: string;
+    /** Board-shipped DT alias, e.g. 'pwm-led0'. Omit when using the
+     *  synthesized form (controller + channel). */
+    readonly dtSpec?: string;
+    /** Synthesized form: PWM controller DT nodelabel, e.g. 'pwm4' (the STM32
+     *  timer's pwm child node). The overlay's pwm-leds node consumes it. */
+    readonly controller?: string;
+    /** Synthesized form: channel index within the controller (1-based timer
+     *  channel, matching the `pwms` binding's channel cell). */
+    readonly channel?: number;
+    /** Synthesized form: period in nanoseconds, baked into the DT spec. The
+     *  lowering scales duty against `spec.period`. Default 20 000 000 (20 ms /
+     *  50 Hz — the servo convention; harmless for LED dimming). */
+    readonly periodNs?: number;
+    /** Synthesized form: PWM polarity flag. Default PWM_POLARITY_NORMAL. */
+    readonly polarity?: string;
 }
 /**
  * A GPIO pin usable as an interrupt source.
@@ -69,7 +92,7 @@ export interface ZephyrInterruptPin {
     readonly dtSpec: string;
 }
 /**
- * An ADC channel: which SAADC input a given HAL pin maps to.
+ * An ADC channel: which ADC input a given HAL pin maps to.
  *
  * The XIAO nRF52840 has no pre-declared ADC channel nodes in devicetree, so the
  * lowering emits `adc_channel_setup` against `DEVICE_DT_GET(DT_NODELABEL(adc))`
@@ -78,8 +101,16 @@ export interface ZephyrInterruptPin {
 export interface ZephyrAdcChannel {
     /** GPIO number (matches the HAL op `pin` field). */
     readonly pin: number;
-    /** SAADC channel index (AIN0–AIN7). */
+    /** ADC channel index (nRF SAADC AIN0–AIN7; STM32 ADC1_IN0–IN9). */
     readonly channel: number;
+    /**
+     * Pinctrl node label that muxes this pin to analog mode, e.g.
+     * 'adc1_in0_pa0' (STM32). When present, the overlay generator rewrites the
+     * ADC node's pinctrl-0 to the channels the program actually reads — SoCs
+     * like STM32 leave the pad in GPIO mode otherwise and reads float.
+     * Omit on SoCs whose ADC needs no pad muxing (nRF SAADC, RP2040).
+     */
+    readonly pinctrl?: string;
 }
 /**
  * A DAC channel: which DAC output a given HAL pin maps to. The lowering emits
@@ -113,11 +144,18 @@ export interface ZephyrChipDescriptor {
     readonly gpioController: string;
     /**
      * Per-range GPIO controllers for SoCs that split GPIO across multiple
-     * devicetree nodes (ESP32-S3: `gpio0` 0–31, `gpio1` 32–48). When present, the
-     * lowering routes a HAL pin to its owning controller at runtime via the
-     * emitted `__tc_gpio_dev(pin)` dispatcher; `gpioController` is the fallback.
-     * Omit on single-controller SoCs (nRF52840, RP2040, …) — every pin is on the
-     * one controller described by `gpioController`.
+     * devicetree nodes (ESP32-S3: `gpio0` 0–31, `gpio1` 32–48; STM32: one
+     * controller per port — `gpioa` 0–15, `gpiob` 16–31, `gpioc` 32–47).
+     * When present, the lowering routes a HAL pin to its owning controller at
+     * runtime via the emitted `__tc_gpio_dev(pin)` dispatcher; `gpioController`
+     * is the fallback. Omit on single-controller SoCs (RP2040, …) — every pin
+     * is on the one controller described by `gpioController`.
+     *
+     * NUMBERING RULE (load-bearing): `minPin` must equal the controller's port
+     * base so the port-relative raw index is `pin - minPin` (STM32 PB12 = pin
+     * 28 → raw 12 — the Zephyr raw API addresses the index WITHIN the
+     * controller). Number pins by port blocks and never contiguously across
+     * unbonded pins.
      */
     readonly gpioControllers?: readonly ZephyrGpioController[];
     /** GPIO pins with devicetree specs (LEDs, buttons, board-defined pins). */
@@ -142,7 +180,7 @@ export interface ZephyrChipDescriptor {
     readonly pwm?: {
         readonly specs: readonly ZephyrPwmSpec[];
     };
-    /** ADC: the SAADC node label + the pin→channel map. */
+    /** ADC: the ADC device node label + the pin→channel map. */
     readonly adc?: {
         readonly nodeLabel: string;
         readonly channels: readonly ZephyrAdcChannel[];
@@ -150,6 +188,19 @@ export interface ZephyrChipDescriptor {
         readonly vrefMv: number;
         /** ADC resolution in bits. */
         readonly resolution: number;
+        /**
+         * Zephyr `enum adc_gain` macro for the channel setup, e.g.
+         * 'ADC_GAIN_1_4' (nRF SAADC default) or 'ADC_GAIN_1' (STM32 driver
+         * requires exactly this). Defaults to 'ADC_GAIN_1_4'.
+         */
+        readonly gain?: string;
+        /**
+         * Zephyr `enum adc_reference` macro, e.g. 'ADC_REF_INTERNAL'. Defaults to
+         * 'ADC_REF_INTERNAL' — on nRF that is the 0.6 V internal ref measured
+         * through the gain divider; the STM32 driver ALSO requires
+         * ADC_REF_INTERNAL (Zephyr maps it to the VREF+ pad) with vrefMv = VDDA.
+         */
+        readonly reference?: string;
     };
     /**
      * DAC: the DAC device node label + the pin→channel map. Present only on chips

package/dist/chips/xiao-ble.js

@@ -8,6 +8,18 @@ export const XIAO_BLE = {
     id: 'xiao_ble',
     soc: 'nrf52840',
     gpioController: 'gpio0',
+    // GPIO is split across two devicetree controllers: gpio0 (P0.00–P0.31)
+    // and gpio1 (P1.00–P1.15, HAL pins 32–47). Declaring the split makes the
+    // raw path emit the port-relative index against gpio1 (P1.11 = raw 11),
+    // which NRF_GPIO_PIN_MAP(1, 11) resolves to absolute pin 43 — the same
+    // physical pin the old single-controller form reached only by accident:
+    // gpio0 + global 43 also maps to 43 (MAP(0, 43) = 43), but that form
+    // trips the generic layer's port_pin_mask __ASSERT ("Unsupported pin",
+    // gpio0's mask covers 0–31) on any assert-enabled build.
+    gpioControllers: [
+        { nodelabel: 'gpio0', minPin: 0, maxPin: 31 },
+        { nodelabel: 'gpio1', minPin: 32, maxPin: 47 },
+    ],
     gpio: {
         dtSpecs: [
             // Onboard RGB LEDs — active-low (GPIO_ACTIVE_LOW in xiao_ble_common.dtsi).

package/dist/dt-config/kconfig.d.ts

@@ -25,6 +25,17 @@ export interface KconfigUsage {
     /** PSRAM type ('opi' | 'quad') when the target board has PSRAM. Emits the
      *  CONFIG_SPIRAM symbols so the ESP heap serves PSRAM for canvas allocations. */
     psram?: 'opi' | 'quad';
+    /** HAL pin numbers the program reads with adc.* — scanned from the emitted
+     *  `__tc_adc<N>_setup()` calls at compile time. Only the overlay generator
+     *  consumes this (to rewrite the ADC node's pinctrl-0 to the used channels
+     *  on SoCs that need pad muxing, e.g. STM32); prj.conf ignores it. */
+    adcReadPins?: readonly number[];
+    /** HAL pin numbers the program drives with pwm.* — scanned from the
+     *  emitted `__tc_pwm_*` spec references at compile time. Only the overlay
+     *  generator consumes this (synthesized pwm-leds consumers + aliases are
+     *  emitted per used pin, so the DT carries no dead channels); prj.conf
+     *  ignores it. */
+    pwmUsedPins?: readonly number[];
 }
 /**
  * Resolve the Kconfig symbol→value map for a prj.conf. Returns a Map preserving

package/dist/dt-config/kconfig.js

@@ -97,7 +97,7 @@ export function resolveKconfigFragments(usage, debug) {
         // (without it, Kconfig silently forces them all to n).
         m.set('CONFIG_NETWORKING', 'y');
         m.set('CONFIG_WIFI', 'y');
-        m.set('CONFIG_WIFI_ESP32', 'y'); // ESP32-specific driver (sole WiFi target)
+        m.set('CONFIG_WIFI_ESP32', 'y'); // family-wide ESP32 driver (esp32/s3/c3/c6)
         m.set('CONFIG_NET_L2_ETHERNET', 'y');
         m.set('CONFIG_NET_IPV4', 'y');
         m.set('CONFIG_NET_UDP', 'y'); // transitive dep of NET_DHCPV4

package/dist/dt-config/overlay.js

@@ -53,6 +53,24 @@ export function generateOverlay(chip, usage, display, wiring, touch, diagnostics
         for (const c of chip.uart.controllers)
             block(c.nodeLabel);
     }
+    // PWM: synthesized specs (controller + channel, no board-shipped alias) get
+    // a pwm-leds consumer node + tc-pwm<pin> alias here — the lowering addresses
+    // the channel as PWM_DT_SPEC_GET(DT_ALIAS(tc-pwm<pin>)), so the alias must
+    // exist in the merged DT. pwmDtAlias (lowering/pwm.ts) derives the same
+    // name from the pin; the two sides cannot drift. Filtered to the pins the
+    // program actually drives (pwmUsedPins) so the DT carries no dead channels;
+    // an undefined list (prepare-time overlay) emits all specs.
+    if (usage.usesPwm && chip.pwm) {
+        emitPwmNodes(lines, chip, usage.pwmUsedPins);
+    }
+    // ADC: enable the ADC device node, and on SoCs whose channels carry a
+    // pinctrl label (STM32: the pad stays in GPIO mode unless the ADC node's
+    // pinctrl-0 muxes it analog), rewrite pinctrl-0 to exactly the channels the
+    // program reads. DT assignment replaces the whole property — the board
+    // default (one pad) is deliberately dropped in favor of the used set.
+    if (usage.usesAdc && chip.adc) {
+        emitAdcNode(lines, chip, usage.adcReadPins);
+    }
     // DAC: enable the chip's DAC device node when the program uses dac.*. The
     // lowering references DEVICE_DT_GET(DT_NODELABEL(<dac.device>)).
     if (usage.usesDac && chip.dac) {
@@ -106,6 +124,73 @@ export function generateOverlay(chip, usage, display, wiring, touch, diagnostics
     }
     return lines.join('\n');
 }
+/**
+ * Emit the pwm-leds consumer node + aliases for synthesized PWM specs.
+ *
+ * A board DTS may enable a PWM controller (`pwm4`) without aliasing any
+ * channel — the STM32 pattern — while the lowering addresses channels via
+ * DT_ALIAS. Each synthesized spec gets a `pwm-leds` child whose `pwms` cell
+ * binds the controller+channel (+ period/polarity), and a `tc-pwm<pin>`
+ * alias pointing at it. Alias/label names are valid DT identifiers (lowercase
+ * alphanumerics + dash/underscore).
+ */
+function emitPwmNodes(lines, chip, usedPins) {
+    const synthesized = (chip.pwm?.specs ?? []).filter((s) => s.controller && s.channel != null && !s.dtSpec).filter((s) => !usedPins || usedPins.includes(s.pin));
+    if (synthesized.length === 0)
+        return;
+    // Enable each distinct PWM controller node (idempotent when already okay).
+    for (const controller of [...new Set(synthesized.map((s) => s.controller))]) {
+        lines.push(`&${controller} {`);
+        lines.push('    status = "okay";');
+        lines.push('};');
+        lines.push('');
+    }
+    lines.push('/ {');
+    lines.push('    tc_pwm_leds: tc-pwm-leds {');
+    lines.push('        compatible = "pwm-leds";');
+    for (const s of synthesized) {
+        // 20 ms / 50 Hz default — the servo convention; the duty scaling in the
+        // lowering normalizes 0-255 against whatever period is baked in.
+        const period = s.periodNs ?? 20_000_000;
+        const polarity = s.polarity ?? 'PWM_POLARITY_NORMAL';
+        lines.push(`        tc_pwm_${s.pin}: pwm-led-${s.pin} {`);
+        lines.push(`            pwms = <&${s.controller} ${s.channel} ${period} ${polarity}>;`);
+        lines.push('        };');
+    }
+    lines.push('    };');
+    lines.push('    aliases {');
+    for (const s of synthesized) {
+        lines.push(`        tc-pwm${s.pin} = &tc_pwm_${s.pin};`);
+    }
+    lines.push('    };');
+    lines.push('};');
+    lines.push('');
+}
+/**
+ * Emit the ADC device-node enable (+ optional pinctrl override). The pinctrl
+ * override applies only when the descriptor's channels carry pinctrl labels
+ * AND the caller knows which pins the program reads (compile-time regen scans
+ * the emitted `__tc_adc<N>_setup()` calls); the prepare-time overlay omits it
+ * and the compile regen rewrites the file before west runs.
+ */
+function emitAdcNode(lines, chip, readPins) {
+    const adc = chip.adc;
+    const labeled = adc.channels.filter((c) => c.pinctrl);
+    const used = labeled.filter((c) => !readPins || readPins.includes(c.pin));
+    if (labeled.length > 0 && used.length > 0) {
+        lines.push(`&${adc.nodeLabel} {`);
+        lines.push('    status = "okay";');
+        lines.push(`    pinctrl-0 = <${used.map((c) => `&${c.pinctrl}`).join(' ')}>;`);
+        lines.push('    pinctrl-names = "default";');
+        lines.push('};');
+        lines.push('');
+        return;
+    }
+    lines.push(`&${adc.nodeLabel} {`);
+    lines.push('    status = "okay";');
+    lines.push('};');
+    lines.push('');
+}
 /**
  * Emit a display DT node definition. The node is attached to the profile's SPI
  * controller (default spi2, the ESP32's first user SPI controller) via a MIPI

package/dist/framework.manifest.d.ts

@@ -1,41 +1,31 @@
 declare const _default: {
-    hal: {
-        [x: string]: {
-            supported: boolean;
-            ops: Record<string, "stub" | "polyfill" | "supported" | "unsupported" | "probe-inconclusive">;
-            partialCoverage: boolean;
-            unsupportedReason?: string | undefined;
-        };
-        raw?: unknown;
-    } & {
-        [k: string]: {
-            supported: boolean;
-            ops: Record<string, "stub" | "polyfill" | "supported" | "unsupported" | "probe-inconclusive">;
-            partialCoverage: boolean;
-            unsupportedReason?: string | undefined;
-        };
-    };
-    packageName: string;
     schemaVersion: 1;
     frameworkId: string;
+    packageName: string;
     canonical: boolean;
     displayName: string;
     description: string;
     implementationMode: "from-scratch" | "extends-canonical" | "extends-other";
     entrypoint: {
-        sourceExtension: "cpp" | "ino" | "cc" | "h";
         entrypointFunctionName: string;
         requiresLoopFunction: boolean;
+        sourceExtension: "cpp" | "ino" | "cc" | "h";
         generateHeaderFile: boolean;
         overrideBaseName?: string | undefined;
         outputSubdirectory?: string | undefined;
         customBridgeShim?: string | undefined;
     };
     profile: {
+        targets: string[];
         forcedIncludes: string[];
         symbolAliases: Record<string, string>;
-        targets: string[];
     };
+    hal: Record<string, {
+        supported: boolean;
+        ops: Record<string, "unsupported" | "supported" | "polyfill" | "probe-inconclusive" | "stub">;
+        partialCoverage: boolean;
+        unsupportedReason?: string | undefined;
+    }>;
     polyfills: {
         emitted: {
             id: string;
@@ -59,20 +49,20 @@ declare const _default: {
         reexportedFrom?: string | undefined;
     };
     typeEmission: {
-        needsIostream: boolean;
+        normalizeCppType: boolean;
+        mathHeader: "<math.h>" | "none" | "<Arduino.h>";
         needsStdString: boolean;
         needsStdVector: boolean;
+        needsIostream: boolean;
         needsStdFunction: boolean;
-        mathHeader: "none" | "<math.h>" | "<Arduino.h>";
-        normalizeCppType: boolean;
         stdlibSupport: {
             hasVector: boolean;
             hasString: boolean;
             hasIostream: boolean;
             hasExceptions: boolean;
             hasRTTI: boolean;
-            recommendedArrayImpl: "std_vector" | "static_array";
-            recommendedStringImpl: "std_string" | "static_string";
+            recommendedArrayImpl: "static_array" | "std_vector";
+            recommendedStringImpl: "static_string" | "std_string";
         };
     };
     ambientTypes: string[];
@@ -80,12 +70,6 @@ declare const _default: {
         hardwareTestGroups: string[];
         halResolutionTests: string[];
     };
-    doctor?: {
-        available: boolean;
-    } | undefined;
-    licenses?: {
-        available: boolean;
-    } | undefined;
     basedOn?: string | undefined;
     inheritsStrategyId?: string | undefined;
     libraryResolution?: {
@@ -95,6 +79,12 @@ declare const _default: {
         tryGenerateLibDecl: boolean;
         reexportedFrom?: string | undefined;
     } | undefined;
+    doctor?: {
+        available: boolean;
+    } | undefined;
+    licenses?: {
+        available: boolean;
+    } | undefined;
     compat?: {
         zephyr?: string | undefined;
     } | undefined;

package/dist/framework.manifest.js

@@ -45,8 +45,16 @@ export default defineFrameworkManifest({
     profile: {
         // Informational list of supported board targets. The manifest validator
         // never iterates this; chipForTarget (src/chips/index.ts) is the real
-        // resolver. ESP32-S3 + plain ESP32 added alongside the nRF52840 MVP target.
-        targets: ['xiao_ble', 'esp32s3_devkitc', 'esp32_devkitc'],
+        // resolver. ESP32-S3 + plain ESP32 added alongside the nRF52840 MVP target;
+        // rpi_pico / rpi_pico2 / esp32c3 / esp32c6 / blackpill_f411ce resolve via
+        // the board packages' zephyr chip data (resolveChipFromBoard), not the
+        // hardcoded chip registry.
+        targets: [
+            'xiao_ble', 'esp32s3_devkitc', 'esp32_devkitc',
+            'rpi_pico', 'rpi_pico2/rp2350a/m33',
+            'esp32c3_devkitm/esp32c3', 'esp32c6_devkitc/esp32c6/hpcore',
+            'blackpill_f411ce/stm32f411xe',
+        ],
         forcedIncludes: ['<zephyr/kernel.h>', '<zephyr/drivers/gpio.h>', '<cstdint>'],
         symbolAliases: {},
     },
@@ -204,7 +212,8 @@ export default defineFrameworkManifest({
             },
         },
         // ── Partial: WiFi (STA connect + scan + config via conn_mgr/net_mgmt) ────
-        // ESP32-S3 only — profileDiagnostics flags wifi usage on radioless chips.
+        // ESP32 family only (esp32, esp32s3, esp32c3, esp32c6) — profileDiagnostics
+        // flags wifi usage on radioless chips (nRF52840, RP2040/RP2350).
         // AP mode, credential persistence, static IP, and event callbacks deferred.
         wifi: {
             supported: true,

package/dist/lowering/adc.d.ts

@@ -4,11 +4,14 @@ import type { ZephyrChipDescriptor } from '../chips/types.js';
 export declare function adcChannelForPin(chip: ZephyrChipDescriptor, pin: number): number;
 /**
  * Emit the per-channel ADC setup state. One block per channel in the chip
- * descriptor, each guarded by a `static bool __tc_adc<N>_ready` so the first
- * read configures it and subsequent reads skip. Called from shimLines when
- * the program uses ADC.
+ * descriptor that the PROGRAM ACTUALLY READS (`usedPins`) — an unread
+ * channel's `static` setup function would trip -Wunused-function in the
+ * single generated TU. When `usedPins` is omitted (probe paths with no
+ * program), every descriptor channel is emitted. Each block is guarded by a
+ * `static bool __tc_adc<N>_ready` so the first read configures it and
+ * subsequent reads skip. Called from shimLines when the program uses ADC.
  */
-export declare function adcInitLines(chip: ZephyrChipDescriptor): string[];
+export declare function adcInitLines(chip: ZephyrChipDescriptor, usedPins?: ReadonlySet<number>): string[];
 /**
  * Resolve a HAL adc.* op to Zephyr C++.
  * Returns `{ code }` for statement ops, `{ expression }` for value-returning ops.