@typeberry/lib 0.5.1-a4d7c93 → 0.5.1-eb84786

package/packages/core/pvm-interpreter/args-decoder/decoders/nibbles-decoder.test.js

@@ -0,0 +1,77 @@
+import assert from "node:assert";
+import { describe, it } from "node:test";
+import { NibblesDecoder } from "./nibbles-decoder.js";
+describe("NibblesDecoder", () => {
+    it("should decode high nibble from 0x79", () => {
+        const nibblesDecoder = new NibblesDecoder();
+        nibblesDecoder.setByte(0x79);
+        const registerValue = nibblesDecoder.getHighNibble();
+        assert.strictEqual(registerValue, 7);
+    });
+    it("should decode low nibble from 0x79", () => {
+        const nibblesDecoder = new NibblesDecoder();
+        nibblesDecoder.setByte(0x79);
+        const registerValue = nibblesDecoder.getLowNibble();
+        assert.strictEqual(registerValue, 9);
+    });
+    it("should not clamp high nibble", () => {
+        const nibblesDecoder = new NibblesDecoder();
+        nibblesDecoder.setByte(0xde);
+        const registerValue = nibblesDecoder.getHighNibble();
+        assert.strictEqual(registerValue, 13);
+    });
+    it("should not clamp low nibble", () => {
+        const nibblesDecoder = new NibblesDecoder();
+        nibblesDecoder.setByte(0xde);
+        const registerValue = nibblesDecoder.getLowNibble();
+        assert.strictEqual(registerValue, 14);
+    });
+    it("should decode high register index from 0x79", () => {
+        const nibblesDecoder = new NibblesDecoder();
+        nibblesDecoder.setByte(0x79);
+        const registerValue = nibblesDecoder.getHighNibbleAsRegisterIndex();
+        assert.strictEqual(registerValue, 7);
+    });
+    it("should decode low register index from 0x79", () => {
+        const nibblesDecoder = new NibblesDecoder();
+        nibblesDecoder.setByte(0x79);
+        const registerValue = nibblesDecoder.getLowNibbleAsRegisterIndex();
+        assert.strictEqual(registerValue, 9);
+    });
+    it("should clamp high register index", () => {
+        const nibblesDecoder = new NibblesDecoder();
+        nibblesDecoder.setByte(0xed);
+        const registerValue = nibblesDecoder.getHighNibbleAsRegisterIndex();
+        assert.strictEqual(registerValue, 12);
+    });
+    it("should clamp low register index", () => {
+        const nibblesDecoder = new NibblesDecoder();
+        nibblesDecoder.setByte(0xde);
+        const registerValue = nibblesDecoder.getLowNibbleAsRegisterIndex();
+        assert.strictEqual(registerValue, 12);
+    });
+    it("decode high length from 0x23", () => {
+        const nibblesDecoder = new NibblesDecoder();
+        nibblesDecoder.setByte(0x23);
+        const registerValue = nibblesDecoder.getHighNibbleAsRegisterIndex();
+        assert.strictEqual(registerValue, 2);
+    });
+    it("should decode low length from 0x23", () => {
+        const nibblesDecoder = new NibblesDecoder();
+        nibblesDecoder.setByte(0x23);
+        const registerValue = nibblesDecoder.getLowNibbleAsRegisterIndex();
+        assert.strictEqual(registerValue, 3);
+    });
+    it("should clamp high length", () => {
+        const nibblesDecoder = new NibblesDecoder();
+        nibblesDecoder.setByte(0xed);
+        const registerValue = nibblesDecoder.getHighNibbleAsLength();
+        assert.strictEqual(registerValue, 4);
+    });
+    it("should clamp low length", () => {
+        const nibblesDecoder = new NibblesDecoder();
+        nibblesDecoder.setByte(0xde);
+        const registerValue = nibblesDecoder.getLowNibbleAsLength();
+        assert.strictEqual(registerValue, 4);
+    });
+});

package/packages/core/pvm-interpreter/args-decoder/index.d.ts

@@ -0,0 +1,8 @@
+export * from "./args-decoder.js";
+export * from "./args-decoding-results.js";
+export * from "./argument-type.js";
+export * from "./decoders/extended-with-immediate-decoder.js";
+export * from "./decoders/immediate-decoder.js";
+export * from "./decoders/nibbles-decoder.js";
+export * from "./instruction-argument-type-map.js";
+//# sourceMappingURL=index.d.ts.map

package/packages/core/pvm-interpreter/args-decoder/index.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"index.d.ts","sourceRoot":"","sources":["../../../../../../packages/core/pvm-interpreter/args-decoder/index.ts"],"names":[],"mappings":"AAAA,cAAc,mBAAmB,CAAC;AAClC,cAAc,4BAA4B,CAAC;AAC3C,cAAc,oBAAoB,CAAC;AACnC,cAAc,+CAA+C,CAAC;AAC9D,cAAc,iCAAiC,CAAC;AAChD,cAAc,+BAA+B,CAAC;AAC9C,cAAc,oCAAoC,CAAC"}

package/packages/core/pvm-interpreter/args-decoder/index.js

@@ -0,0 +1,7 @@
+export * from "./args-decoder.js";
+export * from "./args-decoding-results.js";
+export * from "./argument-type.js";
+export * from "./decoders/extended-with-immediate-decoder.js";
+export * from "./decoders/immediate-decoder.js";
+export * from "./decoders/nibbles-decoder.js";
+export * from "./instruction-argument-type-map.js";

package/packages/core/pvm-interpreter/args-decoder/instruction-argument-type-map.d.ts

@@ -0,0 +1,3 @@
+import { ArgumentType } from "./argument-type.js";
+export declare const instructionArgumentTypeMap: ArgumentType[];
+//# sourceMappingURL=instruction-argument-type-map.d.ts.map

package/packages/core/pvm-interpreter/args-decoder/instruction-argument-type-map.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"instruction-argument-type-map.d.ts","sourceRoot":"","sources":["../../../../../../packages/core/pvm-interpreter/args-decoder/instruction-argument-type-map.ts"],"names":[],"mappings":"AACA,OAAO,EAAE,YAAY,EAAE,MAAM,oBAAoB,CAAC;AAElD,eAAO,MAAM,0BAA0B,gBA4JnC,CAAC"}

package/packages/core/pvm-interpreter/args-decoder/instruction-argument-type-map.js

@@ -0,0 +1,145 @@
+import { HIGHEST_INSTRUCTION_NUMBER, Instruction } from "../instruction.js";
+import { ArgumentType } from "./argument-type.js";
+export const instructionArgumentTypeMap = (() => {
+    const instructionArgumentTypeMap = new Array(HIGHEST_INSTRUCTION_NUMBER + 1);
+    instructionArgumentTypeMap[Instruction.TRAP] = ArgumentType.NO_ARGUMENTS;
+    instructionArgumentTypeMap[Instruction.FALLTHROUGH] = ArgumentType.NO_ARGUMENTS;
+    instructionArgumentTypeMap[Instruction.ECALLI] = ArgumentType.ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.LOAD_IMM_64] = ArgumentType.ONE_REGISTER_ONE_EXTENDED_WIDTH_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.STORE_IMM_U8] = ArgumentType.TWO_IMMEDIATES;
+    instructionArgumentTypeMap[Instruction.STORE_IMM_U16] = ArgumentType.TWO_IMMEDIATES;
+    instructionArgumentTypeMap[Instruction.STORE_IMM_U32] = ArgumentType.TWO_IMMEDIATES;
+    instructionArgumentTypeMap[Instruction.STORE_IMM_U64] = ArgumentType.TWO_IMMEDIATES;
+    instructionArgumentTypeMap[Instruction.JUMP] = ArgumentType.ONE_OFFSET;
+    instructionArgumentTypeMap[Instruction.JUMP_IND] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.LOAD_IMM] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.LOAD_U8] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.LOAD_I8] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.LOAD_U16] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.LOAD_I16] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.LOAD_U32] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.LOAD_I32] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.LOAD_U64] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.STORE_U8] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.STORE_U16] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.STORE_U32] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.STORE_U64] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.STORE_IMM_IND_U8] = ArgumentType.ONE_REGISTER_TWO_IMMEDIATES;
+    instructionArgumentTypeMap[Instruction.STORE_IMM_IND_U16] = ArgumentType.ONE_REGISTER_TWO_IMMEDIATES;
+    instructionArgumentTypeMap[Instruction.STORE_IMM_IND_U32] = ArgumentType.ONE_REGISTER_TWO_IMMEDIATES;
+    instructionArgumentTypeMap[Instruction.STORE_IMM_IND_U64] = ArgumentType.ONE_REGISTER_TWO_IMMEDIATES;
+    instructionArgumentTypeMap[Instruction.LOAD_IMM_JUMP] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE_ONE_OFFSET;
+    instructionArgumentTypeMap[Instruction.BRANCH_EQ_IMM] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE_ONE_OFFSET;
+    instructionArgumentTypeMap[Instruction.BRANCH_NE_IMM] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE_ONE_OFFSET;
+    instructionArgumentTypeMap[Instruction.BRANCH_LT_U_IMM] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE_ONE_OFFSET;
+    instructionArgumentTypeMap[Instruction.BRANCH_LE_U_IMM] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE_ONE_OFFSET;
+    instructionArgumentTypeMap[Instruction.BRANCH_GE_U_IMM] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE_ONE_OFFSET;
+    instructionArgumentTypeMap[Instruction.BRANCH_GT_U_IMM] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE_ONE_OFFSET;
+    instructionArgumentTypeMap[Instruction.BRANCH_LT_S_IMM] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE_ONE_OFFSET;
+    instructionArgumentTypeMap[Instruction.BRANCH_LE_S_IMM] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE_ONE_OFFSET;
+    instructionArgumentTypeMap[Instruction.BRANCH_GE_S_IMM] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE_ONE_OFFSET;
+    instructionArgumentTypeMap[Instruction.BRANCH_GT_S_IMM] = ArgumentType.ONE_REGISTER_ONE_IMMEDIATE_ONE_OFFSET;
+    instructionArgumentTypeMap[Instruction.MOVE_REG] = ArgumentType.TWO_REGISTERS;
+    instructionArgumentTypeMap[Instruction.SBRK] = ArgumentType.TWO_REGISTERS;
+    instructionArgumentTypeMap[Instruction.COUNT_SET_BITS_64] = ArgumentType.TWO_REGISTERS;
+    instructionArgumentTypeMap[Instruction.COUNT_SET_BITS_32] = ArgumentType.TWO_REGISTERS;
+    instructionArgumentTypeMap[Instruction.LEADING_ZERO_BITS_64] = ArgumentType.TWO_REGISTERS;
+    instructionArgumentTypeMap[Instruction.LEADING_ZERO_BITS_32] = ArgumentType.TWO_REGISTERS;
+    instructionArgumentTypeMap[Instruction.TRAILING_ZERO_BITS_64] = ArgumentType.TWO_REGISTERS;
+    instructionArgumentTypeMap[Instruction.TRAILING_ZERO_BITS_32] = ArgumentType.TWO_REGISTERS;
+    instructionArgumentTypeMap[Instruction.SIGN_EXTEND_8] = ArgumentType.TWO_REGISTERS;
+    instructionArgumentTypeMap[Instruction.SIGN_EXTEND_16] = ArgumentType.TWO_REGISTERS;
+    instructionArgumentTypeMap[Instruction.ZERO_EXTEND_16] = ArgumentType.TWO_REGISTERS;
+    instructionArgumentTypeMap[Instruction.REVERSE_BYTES] = ArgumentType.TWO_REGISTERS;
+    instructionArgumentTypeMap[Instruction.STORE_IND_U8] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.STORE_IND_U16] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.STORE_IND_U32] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.STORE_IND_U64] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.LOAD_IND_U8] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.LOAD_IND_I8] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.LOAD_IND_U16] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.LOAD_IND_I16] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.LOAD_IND_U32] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.LOAD_IND_I32] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.LOAD_IND_U64] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.ADD_IMM_32] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.ADD_IMM_64] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.AND_IMM] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.XOR_IMM] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.OR_IMM] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.MUL_IMM_32] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.MUL_IMM_64] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.SET_LT_U_IMM] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.SET_LT_S_IMM] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.SHLO_L_IMM_32] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.SHLO_R_IMM_32] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.SHAR_R_IMM_32] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.NEG_ADD_IMM_32] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.SHLO_L_IMM_64] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.SHLO_R_IMM_64] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.SHAR_R_IMM_64] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.NEG_ADD_IMM_64] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.SET_GT_U_IMM] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.SET_GT_S_IMM] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.SHLO_L_IMM_ALT_32] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.SHLO_R_IMM_ALT_32] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.SHAR_R_IMM_ALT_32] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.SHLO_L_IMM_ALT_64] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.SHLO_R_IMM_ALT_64] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.SHAR_R_IMM_ALT_64] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.CMOV_IZ_IMM] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.CMOV_NZ_IMM] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.ROT_R_64_IMM] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.ROT_R_64_IMM_ALT] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.ROT_R_32_IMM] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.ROT_R_32_IMM_ALT] = ArgumentType.TWO_REGISTERS_ONE_IMMEDIATE;
+    instructionArgumentTypeMap[Instruction.BRANCH_EQ] = ArgumentType.TWO_REGISTERS_ONE_OFFSET;
+    instructionArgumentTypeMap[Instruction.BRANCH_NE] = ArgumentType.TWO_REGISTERS_ONE_OFFSET;
+    instructionArgumentTypeMap[Instruction.BRANCH_LT_U] = ArgumentType.TWO_REGISTERS_ONE_OFFSET;
+    instructionArgumentTypeMap[Instruction.BRANCH_LT_S] = ArgumentType.TWO_REGISTERS_ONE_OFFSET;
+    instructionArgumentTypeMap[Instruction.BRANCH_GE_U] = ArgumentType.TWO_REGISTERS_ONE_OFFSET;
+    instructionArgumentTypeMap[Instruction.BRANCH_GE_S] = ArgumentType.TWO_REGISTERS_ONE_OFFSET;
+    instructionArgumentTypeMap[Instruction.LOAD_IMM_JUMP_IND] = ArgumentType.TWO_REGISTERS_TWO_IMMEDIATES;
+    instructionArgumentTypeMap[Instruction.ADD_32] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.ADD_64] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.SUB_32] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.SUB_64] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.AND] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.XOR] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.OR] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.MUL_32] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.MUL_64] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.MUL_UPPER_S_S] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.MUL_UPPER_U_U] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.MUL_UPPER_S_U] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.DIV_U_32] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.DIV_S_32] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.REM_U_32] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.REM_S_32] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.DIV_U_64] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.DIV_S_64] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.REM_U_64] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.REM_S_64] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.SET_LT_U] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.SET_LT_S] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.SHLO_L_32] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.SHLO_R_32] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.SHAR_R_32] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.SHLO_L_64] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.SHLO_R_64] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.SHAR_R_64] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.CMOV_IZ] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.CMOV_NZ] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.ROT_L_64] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.ROT_L_32] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.ROT_R_64] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.ROT_R_32] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.AND_INV] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.OR_INV] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.XNOR] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.MAX] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.MAX_U] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.MIN] = ArgumentType.THREE_REGISTERS;
+    instructionArgumentTypeMap[Instruction.MIN_U] = ArgumentType.THREE_REGISTERS;
+    return instructionArgumentTypeMap;
+})();

package/packages/core/pvm-interpreter/args-decoder/instruction-argument-type-map.test.d.ts

@@ -0,0 +1,2 @@
+export {};
+//# sourceMappingURL=instruction-argument-type-map.test.d.ts.map

package/packages/core/pvm-interpreter/args-decoder/instruction-argument-type-map.test.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"instruction-argument-type-map.test.d.ts","sourceRoot":"","sources":["../../../../../../packages/core/pvm-interpreter/args-decoder/instruction-argument-type-map.test.ts"],"names":[],"mappings":""}

package/packages/core/pvm-interpreter/args-decoder/instruction-argument-type-map.test.js

@@ -0,0 +1,13 @@
+import assert from "node:assert";
+import { describe, it } from "node:test";
+import { Instruction } from "../instruction.js";
+import { instructionArgumentTypeMap } from "./instruction-argument-type-map.js";
+describe("instructionArgumentTypeMap", () => {
+    const instructions = Object.entries(Instruction).filter((entry) => typeof entry[0] === "string" && typeof entry[1] === "number");
+    for (const [name, instruction] of instructions) {
+        it(`checks if instruction ${name} = ${instruction} is correctly mapped to arguments type`, () => {
+            const argumentsType = instructionArgumentTypeMap[instruction];
+            assert.notEqual(null, argumentsType);
+        });
+    }
+});

package/packages/core/pvm-interpreter/assemblify.d.ts

@@ -0,0 +1,13 @@
+import { type SmallGas } from "#@typeberry/pvm-interface";
+import type { Mask } from "./program-decoder/mask.js";
+type Byte = number;
+type OpCode = {
+    gas: SmallGas;
+};
+type ByteToOpCodeMap = {
+    [key: Byte]: OpCode;
+};
+export declare const byteToOpCodeMap: ByteToOpCodeMap;
+export declare function assemblify(program: Uint8Array, mask: Mask): (string | number)[][];
+export {};
+//# sourceMappingURL=assemblify.d.ts.map

package/packages/core/pvm-interpreter/assemblify.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"assemblify.d.ts","sourceRoot":"","sources":["../../../../../packages/core/pvm-interpreter/assemblify.ts"],"names":[],"mappings":"AAAA,OAAO,EAAE,KAAK,QAAQ,EAAiB,MAAM,0BAA0B,CAAC;AAExE,OAAO,KAAK,EAAE,IAAI,EAAE,MAAM,2BAA2B,CAAC;AAEtD,KAAK,IAAI,GAAG,MAAM,CAAC;AA8LnB,KAAK,MAAM,GAAG;IACZ,GAAG,EAAE,QAAQ,CAAC;CACf,CAAC;AAIF,KAAK,eAAe,GAAG;IAAE,CAAC,GAAG,EAAE,IAAI,GAAG,MAAM,CAAA;CAAE,CAAC;AAE/C,eAAO,MAAM,eAAe,iBAIH,CAAC;AAE1B,wBAAgB,UAAU,CAAC,OAAO,EAAE,UAAU,EAAE,IAAI,EAAE,IAAI,yBAYzD"}

package/packages/core/pvm-interpreter/assemblify.js

@@ -0,0 +1,191 @@
+import { tryAsSmallGas } from "#@typeberry/pvm-interface";
+import { Instruction } from "./instruction.js";
+const instructionsWithoutArgs = [
+    [Instruction.TRAP, 1],
+    [Instruction.FALLTHROUGH, 1],
+];
+const instructionsWithOneImmediate = [[Instruction.ECALLI, 1]];
+const instructionsWithOneRegisterAndOneExtendedWidthImmediate = [[Instruction.LOAD_IMM_64, 1]];
+const instructionsWithTwoImmediates = [
+    [Instruction.STORE_IMM_U8, 1],
+    [Instruction.STORE_IMM_U16, 1],
+    [Instruction.STORE_IMM_U32, 1],
+    [Instruction.STORE_IMM_U64, 1],
+];
+const instructionsWithOneOffset = [[Instruction.JUMP, 1]];
+const instructionsWithOneRegisterAndOneImmediate = [
+    [Instruction.JUMP_IND, 1],
+    [Instruction.LOAD_IMM, 1],
+    [Instruction.LOAD_U8, 1],
+    [Instruction.LOAD_I8, 1],
+    [Instruction.LOAD_U16, 1],
+    [Instruction.LOAD_I16, 1],
+    [Instruction.LOAD_U32, 1],
+    [Instruction.LOAD_I32, 1],
+    [Instruction.LOAD_U64, 1],
+    [Instruction.STORE_U8, 1],
+    [Instruction.STORE_U16, 1],
+    [Instruction.STORE_U32, 1],
+    [Instruction.STORE_U64, 1],
+];
+const instructionsWithOneRegisterAndTwoImmediate = [
+    [Instruction.STORE_IMM_IND_U8, 1],
+    [Instruction.STORE_IMM_IND_U16, 1],
+    [Instruction.STORE_IMM_IND_U32, 1],
+    [Instruction.STORE_IMM_IND_U64, 1],
+];
+const instructionsWithOneRegisterOneImmediateAndOneOffset = [
+    [Instruction.LOAD_IMM_JUMP, 1],
+    [Instruction.BRANCH_EQ_IMM, 1],
+    [Instruction.BRANCH_NE_IMM, 1],
+    [Instruction.BRANCH_LT_U_IMM, 1],
+    [Instruction.BRANCH_LE_U_IMM, 1],
+    [Instruction.BRANCH_GE_U_IMM, 1],
+    [Instruction.BRANCH_GT_U_IMM, 1],
+    [Instruction.BRANCH_LT_S_IMM, 1],
+    [Instruction.BRANCH_LE_S_IMM, 1],
+    [Instruction.BRANCH_GE_S_IMM, 1],
+    [Instruction.BRANCH_GT_S_IMM, 1],
+];
+const instructionsWithTwoRegisters = [
+    [Instruction.MOVE_REG, 1],
+    [Instruction.SBRK, 1],
+    [Instruction.COUNT_SET_BITS_64, 1],
+    [Instruction.COUNT_SET_BITS_32, 1],
+    [Instruction.LEADING_ZERO_BITS_64, 1],
+    [Instruction.LEADING_ZERO_BITS_32, 1],
+    [Instruction.TRAILING_ZERO_BITS_64, 1],
+    [Instruction.TRAILING_ZERO_BITS_32, 1],
+    [Instruction.SIGN_EXTEND_8, 1],
+    [Instruction.SIGN_EXTEND_16, 1],
+    [Instruction.ZERO_EXTEND_16, 1],
+    [Instruction.REVERSE_BYTES, 1],
+];
+const instructionsWithTwoRegistersAndOneImmediate = [
+    [Instruction.STORE_IND_U8, 1],
+    [Instruction.STORE_IND_U16, 1],
+    [Instruction.STORE_IND_U32, 1],
+    [Instruction.STORE_IND_U64, 1],
+    [Instruction.LOAD_IND_U8, 1],
+    [Instruction.LOAD_IND_I8, 1],
+    [Instruction.LOAD_IND_U16, 1],
+    [Instruction.LOAD_IND_I16, 1],
+    [Instruction.LOAD_IND_U32, 1],
+    [Instruction.LOAD_IND_I32, 1],
+    [Instruction.LOAD_IND_U64, 1],
+    [Instruction.ADD_IMM_32, 1],
+    [Instruction.AND_IMM, 1],
+    [Instruction.XOR_IMM, 1],
+    [Instruction.OR_IMM, 1],
+    [Instruction.MUL_IMM_32, 1],
+    [Instruction.SET_LT_U_IMM, 1],
+    [Instruction.SET_LT_S_IMM, 1],
+    [Instruction.SHLO_L_IMM_32, 1],
+    [Instruction.SHLO_R_IMM_32, 1],
+    [Instruction.SHAR_R_IMM_32, 1],
+    [Instruction.NEG_ADD_IMM_32, 1],
+    [Instruction.SET_GT_U_IMM, 1],
+    [Instruction.SET_GT_S_IMM, 1],
+    [Instruction.SHLO_L_IMM_ALT_32, 1],
+    [Instruction.SHLO_R_IMM_ALT_32, 1],
+    [Instruction.SHAR_R_IMM_ALT_32, 1],
+    [Instruction.CMOV_IZ_IMM, 1],
+    [Instruction.CMOV_NZ_IMM, 1],
+    [Instruction.ADD_IMM_64, 1],
+    [Instruction.MUL_IMM_64, 1],
+    [Instruction.SHLO_L_IMM_64, 1],
+    [Instruction.SHLO_R_IMM_64, 1],
+    [Instruction.SHAR_R_IMM_64, 1],
+    [Instruction.NEG_ADD_IMM_64, 1],
+    [Instruction.SHLO_L_IMM_ALT_64, 1],
+    [Instruction.SHLO_R_IMM_ALT_64, 1],
+    [Instruction.SHAR_R_IMM_ALT_64, 1],
+    [Instruction.ROT_R_64_IMM, 1],
+    [Instruction.ROT_R_64_IMM_ALT, 1],
+    [Instruction.ROT_R_32_IMM, 1],
+    [Instruction.ROT_R_32_IMM_ALT, 1],
+];
+const instructionsWithTwoRegistersAndOneOffset = [
+    [Instruction.BRANCH_EQ, 1],
+    [Instruction.BRANCH_NE, 1],
+    [Instruction.BRANCH_LT_U, 1],
+    [Instruction.BRANCH_LT_S, 1],
+    [Instruction.BRANCH_GE_U, 1],
+    [Instruction.BRANCH_GE_S, 1],
+];
+const instructionWithTwoRegistersAndTwoImmediates = [[Instruction.LOAD_IMM_JUMP_IND, 1]];
+const instructionsWithThreeRegisters = [
+    [Instruction.ADD_32, 1],
+    [Instruction.SUB_32, 1],
+    [Instruction.MUL_32, 1],
+    [Instruction.DIV_U_32, 1],
+    [Instruction.DIV_S_32, 1],
+    [Instruction.REM_U_32, 1],
+    [Instruction.REM_S_32, 1],
+    [Instruction.SHLO_L_32, 1],
+    [Instruction.SHLO_R_32, 1],
+    [Instruction.SHAR_R_32, 1],
+    [Instruction.ADD_64, 1],
+    [Instruction.SUB_64, 1],
+    [Instruction.MUL_64, 1],
+    [Instruction.DIV_U_64, 1],
+    [Instruction.DIV_S_64, 1],
+    [Instruction.REM_U_64, 1],
+    [Instruction.REM_S_64, 1],
+    [Instruction.SHLO_L_64, 1],
+    [Instruction.SHLO_R_64, 1],
+    [Instruction.SHAR_R_64, 1],
+    [Instruction.AND, 1],
+    [Instruction.XOR, 1],
+    [Instruction.OR, 1],
+    [Instruction.MUL_UPPER_S_S, 1],
+    [Instruction.MUL_UPPER_U_U, 1],
+    [Instruction.MUL_UPPER_S_U, 1],
+    [Instruction.SET_LT_U, 1],
+    [Instruction.SET_LT_S, 1],
+    [Instruction.CMOV_IZ, 1],
+    [Instruction.CMOV_NZ, 1],
+    [Instruction.ROT_L_64, 1],
+    [Instruction.ROT_L_32, 1],
+    [Instruction.ROT_R_64, 1],
+    [Instruction.ROT_R_32, 1],
+    [Instruction.AND_INV, 1],
+    [Instruction.OR_INV, 1],
+    [Instruction.XNOR, 1],
+    [Instruction.MAX, 1],
+    [Instruction.MAX_U, 1],
+    [Instruction.MIN, 1],
+    [Instruction.MIN_U, 1],
+];
+const instructions = [
+    ...instructionsWithoutArgs,
+    ...instructionsWithOneImmediate,
+    ...instructionsWithOneRegisterAndOneExtendedWidthImmediate,
+    ...instructionsWithTwoImmediates,
+    ...instructionsWithOneOffset,
+    ...instructionsWithOneRegisterAndOneImmediate,
+    ...instructionsWithOneRegisterAndTwoImmediate,
+    ...instructionsWithOneRegisterOneImmediateAndOneOffset,
+    ...instructionsWithTwoRegisters,
+    ...instructionsWithTwoRegistersAndOneImmediate,
+    ...instructionsWithTwoRegistersAndOneOffset,
+    ...instructionWithTwoRegistersAndTwoImmediates,
+    ...instructionsWithThreeRegisters,
+];
+const createOpCodeEntry = ([byte, gas]) => [byte, { gas: tryAsSmallGas(gas) }];
+export const byteToOpCodeMap = instructions.reduce((acc, instruction) => {
+    const [byte, opCode] = createOpCodeEntry(instruction);
+    acc[byte] = opCode;
+    return acc;
+}, {});
+export function assemblify(program, mask) {
+    return program.reduce((acc, byte, index) => {
+        if (mask.isInstruction(index)) {
+            acc.push([Instruction[byte]]);
+        }
+        else {
+            acc[acc.length - 1].push(byte);
+        }
+        return acc;
+    }, []);
+}

package/packages/core/pvm-interpreter/basic-blocks/basic-blocks.d.ts

@@ -0,0 +1,7 @@
+import type { Mask } from "../program-decoder/mask.js";
+export declare class BasicBlocks {
+    private basicBlocks;
+    reset(code: Uint8Array, mask: Mask): void;
+    isBeginningOfBasicBlock(index: number): boolean;
+}
+//# sourceMappingURL=basic-blocks.d.ts.map

package/packages/core/pvm-interpreter/basic-blocks/basic-blocks.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"basic-blocks.d.ts","sourceRoot":"","sources":["../../../../../../packages/core/pvm-interpreter/basic-blocks/basic-blocks.ts"],"names":[],"mappings":"AAAA,OAAO,KAAK,EAAE,IAAI,EAAE,MAAM,4BAA4B,CAAC;AAGvD,qBAAa,WAAW;IACtB,OAAO,CAAC,WAAW,CAA0B;IAE7C,KAAK,CAAC,IAAI,EAAE,UAAU,EAAE,IAAI,EAAE,IAAI;IAelC,uBAAuB,CAAC,KAAK,EAAE,MAAM;CAGtC"}

package/packages/core/pvm-interpreter/basic-blocks/basic-blocks.js

@@ -0,0 +1,18 @@
+import { terminationInstructions } from "./is-termination-instruction.js";
+export class BasicBlocks {
+    basicBlocks = new Set();
+    reset(code, mask) {
+        this.basicBlocks.clear();
+        this.basicBlocks.add(0);
+        const codeLength = code.length;
+        const isBasicBlockTermination = (index) => mask.isInstruction(index) && terminationInstructions[code[index]];
+        for (let i = 0; i < codeLength; i++) {
+            if (mask.isInstruction(i) && isBasicBlockTermination(i)) {
+                this.basicBlocks.add(i + 1 + mask.getNoOfBytesToNextInstruction(i + 1));
+            }
+        }
+    }
+    isBeginningOfBasicBlock(index) {
+        return this.basicBlocks.has(index);
+    }
+}

package/packages/core/pvm-interpreter/basic-blocks/basic-blocks.test.d.ts

@@ -0,0 +1,2 @@
+export {};
+//# sourceMappingURL=basic-blocks.test.d.ts.map

package/packages/core/pvm-interpreter/basic-blocks/basic-blocks.test.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"basic-blocks.test.d.ts","sourceRoot":"","sources":["../../../../../../packages/core/pvm-interpreter/basic-blocks/basic-blocks.test.ts"],"names":[],"mappings":""}

package/packages/core/pvm-interpreter/basic-blocks/basic-blocks.test.js

@@ -0,0 +1,114 @@
+import assert from "node:assert";
+import { describe, it } from "node:test";
+import { BitVec } from "#@typeberry/bytes";
+import { Instruction } from "../instruction.js";
+import { Mask } from "../program-decoder/mask.js";
+import { BasicBlocks } from "./basic-blocks.js";
+describe("BasicBlocks", () => {
+    it("should return true for the first instruction even it is a termination block instruction", () => {
+        const code = new Uint8Array([Instruction.TRAP]);
+        const mask = new Mask(BitVec.fromBlob(new Uint8Array([0b0000_0001]), code.length));
+        const basicBlocks = new BasicBlocks();
+        basicBlocks.reset(code, mask);
+        const index = 0;
+        const result = basicBlocks.isBeginningOfBasicBlock(index);
+        assert.strictEqual(result, true);
+    });
+    it("should return true for the first instruction after a termination block instruction", () => {
+        const code = new Uint8Array([Instruction.TRAP, Instruction.ADD_32, 5, 7]);
+        const mask = new Mask(BitVec.fromBlob(new Uint8Array([0b0000_0011]), code.length));
+        const basicBlocks = new BasicBlocks();
+        basicBlocks.reset(code, mask);
+        const index = 1;
+        const result = basicBlocks.isBeginningOfBasicBlock(index);
+        assert.strictEqual(result, true);
+    });
+    it("should return false for the second instruction after a termination block instruction", () => {
+        const code = new Uint8Array([Instruction.TRAP, Instruction.ADD_32, 5, 7, Instruction.SUB_32, 5, 7]);
+        const mask = new Mask(BitVec.fromBlob(new Uint8Array([0b0001_0011]), code.length));
+        const basicBlocks = new BasicBlocks();
+        basicBlocks.reset(code, mask);
+        const index = 4;
+        const result = basicBlocks.isBeginningOfBasicBlock(index);
+        assert.strictEqual(result, false);
+    });
+    it("should return false for a termination block instruction that is not the first instruction in the program", () => {
+        const code = new Uint8Array([Instruction.TRAP, Instruction.ADD_32, 5, 7, Instruction.TRAP]);
+        const mask = new Mask(BitVec.fromBlob(new Uint8Array([0b0001_0011]), code.length));
+        const basicBlocks = new BasicBlocks();
+        basicBlocks.reset(code, mask);
+        const index = 4;
+        const result = basicBlocks.isBeginningOfBasicBlock(index);
+        assert.strictEqual(result, false);
+    });
+    it("should return true for a beginning of basic block instruction that is not the first instruction after a block termination instruction that has some args", () => {
+        const code = new Uint8Array([Instruction.BRANCH_EQ, 135, 25, Instruction.ADD_32, 5, 7, Instruction.TRAP]);
+        const mask = new Mask(BitVec.fromBlob(new Uint8Array([0b0100_1001]), code.length));
+        const basicBlocks = new BasicBlocks();
+        basicBlocks.reset(code, mask);
+        const index = 3;
+        const result = basicBlocks.isBeginningOfBasicBlock(index);
+        assert.strictEqual(result, true);
+    });
+    it("should return true for a termination block instruction that is the after a termination instruction", () => {
+        const code = new Uint8Array([Instruction.TRAP, Instruction.TRAP]);
+        const mask = new Mask(BitVec.fromBlob(new Uint8Array([0b0000_0011]), code.length));
+        const basicBlocks = new BasicBlocks();
+        basicBlocks.reset(code, mask);
+        const index = 1;
+        const result = basicBlocks.isBeginningOfBasicBlock(index);
+        assert.strictEqual(result, true);
+    });
+    it("should return false for a negative number", () => {
+        const code = new Uint8Array([Instruction.TRAP, Instruction.TRAP]);
+        const mask = new Mask(BitVec.fromBlob(new Uint8Array([0b0000_0011]), code.length));
+        const basicBlocks = new BasicBlocks();
+        basicBlocks.reset(code, mask);
+        const index = -1;
+        const result = basicBlocks.isBeginningOfBasicBlock(index);
+        assert.strictEqual(result, false);
+    });
+    it("should correctly detect basic blocks when distance between instructions is longer than 24", () => {
+        const code = new Uint8Array([
+            Instruction.TRAP,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            0,
+            Instruction.JUMP_IND,
+        ]);
+        const mask = new Mask(BitVec.fromBlob(new Uint8Array([0b0000_0001, 0b0000_0000, 0b0000_0000, 0b1000_0000]), 32));
+        const basicBlocks = new BasicBlocks();
+        basicBlocks.reset(code, mask);
+        const expectedStartingBasicBlockIndices = [0, 26];
+        for (let i = 0; i < 32; i++) {
+            assert.strictEqual(basicBlocks.isBeginningOfBasicBlock(i), expectedStartingBasicBlockIndices.includes(i));
+        }
+    });
+});

package/packages/core/pvm-interpreter/basic-blocks/index.d.ts

@@ -0,0 +1,2 @@
+export { BasicBlocks } from "./basic-blocks.js";
+//# sourceMappingURL=index.d.ts.map

package/packages/core/pvm-interpreter/basic-blocks/index.d.ts.map

@@ -0,0 +1 @@
+{"version":3,"file":"index.d.ts","sourceRoot":"","sources":["../../../../../../packages/core/pvm-interpreter/basic-blocks/index.ts"],"names":[],"mappings":"AAAA,OAAO,EAAE,WAAW,EAAE,MAAM,mBAAmB,CAAC"}

package/packages/core/pvm-interpreter/basic-blocks/index.js

@@ -0,0 +1 @@
+export { BasicBlocks } from "./basic-blocks.js";