@ttsc/win32-arm64 0.33.0 → 0.34.0

package/bin/go/src/simd/archsimd/_gen/simdgen/ops/Moves/go_arm64.yaml

@@ -0,0 +1,264 @@
+!sum
+
+# GetElem VMOV (UMOV, integer)
+- go: GetElem
+  asm: "VMOV"
+  SSAVariant: "extr"
+  in:
+  - &immIndex
+    class: immediate
+    go: Immediate
+    name: index
+  - &vector
+    go: $t
+    base: int|uint
+  out:
+  - &scalar
+    class: greg
+
+# GetElem VDUP (duplicate element into scalar float in vreg)
+- go: GetElem
+  asm: "VDUP"
+  SSAVariant: "extr"
+  in:
+  - *immIndex
+  - &fvector
+    go: $t
+    base: float
+  out:
+  - &fscalarOut
+    class: vreg
+    treatLikeAScalarOfSize: 0
+    OverwriteClass: greg
+    OverwriteBase: float
+
+# SetElem VMOV (INS, integer)
+- go: SetElem
+  asm: "VMOV"
+  SSAVariant: "ins"
+  in:
+  - *immIndex
+  - *vector
+  - *scalar
+  out:
+  - *vector
+
+# SetElem VMOV (float: INS from the lane 0 of the source)
+- go: SetElem
+  asm: "VMOV"
+  SSAVariant: "ins0"
+  specialLower: !string "match (%h [0] (VMOVI16B [0]) y:(VDUP%sextr [i] _)) => y"
+  in:
+  - *immIndex
+  - &imm0
+    class: immediate
+    go: Immediate
+    const: 0 # imm+vreg with treatLikeAScalarOfSize are treated as scalar in lane 0
+  - *fvector
+  - &fscalarIn
+    class: vreg
+    treatLikeAScalarOfSize: 0
+  out:
+  - *fvector
+
+# broadcast1To16 VDUP (duplicate element 0 to all 16 byte lanes)
+- go: broadcast1To16
+  asm: "VDUP"
+  SSAVariant: "bcast"
+  constImm: 0
+  specialLower: !string "match (%h [i] (VMOV%sins [j] _ (MOVDconst [c]))) && i == j && c>=-128 && c<=255 => (VMOVI%a [uint8(c)])"
+  in:
+  - &immLane0
+    name: "@" # tag "fully constant" (no aux field needed)
+    const: 0
+    class: immediate
+    go: Immediate
+  - &bcast8
+    go: $t
+    bits: 128
+    elemBits: 8
+  out:
+  - *bcast8
+
+# broadcast1To8 VDUP (duplicate element 0 to all 8 halfword lanes)
+- go: broadcast1To8
+  asm: "VDUP"
+  SSAVariant: "bcast"
+  constImm: 0
+  in:
+  - *immLane0
+  - &bcast16
+    go: $t
+    bits: 128
+    elemBits: 16
+  out:
+  - *bcast16
+
+# broadcast1To4 VDUP (duplicate element 0 to all 4 word lanes)
+- go: broadcast1To4
+  asm: "VDUP"
+  SSAVariant: "bcast"
+  constImm: 0
+  in:
+  - *immLane0
+  - &bcast32
+    go: $t
+    bits: 128
+    elemBits: 32
+  out:
+  - *bcast32
+
+# broadcast1To2 VDUP (duplicate element 0 to both doubleword lanes)
+- go: broadcast1To2
+  asm: "VDUP"
+  SSAVariant: "bcast"
+  constImm: 0
+  in:
+  - *immLane0
+  - &bcast64
+    go: $t
+    bits: 128
+    elemBits: 64
+  out:
+  - *bcast64
+
+# bitSelect — VBIF (bit insert if false, internal)
+# Only Int8x16 is needed since VBIF operates on the full 128-bit register.
+# Other types cast to Int8x16 before calling bitSelect.
+- go: bitSelect
+  asm: "VBIF"
+  specialLower: !string "match (%h x y (VNOT16B mask)) => (VBIT16B x y mask)"
+  in:
+  - &v8
+    go: $t
+    class: vreg
+    base: int
+    elemBits: 8
+  - *v8
+  - &maskReg
+    class: vreg
+    base: int
+    name: mask
+  out:
+  - *v8
+
+# bitSelectNot — VBIT (bit insert if true, internal)
+- go: bitSelectNot
+  asm: "VBIT"
+  specialLower: !string "match (%h x y (VNOT16B mask)) => (VBIF16B x y mask)"
+  in:
+  - *v8
+  - *v8
+  - *maskReg
+  out:
+  - *v8
+
+# LookupOrZero — TBL (table lookup, zeros for out-of-range indices)
+- go: LookupOrZero
+  regexpTag: "move"
+  asm: "VTBL"
+  in:
+  - &bytesTable
+    go: $t
+    base: int|uint
+    elemBits: 8
+    name: table
+  - &byteIndices
+    go: $t
+    base: int|uint
+    elemBits: 8
+    name: indices
+  out:
+  - &bytes
+    go: $t
+    base: int|uint
+    elemBits: 8
+
+# LookupOrKeep — TBX (table lookup extended, keeps original for out-of-range)
+- go: lookupOrKeep
+  noGenericOps: "true"
+  regexpTag: "move"
+  asm: "VTBX"
+  in:
+  - &bytesKeep
+    go: $t
+    base: int|uint
+    elemBits: 8
+    name: keep
+  - *bytesTable
+  - *byteIndices
+  out:
+  - *bytes
+
+# ConcatShiftBytesRight — EXT (extract bytes from concatenated pair)
+- go: ConcatShiftBytesRight
+  asm: "VEXT"
+  operandOrder: 2I
+  in:
+  - class: immediate
+    immOffset: 0
+    name: shift
+  - &uint8x128
+    go: $t
+    base: uint
+    bits: 128
+    elemBits: 8
+  - *uint8x128
+  out:
+  - *uint8x128
+
+# InterleaveLo — ZIP1 (interleave low halves)
+- go: InterleaveLo
+  asm: "VZIP1"
+  in:
+  - &any128
+    go: $t
+    bits: 128
+  - *any128
+  out:
+  - *any128
+
+# InterleaveHi — ZIP2 (interleave high halves)
+- go: InterleaveHi
+  asm: "VZIP2"
+  in:
+  - *any128
+  - *any128
+  out:
+  - *any128
+
+# ConcatEven — UZP1 (extract even-indexed elements)
+- go: ConcatEven
+  asm: "VUZP1"
+  in:
+  - *any128
+  - *any128
+  out:
+  - *any128
+
+# ConcatOdd — UZP2 (extract odd-indexed elements)
+- go: ConcatOdd
+  asm: "VUZP2"
+  in:
+  - *any128
+  - *any128
+  out:
+  - *any128
+
+# InterleaveEven — TRN1 (transpose even-position pairs)
+- go: InterleaveEven
+  asm: "VTRN1"
+  in:
+  - *any128
+  - *any128
+  out:
+  - *any128
+
+# InterleaveOdd — TRN2 (transpose odd-position pairs)
+- go: InterleaveOdd
+  asm: "VTRN2"
+  in:
+  - *any128
+  - *any128
+  out:
+  - *any128

package/bin/go/src/simd/archsimd/_gen/simdgen/ops/Mul/categories.yaml

@@ -2,8 +2,8 @@
 - go: Mul
   commutative: true
   documentation: !string |-
-    // NAME multiplies corresponding elements of two vectors.
-- go: MulEvenWiden
+    // NAME multiplies corresponding elements of two vectors, modulo 2ⁿ.
+- go: MulWidenEven
   commutative: true
   documentation: !string |-
     // NAME multiplies even-indexed elements, widening the result.
@@ -12,3 +12,7 @@
   commutative: true
   documentation: !string |-
     // NAME multiplies elements and stores the high part of the result.
+- go: MulWidenLo
+  commutative: true
+  documentation: !string |-
+    // NAME multiplies corresponding low-indexed elements and produces a result with double the element width.

package/bin/go/src/simd/archsimd/_gen/simdgen/ops/Mul/{go.yaml → go_amd64.yaml}

@@ -13,9 +13,9 @@
 
 # Integer multiplications.
 
-# MulEvenWiden
+# MulWidenEven
 # Dword only.
-- go: MulEvenWiden
+- go: MulWidenEven
   asm: "VPMULDQ"
   in:
   - &intNot64
@@ -27,7 +27,7 @@
   - &int2
     go: $t2
     base: int
-- go: MulEvenWiden
+- go: MulWidenEven
   asm: "VPMULUDQ"
   in:
   - &uintNot64

package/bin/go/src/simd/archsimd/_gen/simdgen/ops/Mul/go_arm64.yaml

@@ -0,0 +1,38 @@
+!sum
+- go: Mul
+  asm: "VMUL|VFMUL"
+  in:
+  - &any
+    go: $t
+    elemBits: 8|16|32|64
+  - *any
+  out:
+  - *any
+
+# Multiply long signed (SMULL)
+- go: MulWidenLo
+  signed: true
+  asm: "VSMULL"
+  hiHalfAsm: "VSMULL2"
+  in:
+  - go: $t
+    base: int
+  - go: $t
+    base: int
+  out:
+  - go: $u
+    base: int
+
+# Multiply long unsigned (UMULL)
+- go: MulWidenLo
+  signed: false
+  asm: "VUMULL"
+  hiHalfAsm: "VUMULL2"
+  in:
+  - go: $t
+    base: uint
+  - go: $t
+    base: uint
+  out:
+  - go: $u
+    base: uint

package/bin/go/src/simd/archsimd/_gen/simdgen/ops/NegAbs/categories.yaml

@@ -0,0 +1,7 @@
+!sum
+- go: Neg
+  commutative: false
+  documentation: !string |-
+    // NAME returns the elementwise negation of x.
+
+# TODO: move Abs here from IntOnlyArith; on ARM64 it applies to float types too.

package/bin/go/src/simd/archsimd/_gen/simdgen/ops/NegAbs/go_arm64.yaml

@@ -0,0 +1,36 @@
+!sum
+# Signed integer Neg — VNEG
+- go: Neg
+  asm: "VNEG"
+  in:
+  - &int
+    go: $t
+    base: int
+  out:
+  - *int
+
+# Float Neg — VFNEG
+- go: Neg
+  asm: "VFNEG"
+  in:
+  - &float
+    go: $t
+    base: float
+  out:
+  - *float
+
+# Signed integer Abs — VABS
+- go: Abs
+  asm: "VABS"
+  in:
+  - *int
+  out:
+  - *int
+
+# Float Abs — VFABS
+- go: Abs
+  asm: "VFABS"
+  in:
+  - *float
+  out:
+  - *float

package/bin/go/src/simd/archsimd/_gen/simdgen/ops/Others/categories.yaml

@@ -3,6 +3,10 @@
   commutative: false
   documentation: !string |-
     // NAME counts the leading zeros of each element in x.
+- go: LeadingSignBits
+  commutative: false
+  documentation: !string |-
+    // NAME counts the leading sign bits of each element in x.
 - go: AESEncryptOneRound
   commutative: false
   documentation: !string |-
@@ -105,4 +109,4 @@
     // NAME does the sigma and addition of 3 in SHA256 algorithm defined in FIPS 180-4.
     // x = result of 2
     // y = {0, 0, W14, W15}
-    // result = {W16, W17, W18, W19}
+    // result = {W16, W17, W18, W19}

package/bin/go/src/simd/archsimd/_gen/simdgen/ops/Others/go_arm64.yaml

@@ -0,0 +1,19 @@
+!sum
+
+# Count leading zeros per element — VCLZ
+- go: LeadingZeros
+  asm: "VCLZ"
+  in:
+  - &any
+    go: $t
+    elemBits: 8|16|32
+  out:
+  - *any
+
+# Count leading sign bits per element — VCLS
+- go: LeadingSignBits
+  asm: "VCLS"
+  in:
+  - *any
+  out:
+  - *any

package/bin/go/src/simd/archsimd/_gen/simdgen/ops/Reduce/categories.yaml

@@ -0,0 +1,16 @@
+!sum
+- go: reduceSum
+  commutative: false
+  documentation: !string |-
+    // NAME reduces x by summing all elements. The sum is placed in element 0
+    // of the result; other elements are zeroed.
+- go: reduceMax
+  commutative: false
+  documentation: !string |-
+    // NAME reduces x by taking the maximum of all elements. The maximum is placed
+    // in element 0 of the result; other elements are zeroed.
+- go: reduceMin
+  commutative: false
+  documentation: !string |-
+    // NAME reduces x by taking the minimum of all elements. The minimum is placed
+    // in element 0 of the result; other elements are zeroed.

package/bin/go/src/simd/archsimd/_gen/simdgen/ops/Reduce/go_arm64.yaml

@@ -0,0 +1,71 @@
+!sum
+
+# Sum all elements — VADDV (integer)
+- go: reduceSum
+  asm: "VADDV"
+  in:
+  - &any
+    go: $t
+    base: int|uint
+  out:
+  - &scalarOut
+    go: $t
+    treatLikeAScalarOfSize: 0
+
+# Max of all elements — VSMAXV (signed)
+- go: reduceMax
+  signed: true
+  asm: "VSMAXV"
+  in:
+  - &int
+    go: $t
+    base: int
+  out:
+  - *scalarOut
+
+# Max of all elements — VUMAXV (unsigned)
+- go: reduceMax
+  signed: false
+  asm: "VUMAXV"
+  in:
+  - &uint
+    go: $t
+    base: uint
+  out:
+  - *scalarOut
+
+# Max of all elements — VFMAXV (float32)
+- go: reduceMax
+  asm: "VFMAXV"
+  in:
+  - &fp
+    go: $t
+    base: float
+  out:
+  - *scalarOut
+
+# Min of all elements — VSMINV (signed)
+- go: reduceMin
+  signed: true
+  asm: "VSMINV"
+  in:
+  - *int
+  out:
+  - *scalarOut
+
+# Min of all elements — VUMINV (unsigned)
+- go: reduceMin
+  signed: false
+  asm: "VUMINV"
+  in:
+  - *uint
+  out:
+  - *scalarOut
+
+# Min of all elements — VFMINV (float32)
+- go: reduceMin
+  asm: "VFMINV"
+  in:
+  - *fp
+  out:
+  - *scalarOut