@tscircuit/schematic-trace-solver 0.0.91 → 0.0.93

package/tests/repros/assets/repro-rectifier-trace-overlap.input.json

@@ -0,0 +1,137 @@
+{
+  "chips": [
+    {
+      "chipId": "schematic_component_0",
+      "center": {
+        "x": 0,
+        "y": 0
+      },
+      "width": 1.08,
+      "height": 0.818910699999999,
+      "pins": [
+        {
+          "pinId": "V1.1",
+          "x": -0.54,
+          "y": -0.0050000000000000044,
+          "_facingDirection": "x-"
+        },
+        {
+          "pinId": "V1.2",
+          "x": 0.54,
+          "y": 0.0049999999999999975,
+          "_facingDirection": "x+"
+        }
+      ]
+    },
+    {
+      "chipId": "schematic_component_1",
+      "center": {
+        "x": 0.019999999999999796,
+        "y": 1.4194553499999993
+      },
+      "width": 1.04,
+      "height": 0.6799999999999999,
+      "pins": [
+        {
+          "pinId": "D1.1",
+          "x": -0.5000000000000002,
+          "y": 1.3494553499999995,
+          "_facingDirection": "x-"
+        },
+        {
+          "pinId": "D1.2",
+          "x": 0.5399999999999998,
+          "y": 1.3494553499999995,
+          "_facingDirection": "x+"
+        }
+      ]
+    },
+    {
+      "chipId": "schematic_component_2",
+      "center": {
+        "x": 2.8400000000000003,
+        "y": 0.004999999999999449
+      },
+      "width": 0.5999999999999996,
+      "height": 0.6799999999999999,
+      "pins": [
+        {
+          "pinId": "R1.1",
+          "x": 3.14,
+          "y": 0.004999999999999413,
+          "_facingDirection": "x+"
+        },
+        {
+          "pinId": "R1.2",
+          "x": 2.5400000000000005,
+          "y": 0.004999999999999486,
+          "_facingDirection": "x-"
+        }
+      ]
+    },
+    {
+      "chipId": "schematic_component_3",
+      "center": {
+        "x": 1.54,
+        "y": 0.004999999999999893
+      },
+      "width": 0.6000000000000001,
+      "height": 0.84,
+      "pins": [
+        {
+          "pinId": "C1.1",
+          "x": 1.84,
+          "y": 0.004999999999999857,
+          "_facingDirection": "x+"
+        },
+        {
+          "pinId": "C1.2",
+          "x": 1.24,
+          "y": 0.00499999999999993,
+          "_facingDirection": "x-"
+        }
+      ]
+    }
+  ],
+  "directConnections": [
+    {
+      "pinIds": [
+        "V1.1",
+        "D1.1"
+      ],
+      "netId": ".V1 > .pin1 to .D1 > .anode"
+    },
+    {
+      "pinIds": [
+        "D1.2",
+        "R1.1"
+      ],
+      "netId": ".D1 > .cathode to .R1 > .pin1"
+    },
+    {
+      "pinIds": [
+        "D1.2",
+        "C1.1"
+      ],
+      "netId": ".D1 > .cathode to .C1 > .pin1"
+    },
+    {
+      "pinIds": [
+        "V1.2",
+        "R1.2"
+      ],
+      "netId": ".V1 > .pin2 to .R1 > .pin2"
+    },
+    {
+      "pinIds": [
+        "V1.2",
+        "C1.2"
+      ],
+      "netId": ".V1 > .pin2 to .C1 > .pin2"
+    }
+  ],
+  "netConnections": [],
+  "textBoxes": [],
+  "availableNetLabelOrientations": {},
+  "maxMspPairDistance": 10
+}

package/tests/repros/repro-missing-trace-netlabel.test.ts

@@ -0,0 +1,14 @@
+import { expect, test } from "bun:test"
+import { SchematicTracePipelineSolver } from "lib/solvers/SchematicTracePipelineSolver/SchematicTracePipelineSolver"
+import inputProblem from "./assets/repro-missing-trace-netlabel.input.json"
+import "tests/fixtures/matcher"
+
+// Regression (from @tscircuit/core repro148): the RESET connection between R3 and
+// SW2 used to route as a trace but now falls back to two net labels.
+test("repro148 missing trace becomes net labels", () => {
+  const solver = new SchematicTracePipelineSolver(inputProblem as any)
+
+  solver.solve()
+
+  expect(solver).toMatchSolverSnapshot(import.meta.path)
+})

package/tests/repros/repro-netlabel-overlap-trace.test.ts

@@ -0,0 +1,14 @@
+import { expect, test } from "bun:test"
+import { SchematicTracePipelineSolver } from "lib/solvers/SchematicTracePipelineSolver/SchematicTracePipelineSolver"
+import inputProblem from "./assets/repro-netlabel-overlap-trace.input.json"
+import "tests/fixtures/matcher"
+
+// Regression (from @tscircuit/core repro147): a GND net label ends up overlapping
+// the B1/SW1 junction trace instead of being placed clear of it.
+test("repro147 netlabel overlaps trace", () => {
+  const solver = new SchematicTracePipelineSolver(inputProblem as any)
+
+  solver.solve()
+
+  expect(solver).toMatchSolverSnapshot(import.meta.path)
+})

package/tests/repros/repro-rectifier-trace-overlap.test.ts

@@ -0,0 +1,14 @@
+import { expect, test } from "bun:test"
+import { SchematicTracePipelineSolver } from "lib/solvers/SchematicTracePipelineSolver/SchematicTracePipelineSolver"
+import inputProblem from "./assets/repro-rectifier-trace-overlap.input.json"
+import "tests/fixtures/matcher"
+
+// Regression (from @tscircuit/core half-bridge-rectifier): the R1->C1 connection
+// used to be a simple direct trace but now detours and overlaps another trace.
+test("repro149 rectifier trace overlap", () => {
+  const solver = new SchematicTracePipelineSolver(inputProblem as any)
+
+  solver.solve()
+
+  expect(solver).toMatchSolverSnapshot(import.meta.path)
+})