@tscircuit/schematic-trace-solver 0.0.193 → 0.0.195

package/tests/repros/assets/repro-core-vertical-passive-ground-label-overlap.input.json

@@ -0,0 +1,353 @@
+{
+  "chips": [
+    {
+      "chipId": "schematic_component_0",
+      "center": {
+        "x": 3.5699999999999994,
+        "y": 0.52
+      },
+      "width": 1.1650000000000005,
+      "height": 0.7600000000000001,
+      "symbolName": "capacitor_down",
+      "pins": [
+        {
+          "pinId": "schematic_port_0",
+          "displayName": "1",
+          "x": 3.4374999999999996,
+          "y": 0.9000000000000001,
+          "_facingDirection": "y+"
+        },
+        {
+          "pinId": "schematic_port_1",
+          "displayName": "2",
+          "x": 3.4374999999999996,
+          "y": 0.13999999999999996,
+          "_facingDirection": "y-"
+        }
+      ]
+    },
+    {
+      "chipId": "schematic_component_1",
+      "center": {
+        "x": -2.349166666666667,
+        "y": 2.4799999999999995
+      },
+      "width": 0.9250000000000003,
+      "height": 0.7600000000000007,
+      "symbolName": "capacitor_down",
+      "pins": [
+        {
+          "pinId": "schematic_port_2",
+          "displayName": "1",
+          "x": -2.361666666666667,
+          "y": 2.86,
+          "_facingDirection": "y+"
+        },
+        {
+          "pinId": "schematic_port_3",
+          "displayName": "2",
+          "x": -2.361666666666667,
+          "y": 2.099999999999999,
+          "_facingDirection": "y-"
+        }
+      ]
+    },
+    {
+      "chipId": "schematic_component_2",
+      "center": {
+        "x": 3.6149999999999993,
+        "y": -1.3650000000000004
+      },
+      "width": 1.2100000000000004,
+      "height": 0.6000000000000001,
+      "symbolName": "boxresistor_down",
+      "pins": [
+        {
+          "pinId": "schematic_port_4",
+          "displayName": "anode",
+          "x": 3.4599999999999995,
+          "y": -1.0650000000000004,
+          "_facingDirection": "y+"
+        },
+        {
+          "pinId": "schematic_port_5",
+          "displayName": "cathode",
+          "x": 3.4599999999999995,
+          "y": -1.6650000000000005,
+          "_facingDirection": "y-"
+        }
+      ]
+    },
+    {
+      "chipId": "schematic_component_3",
+      "center": {
+        "x": 1.2049999999999992,
+        "y": -2.405
+      },
+      "width": 1.2099999999999997,
+      "height": 0.5999999999999996,
+      "symbolName": "boxresistor_down",
+      "pins": [
+        {
+          "pinId": "schematic_port_6",
+          "displayName": "anode",
+          "x": 1.0499999999999994,
+          "y": -2.105,
+          "_facingDirection": "y+"
+        },
+        {
+          "pinId": "schematic_port_7",
+          "displayName": "cathode",
+          "x": 1.0499999999999994,
+          "y": -2.7049999999999996,
+          "_facingDirection": "y-"
+        }
+      ]
+    },
+    {
+      "chipId": "schematic_component_4",
+      "center": {
+        "x": 1.097023809523809,
+        "y": -4.29
+      },
+      "width": 0.925,
+      "height": 0.7600000000000002,
+      "symbolName": "capacitor_down",
+      "pins": [
+        {
+          "pinId": "schematic_port_8",
+          "displayName": "1",
+          "x": 1.0845238095238088,
+          "y": -3.91,
+          "_facingDirection": "y+"
+        },
+        {
+          "pinId": "schematic_port_9",
+          "displayName": "2",
+          "x": 1.0845238095238088,
+          "y": -4.67,
+          "_facingDirection": "y-"
+        }
+      ]
+    },
+    {
+      "chipId": "schematic_component_5",
+      "center": {
+        "x": 0.5558333333333332,
+        "y": 2.9799999999999995
+      },
+      "width": 2.5,
+      "height": 0.40000000000000036,
+      "pins": [
+        {
+          "pinId": "schematic_port_10",
+          "displayName": "VDD",
+          "x": -0.6941666666666668,
+          "y": 3.0799999999999996
+        },
+        {
+          "pinId": "schematic_port_11",
+          "displayName": "OUT",
+          "x": 1.8058333333333332,
+          "y": 2.9799999999999995
+        },
+        {
+          "pinId": "schematic_port_12",
+          "displayName": "GND",
+          "x": -0.6941666666666668,
+          "y": 2.8799999999999994
+        }
+      ]
+    },
+    {
+      "chipId": "schematic_component_6",
+      "center": {
+        "x": 3.1708333333333334,
+        "y": 2.4799999999999995
+      },
+      "width": 1.1650000000000005,
+      "height": 0.7600000000000007,
+      "symbolName": "capacitor_down",
+      "pins": [
+        {
+          "pinId": "schematic_port_13",
+          "displayName": "1",
+          "x": 3.038333333333333,
+          "y": 2.86,
+          "_facingDirection": "y+"
+        },
+        {
+          "pinId": "schematic_port_14",
+          "displayName": "2",
+          "x": 3.038333333333333,
+          "y": 2.099999999999999,
+          "_facingDirection": "y-"
+        }
+      ]
+    },
+    {
+      "chipId": "schematic_component_7",
+      "center": {
+        "x": 0,
+        "y": 0
+      },
+      "width": 3.3,
+      "height": 1,
+      "pins": [
+        {
+          "pinId": "schematic_port_15",
+          "displayName": "OUTA",
+          "x": 1.65,
+          "y": 0.09999999999999998
+        },
+        {
+          "pinId": "schematic_port_16",
+          "displayName": "INA_NEG",
+          "x": -1.65,
+          "y": 0.10000000000000003
+        },
+        {
+          "pinId": "schematic_port_17",
+          "displayName": "INA_POS",
+          "x": -1.65,
+          "y": 0.30000000000000004
+        },
+        {
+          "pinId": "schematic_port_18",
+          "displayName": "VSS_NEG",
+          "x": 1.65,
+          "y": -0.30000000000000004
+        },
+        {
+          "pinId": "schematic_port_19",
+          "displayName": "INB_POS",
+          "x": -1.65,
+          "y": -0.09999999999999998
+        },
+        {
+          "pinId": "schematic_port_20",
+          "displayName": "INB_NEG",
+          "x": -1.65,
+          "y": -0.30000000000000004
+        },
+        {
+          "pinId": "schematic_port_21",
+          "displayName": "OUTB",
+          "x": 1.65,
+          "y": -0.10000000000000003
+        },
+        {
+          "pinId": "schematic_port_22",
+          "displayName": "VCC",
+          "x": 1.65,
+          "y": 0.30000000000000004
+        }
+      ]
+    }
+  ],
+  "directConnections": [
+    {
+      "netId": "MK1.OUT to C5.pin1",
+      "pinIds": [
+        "schematic_port_11",
+        "schematic_port_13"
+      ]
+    }
+  ],
+  "netConnections": [
+    {
+      "netId": "VCC",
+      "netLabelText": "VCC",
+      "isGround": false,
+      "netLabelWidth": 0.42,
+      "netLabelHeight": 0.48,
+      "pinIds": [
+        "schematic_port_0",
+        "schematic_port_2",
+        "schematic_port_4",
+        "schematic_port_10",
+        "schematic_port_22"
+      ]
+    },
+    {
+      "netId": "GND",
+      "netLabelText": "GND",
+      "isGround": true,
+      "netLabelWidth": 0.42,
+      "netLabelHeight": 0.48,
+      "pinIds": [
+        "schematic_port_1",
+        "schematic_port_3",
+        "schematic_port_7",
+        "schematic_port_9",
+        "schematic_port_12",
+        "schematic_port_18"
+      ]
+    },
+    {
+      "netId": "VREF",
+      "netLabelText": "VREF",
+      "isGround": false,
+      "netLabelWidth": 0.42,
+      "netLabelHeight": 0.6,
+      "pinIds": [
+        "schematic_port_5",
+        "schematic_port_6",
+        "schematic_port_8"
+      ]
+    },
+    {
+      "netId": "MIC_AC",
+      "netLabelText": "MIC_AC",
+      "isGround": false,
+      "netLabelWidth": 0.84,
+      "anchoredNetLabelWidth": 0.84,
+      "allowInlineNetLabel": true,
+      "inlineNetLabelHeight": 0.12,
+      "inlineNetLabelWidth": 0.56,
+      "pinIds": [
+        "schematic_port_14",
+        "schematic_port_17"
+      ]
+    }
+  ],
+  "textBoxes": [
+    {
+      "chipId": "schematic_component_5",
+      "center": {
+        "x": -0.1141666666666668,
+        "y": 3.295
+      },
+      "width": 0.48,
+      "height": 0.24999999999999956,
+      "text": "MK1"
+    },
+    {
+      "chipId": "schematic_component_7",
+      "center": {
+        "x": -1.13,
+        "y": 0.615
+      },
+      "width": 0.3600000000000001,
+      "height": 0.25,
+      "text": "U1"
+    }
+  ],
+  "availableNetLabelOrientations": {
+    "VCC": [
+      "y+"
+    ],
+    "GND": [
+      "y-"
+    ],
+    "VREF": [
+      "y+"
+    ],
+    "MIC_AC": [
+      "x-",
+      "x+"
+    ]
+  },
+  "maxMspPairDistance": 2.4,
+  "_hideRatsNet": false
+}

package/tests/repros/repro-core-vertical-passive-ground-label-overlap.test.ts

@@ -0,0 +1,39 @@
+import { expect, test } from "bun:test"
+import { SchematicTracePipelineSolver } from "lib/solvers/SchematicTracePipelineSolver/SchematicTracePipelineSolver"
+import type { InputProblem } from "lib/types/InputProblem"
+import { pathIntersectsRenderedLabel } from "lib/utils/pathIntersectsRenderedLabel"
+import "tests/fixtures/matcher"
+import inputProblem from "./assets/repro-core-vertical-passive-ground-label-overlap.input.json"
+
+// Captured via solver:started from @tscircuit/core repro187. Symbol names and
+// display text were added for a readable snapshot; routing geometry is intact.
+test("VREF trace overlaps a vertical passive GND label", async () => {
+  const solver = new SchematicTracePipelineSolver(
+    inputProblem as unknown as InputProblem,
+    { hideRatsNet: true },
+  )
+
+  solver.solve()
+
+  expect(solver.solved).toBe(true)
+  const { traces, netLabelPlacements } =
+    solver.netLabelToTraceSolver!.getOutput()
+  const groundLabel = netLabelPlacements.find(
+    (label) =>
+      label.netId === "GND" && label.pinIds.includes("schematic_port_7"),
+  )!
+  const vrefTrace = traces.find(
+    (trace) =>
+      trace.pinIds.includes("schematic_port_6") &&
+      trace.pinIds.includes("schematic_port_8"),
+  )!
+
+  expect(groundLabel).toBeDefined()
+  expect(vrefTrace).toBeDefined()
+  expect(vrefTrace.globalConnNetId).not.toBe(groundLabel.globalConnNetId)
+  // Current bug: a different-net trace crosses the rendered GND terminal.
+  expect(pathIntersectsRenderedLabel(vrefTrace.tracePath, groundLabel)).toBe(
+    true,
+  )
+  await expect(solver).toMatchSolverSnapshot(import.meta.path)
+})