@tscircuit/schematic-trace-solver 0.0.159 → 0.0.161

package/tests/repros/repro-bluetooth-controller-ground-decoupling-groups.test.ts

@@ -0,0 +1,18 @@
+import { expect, test } from "bun:test"
+import { SchematicTracePipelineSolver } from "lib/solvers/SchematicTracePipelineSolver/SchematicTracePipelineSolver"
+import type { InputProblem } from "lib/types/InputProblem"
+import "tests/fixtures/matcher"
+import inputProblem from "./assets/repro-bluetooth-controller-ground-decoupling-groups.input.json"
+
+test("repro Bluetooth controller GND trace between decoupling groups", () => {
+  const solver = new SchematicTracePipelineSolver(
+    inputProblem as InputProblem,
+    {
+      hideRatsNet: true,
+    },
+  )
+
+  solver.solve()
+
+  expect(solver).toMatchSolverSnapshot(import.meta.path)
+})

package/tests/repros/repro-core-ground-inline-label-fallback.test.ts

@@ -0,0 +1,34 @@
+import { expect, test } from "bun:test"
+import { SchematicTracePipelineSolver } from "lib/solvers/SchematicTracePipelineSolver/SchematicTracePipelineSolver"
+import type { InputProblem } from "lib/types/InputProblem"
+import "tests/fixtures/matcher"
+import inputProblemJson from "./assets/repro-core-ground-inline-label-fallback.input.json"
+
+const signalNetIds = new Set(["step", "direction", "enable"])
+
+// Captured from @tscircuit/core's
+// ground-net-label-preserves-solver-orientation test. These three two-pin
+// signal nets opt into inline labels, but the neighboring shared LOGIC_3V3
+// and GND labels cause post-processing to fall them back to anchored labels.
+test("repro: core inline signal labels fall back near shared rail labels", () => {
+  const inputProblem: InputProblem = JSON.parse(
+    JSON.stringify(inputProblemJson),
+  )
+  const solver = new SchematicTracePipelineSolver(inputProblem)
+
+  solver.solve()
+
+  const inlineOutput = solver.inlineNetLabelSolver!.getOutput()
+  const signalInlineLabels = inlineOutput.inlineNetLabelPlacements.filter(
+    (placement) => signalNetIds.has(placement.netId ?? ""),
+  )
+  const signalAnchoredLabels = inlineOutput.netLabelPlacements.filter(
+    (placement) => signalNetIds.has(placement.netId ?? ""),
+  )
+
+  expect(signalInlineLabels).toHaveLength(0)
+  expect(
+    signalAnchoredLabels.map((placement) => placement.netId).sort(),
+  ).toEqual(["direction", "direction", "enable", "enable", "step", "step"])
+  expect(solver).toMatchSolverSnapshot(import.meta.path)
+})

package/tests/repros/repro-hdc2080-ground-label-alignment.test.ts

@@ -0,0 +1,239 @@
+import { expect, test } from "bun:test"
+import { SchematicTracePipelineSolver } from "lib/solvers/SchematicTracePipelineSolver/SchematicTracePipelineSolver"
+import type { InputProblem } from "lib/types/InputProblem"
+import "tests/fixtures/matcher"
+
+const inputProblem: InputProblem = {
+  chips: [
+    {
+      chipId: "schematic_component_0",
+      center: { x: 4.5, y: 0 },
+      width: 3.4000000000000004,
+      height: 4.6,
+      pins: [
+        {
+          pinId: "schematic_port_0",
+          displayName: "VDD",
+          x: 2.8,
+          y: 0.8500000000000001,
+        },
+        {
+          pinId: "schematic_port_1",
+          displayName: "SCL",
+          x: 2.8,
+          y: 0.4000000000000001,
+        },
+        {
+          pinId: "schematic_port_2",
+          displayName: "SDA",
+          x: 2.8,
+          y: 0.20000000000000007,
+        },
+        {
+          pinId: "schematic_port_3",
+          displayName: "GPIO",
+          x: 2.8,
+          y: 0,
+        },
+        {
+          pinId: "schematic_port_4",
+          displayName: "GND",
+          x: 2.8,
+          y: -0.8500000000000001,
+        },
+      ],
+    },
+    {
+      chipId: "schematic_component_1",
+      center: { x: -2.1, y: 0 },
+      width: 4,
+      height: 4,
+      pins: [
+        {
+          pinId: "schematic_port_5",
+          displayName: "I2C_SDA",
+          x: -0.10000000000000009,
+          y: 0.5499999999999998,
+        },
+        {
+          pinId: "schematic_port_6",
+          displayName: "GND",
+          x: -0.10000000000000009,
+          y: -1.2000000000000002,
+        },
+        {
+          pinId: "schematic_port_7",
+          displayName: "I2C_ADDR",
+          x: -0.10000000000000009,
+          y: -0.5500000000000002,
+        },
+        {
+          pinId: "schematic_port_8",
+          displayName: "DRDY_INT",
+          x: -0.10000000000000009,
+          y: 0.09999999999999987,
+        },
+        {
+          pinId: "schematic_port_9",
+          displayName: "VDD",
+          x: -0.10000000000000009,
+          y: 1.2000000000000002,
+        },
+        {
+          pinId: "schematic_port_10",
+          displayName: "I2C_SCL",
+          x: -0.10000000000000009,
+          y: 0.7499999999999998,
+        },
+      ],
+    },
+    {
+      chipId: "schematic_component_2",
+      center: { x: 0.7949999999999999, y: 1.3 },
+      width: 1.0899999999999999,
+      height: 0.6000000000000001,
+      pins: [
+        {
+          pinId: "schematic_port_11",
+          displayName: "anode",
+          x: 0.7,
+          y: 1.6,
+          _facingDirection: "y+",
+        },
+        {
+          pinId: "schematic_port_12",
+          displayName: "cathode",
+          x: 0.7,
+          y: 1,
+          _facingDirection: "y-",
+        },
+      ],
+    },
+    {
+      chipId: "schematic_component_3",
+      center: { x: 1.5949999999999998, y: 1.3 },
+      width: 1.0899999999999996,
+      height: 0.6000000000000001,
+      pins: [
+        {
+          pinId: "schematic_port_13",
+          displayName: "anode",
+          x: 1.5,
+          y: 1.6,
+          _facingDirection: "y+",
+        },
+        {
+          pinId: "schematic_port_14",
+          displayName: "cathode",
+          x: 1.5,
+          y: 1,
+          _facingDirection: "y-",
+        },
+      ],
+    },
+  ],
+  directConnections: [],
+  netConnections: [
+    {
+      netId: "VDD",
+      netLabelWidth: 0.42,
+      netLabelHeight: 0.48,
+      pinIds: [
+        "schematic_port_0",
+        "schematic_port_9",
+        "schematic_port_11",
+        "schematic_port_13",
+      ],
+    },
+    {
+      netId: "SCL",
+      netLabelWidth: 0.48,
+      pinIds: ["schematic_port_1", "schematic_port_10", "schematic_port_12"],
+    },
+    {
+      netId: "SDA",
+      netLabelWidth: 0.48,
+      pinIds: ["schematic_port_2", "schematic_port_5", "schematic_port_14"],
+    },
+    {
+      netId: "DRDY_INT",
+      netLabelWidth: 1.08,
+      anchoredNetLabelWidth: 1.08,
+      allowInlineNetLabel: true,
+      inlineNetLabelHeight: 0.12,
+      inlineNetLabelWidth: 0.72,
+      pinIds: ["schematic_port_3", "schematic_port_8"],
+    },
+    {
+      netId: "GND",
+      netLabelWidth: 0.42,
+      netLabelHeight: 0.48,
+      pinIds: ["schematic_port_4", "schematic_port_6", "schematic_port_7"],
+    },
+  ],
+  textBoxes: [
+    {
+      chipId: "schematic_component_0",
+      center: { x: 3.38, y: -2.4299999999999997 },
+      width: 0.3599999999999999,
+      height: 0.17999999999999972,
+      text: "MCU",
+    },
+    {
+      chipId: "schematic_component_0",
+      center: { x: 3.3200000000000003, y: 2.415 },
+      width: 0.3600000000000003,
+      height: 0.24999999999999956,
+      text: "U2",
+    },
+    {
+      chipId: "schematic_component_1",
+      center: { x: -3.04, y: -2.13 },
+      width: 1.3199999999999998,
+      height: 0.17999999999999972,
+      text: "HDC2080DMBR",
+    },
+    {
+      chipId: "schematic_component_1",
+      center: { x: -3.58, y: 2.1149999999999998 },
+      width: 0.3600000000000003,
+      height: 0.24999999999999978,
+      text: "U1",
+    },
+  ],
+  availableNetLabelOrientations: {
+    VDD: ["y+"],
+    SCL: ["x-", "x+"],
+    SDA: ["x-", "x+"],
+    DRDY_INT: ["x-", "x+"],
+    GND: ["y-"],
+  },
+  maxMspPairDistance: 2.4,
+  _hideRatsNet: false,
+}
+
+test("aligns the HDC2080 GND label with its vertical rail", () => {
+  const solver = new SchematicTracePipelineSolver(inputProblem)
+
+  solver.solve()
+
+  const orientationOutput = solver.availableNetOrientationSolver!.getOutput()
+  const groundLabel = orientationOutput.netLabelPlacements.find(
+    (label) =>
+      label.netId === "GND" && label.pinIds.includes("schematic_port_6"),
+  )
+  const groundRailTrace = orientationOutput.traces.find(
+    (trace) => trace.mspPairId === "schematic_port_7-schematic_port_6",
+  )
+  const matchingGroundTraces = orientationOutput.traces.filter(
+    (trace) =>
+      trace.userNetId === "GND" &&
+      trace.pinIds.includes("schematic_port_6") &&
+      trace.pinIds.includes("schematic_port_7"),
+  )
+
+  expect(groundLabel?.anchorPoint.x).toBeCloseTo(0.1)
+  expect(groundRailTrace?.tracePath[1]?.x).toBeCloseTo(0.1)
+  expect(matchingGroundTraces).toHaveLength(1)
+  expect(solver).toMatchSolverSnapshot(import.meta.path)
+})

package/tests/repros/repro-tida010076-j4-ground-bus.test.ts

@@ -59,20 +59,24 @@ test("repro TIDA-010076 J4 ground pins should share one vertical bus", () => {
   solver.solve()
 
   const output = solver.sameNetJunctionAlignmentSolver!.getOutput()
+  const groundConnection = inputProblem.netConnections[0]!
+  const groundPinIds = new Set(groundConnection.pinIds)
   const groundTraces = output.traces.filter(
     (trace) =>
-      trace.userNetId === "NET_AGND" &&
-      trace.pinIds.every((pinId) => pinId.startsWith("J4.")),
+      trace.userNetId === groundConnection.netId &&
+      trace.pinIds.every((pinId) => groundPinIds.has(pinId)),
   )
-  const verticalBranchOffsets = new Set(
-    groundTraces.map((trace) => trace.tracePath[1]!.x.toFixed(3)),
+  const verticalRailXs = groundTraces.map((trace) => trace.tracePath[1]!.x)
+  const groundLabel = output.netLabelPlacements.find(
+    (label) => label.netId === groundConnection.netId,
   )
 
-  // Current mismatch: the first three GND pins use one vertical offset while
-  // the final pair detours around the manufacturer text at a second offset.
-  expect(verticalBranchOffsets.size).toBe(2)
-  expect(
-    output.netLabelPlacements.filter((label) => label.netId === "NET_AGND"),
-  ).toHaveLength(1)
+  expect(new Set(verticalRailXs.map((x) => x.toFixed(3))).size).toBe(1)
+  expect(verticalRailXs[0]).toBeCloseTo(0.975)
+  expect(groundLabel?.anchorPoint.x).toBeCloseTo(verticalRailXs[0]!)
+  const productTextBox = inputProblem.textBoxes![0]!
+  expect(groundLabel?.anchorPoint.y).toBeLessThan(
+    productTextBox.center.y - productTextBox.height / 2,
+  )
   expect(solver).toMatchSolverSnapshot(import.meta.path)
 })

package/tests/repros/repro-tida010076-page02.test.ts

@@ -39,8 +39,8 @@ test("repro TIDA-010076 page 02 net-label placement", () => {
     )!
 
   expect(j5AgndLabel.orientation).toBe("y-")
-  expect(j5AgndLabel.anchorPoint.y).toBeCloseTo(
-    Math.min(...j5GroundPins.map((pin) => pin.y)),
+  expect(Math.abs(j5AgndLabel.anchorPoint.x - j5GroundPins[0]!.x)).toBeCloseTo(
+    0.2,
   )
 
   const powerConnectorPinPairs = [

package/tests/repros/repro-usb-power-vbus-label-detour.test.ts

@@ -37,6 +37,13 @@ test("routes the usb power vbus connection without a label detour", () => {
         label.pinIds.includes("schematic_port_54") &&
         label.pinIds.includes("schematic_port_162"),
     )
+  const inlineOutput = solver.inlineNetLabelSolver!.getOutput()
+  const usbHighSpeedInlineLabels = inlineOutput.inlineNetLabelPlacements.filter(
+    (placement) => placement.netId?.startsWith("USB_HS_"),
+  )
+  const usbHighSpeedAnchoredLabels = inlineOutput.netLabelPlacements.filter(
+    (placement) => placement.netId?.startsWith("USB_HS_"),
+  )
 
   expect(gndLabel?.orientation).toBe("y-")
   expect(gndLabel?.anchorPoint.x).toBeCloseTo(-2.34)
@@ -53,5 +60,12 @@ test("routes the usb power vbus connection without a label detour", () => {
     { x: 12.8, y: -5.8 },
     { x: 13, y: -5.8 },
   ])
+  // The available inline side of USB_HS_DM overlaps the retained USB_HS_DP
+  // tag. Keep both differential-pair nets anchored instead of producing a
+  // mixed, overlapping representation.
+  expect(usbHighSpeedInlineLabels).toHaveLength(0)
+  expect(
+    usbHighSpeedAnchoredLabels.map((placement) => placement.netId).sort(),
+  ).toEqual(["USB_HS_DM", "USB_HS_DM", "USB_HS_DP", "USB_HS_DP"])
   expect(solver).toMatchSolverSnapshot(import.meta.path)
 })

package/tests/solvers/InlineNetLabelSolver/__snapshots__/inline-net-label02.snap.svg

@@ -70,6 +70,6 @@ USER_LED_ANODE" data-x="1.5175" data-y="0" cx="324.7058823529412" cy="336.134453
               .port-label { fill: rgb(0, 100, 100); }
               .component-name { fill: rgb(0, 100, 100); }
 
-            </style><rect class="boundary" x="0" y="0" width="1200" height="800"/><g class="trace sch-trace" data-layer="base" data-circuit-json-type="schematic_trace" data-schematic-trace-id="schematic_trace_0__stack1"><path d="M 461.18251928022 464.78149100256 L 602.6992287917735 464.78149100256 L 602.6992287917735 418.5089974293 L 744.215938303327 418.5089974293" class="trace-invisible-hover-outline sch-trace-hitbox" stroke="rgb(0, 150, 0)" fill="none" stroke-width="24.678663239071998px" stroke-linecap="round" opacity="0" stroke-linejoin="round"/><path class="sch-trace-path" d="M 461.18251928022 464.78149100256 L 602.6992287917735 464.78149100256 L 602.6992287917735 418.5089974293 L 744.215938303327 418.5089974293" stroke="rgb(0, 150, 0)" fill="none" stroke-width="3.0848329048839997px" stroke-linecap="round" stroke-linejoin="round"/></g><g class="trace-overlays sch-trace-overlays" data-layer="overlay" data-circuit-json-type="schematic_trace" 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