@tscircuit/schematic-trace-solver 0.0.156 → 0.0.158
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/dist/index.d.ts +2 -0
- package/dist/index.js +151 -57
- package/lib/solvers/MspConnectionPairSolver/MspConnectionPairSolver.ts +10 -2
- package/lib/solvers/SameNetJunctionAlignmentSolver/alignSameNetJunctions.ts +196 -67
- package/package.json +1 -1
- package/site/bug-reports/bug-report-20260826T072956Z.page.tsx +4 -0
- package/site/components/PipelineDebugger.tsx +4 -2
- package/site/examples/example51.page.tsx +3 -1
- package/tests/bug-reports/bug-report-20260706T213649Z/__snapshots__/bug-report-20260706T213649Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260706T220324Z/__snapshots__/bug-report-20260706T220324Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260707T020342Z/__snapshots__/bug-report-20260707T020342Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260707T092615Z/__snapshots__/bug-report-20260707T092615Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260707T134549Z/__snapshots__/bug-report-20260707T134549Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260707T134722Z/__snapshots__/bug-report-20260707T134722Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260707T140410Z/__snapshots__/bug-report-20260707T140410Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260707T141025Z/__snapshots__/bug-report-20260707T141025Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260707T141421Z/__snapshots__/bug-report-20260707T141421Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260707T230831Z/__snapshots__/bug-report-20260707T230831Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260708T053736Z/__snapshots__/bug-report-20260708T053736Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260708T055430Z/__snapshots__/bug-report-20260708T055430Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260708T095725Z/__snapshots__/bug-report-20260708T095725Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260716T144856Z/__snapshots__/bug-report-20260716T144856Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260717T022934Z/__snapshots__/bug-report-20260717T022934Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260717T031704Z/__snapshots__/bug-report-20260717T031704Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260717T042845Z/__snapshots__/bug-report-20260717T042845Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260721T221026Z/__snapshots__/bug-report-20260721T221026Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260724T175257Z/__snapshots__/bug-report-20260724T175257Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260728T144234Z/__snapshots__/bug-report-20260728T144234Z.snap.svg +4 -4
- package/tests/bug-reports/bug-report-20260728T225606Z/__snapshots__/bug-report-20260728T225606Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260730T061837Z/__snapshots__/bug-report-20260730T061837Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260731T052229Z/__snapshots__/bug-report-20260731T052229Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260804T095800Z/__snapshots__/bug-report-20260804T095800Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260804T171919Z/__snapshots__/bug-report-20260804T171919Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260804T225912Z/__snapshots__/bug-report-20260804T225912Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260805T061316Z/__snapshots__/bug-report-20260805T061316Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260806T061548Z/__snapshots__/bug-report-20260806T061548Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260806T093501Z/__snapshots__/bug-report-20260806T093501Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260811T075142Z/__snapshots__/bug-report-20260811T075142Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260815T073240Z/__snapshots__/bug-report-20260815T073240Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260819T091818Z/__snapshots__/bug-report-20260819T091818Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260825T045913Z/__snapshots__/bug-report-20260825T045913Z.snap.svg +4 -4
- package/tests/bug-reports/bug-report-20260825T103621Z/__snapshots__/bug-report-20260825T103621Z.snap.svg +2 -2
- package/tests/bug-reports/bug-report-20260826T072956Z/__snapshots__/bug-report-20260826T072956Z.snap.svg +842 -0
- package/tests/bug-reports/bug-report-20260826T072956Z/bug-report-20260826T072956Z.json +2452 -0
- package/tests/bug-reports/bug-report-20260826T072956Z/bug-report-20260826T072956Z.test.ts +12 -0
- package/tests/examples/__snapshots__/example01.snap.svg +2 -2
- package/tests/examples/__snapshots__/example02.snap.svg +12 -12
- package/tests/examples/__snapshots__/example03.snap.svg +2 -2
- package/tests/examples/__snapshots__/example04.snap.svg +2 -2
- package/tests/examples/__snapshots__/example05.snap.svg +2 -2
- package/tests/examples/__snapshots__/example06.snap.svg +2 -2
- package/tests/examples/__snapshots__/example07.snap.svg +2 -2
- package/tests/examples/__snapshots__/example08.snap.svg +2 -2
- package/tests/examples/__snapshots__/example09.snap.svg +2 -2
- package/tests/examples/__snapshots__/example10.snap.svg +2 -2
- package/tests/examples/__snapshots__/example11.snap.svg +2 -2
- package/tests/examples/__snapshots__/example12.snap.svg +2 -2
- package/tests/examples/__snapshots__/example13.snap.svg +2 -2
- package/tests/examples/__snapshots__/example14.snap.svg +2 -2
- package/tests/examples/__snapshots__/example15.snap.svg +2 -2
- package/tests/examples/__snapshots__/example16.snap.svg +2 -2
- package/tests/examples/__snapshots__/example17.snap.svg +2 -2
- package/tests/examples/__snapshots__/example18.snap.svg +2 -2
- package/tests/examples/__snapshots__/example19.snap.svg +2 -2
- package/tests/examples/__snapshots__/example20.snap.svg +2 -2
- package/tests/examples/__snapshots__/example21.snap.svg +2 -2
- package/tests/examples/__snapshots__/example22.snap.svg +2 -2
- package/tests/examples/__snapshots__/example23.snap.svg +2 -2
- package/tests/examples/__snapshots__/example24.snap.svg +2 -2
- package/tests/examples/__snapshots__/example25.snap.svg +2 -2
- package/tests/examples/__snapshots__/example26.snap.svg +2 -2
- package/tests/examples/__snapshots__/example27.snap.svg +2 -2
- package/tests/examples/__snapshots__/example28.snap.svg +2 -2
- package/tests/examples/__snapshots__/example29.snap.svg +2 -2
- package/tests/examples/__snapshots__/example30.snap.svg +2 -2
- package/tests/examples/__snapshots__/example31.snap.svg +2 -2
- package/tests/examples/__snapshots__/example32.snap.svg +2 -2
- package/tests/examples/__snapshots__/example33.snap.svg +2 -2
- package/tests/examples/__snapshots__/example34.snap.svg +2 -2
- package/tests/examples/__snapshots__/example35.snap.svg +2 -2
- package/tests/examples/__snapshots__/example36.snap.svg +2 -2
- package/tests/examples/__snapshots__/example37.snap.svg +2 -2
- package/tests/examples/__snapshots__/example38.snap.svg +2 -2
- package/tests/examples/__snapshots__/example39.snap.svg +2 -2
- package/tests/examples/__snapshots__/example40.snap.svg +2 -2
- package/tests/examples/__snapshots__/example41.snap.svg +2 -2
- package/tests/examples/__snapshots__/example42.snap.svg +2 -2
- package/tests/examples/__snapshots__/example43.snap.svg +2 -2
- package/tests/examples/__snapshots__/example44.snap.svg +2 -2
- package/tests/examples/__snapshots__/example45.snap.svg +2 -2
- package/tests/examples/__snapshots__/example46.snap.svg +2 -2
- package/tests/examples/__snapshots__/example47.snap.svg +2 -2
- package/tests/examples/__snapshots__/example48.snap.svg +2 -2
- package/tests/examples/__snapshots__/example49.snap.svg +2 -2
- package/tests/examples/__snapshots__/example50.snap.svg +2 -2
- package/tests/examples/__snapshots__/example51.snap.svg +4 -4
- package/tests/fixtures/matcher.ts +3 -3
- package/tests/repros/__snapshots__/board-1273-trace-overlap-cycle.snap.svg +73 -82
- package/tests/repros/__snapshots__/board-15984-same-net-junction.snap.svg +12 -12
- package/tests/repros/__snapshots__/board1096-usb-label-overlap-iteration.snap.svg +5 -5
- package/tests/repros/__snapshots__/bugreport-001-gnd-overlap.snap.svg +2 -2
- package/tests/repros/__snapshots__/manufacturePartNumber-text-box.snap.svg +2 -2
- package/tests/repros/__snapshots__/netlabel-connector-through-rail-label.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-atmega328p-fault-pullup.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-atmega328p-missing-gnd-netlabel.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-board-589-regulator-section.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-board-648-esp12f-section.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-bq24074-battery-charger.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-bq25895-cross-net-trace-overlap.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-cc2340r5.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-core-555-power-cross-net-overlap.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-core-subcircuit-missing-ground.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-core-tb67s579ftg-inline-label-routing.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-dc-power-isolated-routing.snap.svg +129 -0
- package/tests/repros/__snapshots__/repro-example35-minimize-trace-crossing.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-ground-label-on-lower-rail-end.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-ina237-current-monitor.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-missing-trace-netlabel.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-mspm0l1306-capacitor-symmetry.snap.svg +182 -0
- package/tests/repros/__snapshots__/repro-netlabel-collision-687.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-netlabel-overlap-trace.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-nrf52810-clock-routing.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-pga300-c6-trace-alignment.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-pga300-redundant-ground-traces.snap.svg +288 -0
- package/tests/repros/__snapshots__/repro-pmp11282-isolated-dcdc.snap.svg +1290 -0
- package/tests/repros/__snapshots__/repro-power-group-rail-labels.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-rectifier-trace-overlap.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-rp2040-gamepad-trace-alignment.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-rp2040-usb-cc2-ground-overlap.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-rp2040-v3v3-label-placement.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-rp2040-zero-crystal-fallback-netlabels.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-ti-power-output-section.snap.svg +4 -4
- package/tests/repros/__snapshots__/repro-tida00553-j4-cell-divider.snap.svg +130 -0
- package/tests/repros/__snapshots__/repro-tida010076-j4-ground-bus.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-tida010076-page02.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-tps61222-trace-intersection.snap.svg +4 -4
- package/tests/repros/__snapshots__/repro-type-c-16pin-self-connection.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-type-c-16pin-to-resistor.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-type-c-vbus-led-ground-label.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro-usb-power-vbus-label-detour.snap.svg +12 -12
- package/tests/repros/__snapshots__/repro-vcc-pin1-detour.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro129-host-custom-symbol-passives.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro130-bq27441-fuel-gauge-trace-through-c1.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro161-power-section-autolayout.snap.svg +4 -4
- package/tests/repros/__snapshots__/repro47-endpoint-obstacle-detour.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro48-555-timer-vcc-rail-label.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro5-escape-padded-text-obstacles.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro51-overlap-junction-crossing.snap.svg +2 -2
- package/tests/repros/__snapshots__/repro84-stacked-gnd-label-orientation.snap.svg +2 -2
- package/tests/repros/__snapshots__/small-variant-resistor-facing-direction.snap.svg +2 -2
- package/tests/repros/__snapshots__/trace-overlap-box-resistor.snap.svg +2 -2
- package/tests/repros/assets/repro-dc-power-isolated-routing.input.json +193 -0
- package/tests/repros/assets/repro-mspm0l1306-capacitor-symmetry.input.json +537 -0
- package/tests/repros/assets/repro-pga300-redundant-ground-traces.input.json +858 -0
- package/tests/repros/assets/repro-pmp11282-isolated-dcdc.input.json +4570 -0
- package/tests/repros/board-1273-trace-overlap-cycle.test.ts +1 -1
- package/tests/repros/repro-dc-power-isolated-routing.test.ts +13 -0
- package/tests/repros/repro-mspm0l1306-capacitor-symmetry.test.ts +54 -0
- package/tests/repros/repro-pga300-redundant-ground-traces.test.ts +33 -0
- package/tests/repros/repro-pmp11282-isolated-dcdc.test.ts +77 -0
- package/tests/repros/repro-tida00553-j4-cell-divider.test.ts +111 -0
- package/tests/solvers/InlineNetLabelSolver/__snapshots__/anchored-net-label-width.snap.svg +2 -2
- package/tests/solvers/InlineNetLabelSolver/__snapshots__/inline-net-label-anchored-label-clearance.snap.svg +2 -2
- package/tests/solvers/InlineNetLabelSolver/__snapshots__/inline-net-label-port-stub.snap.svg +2 -2
- package/tests/solvers/InlineNetLabelSolver/__snapshots__/inline-net-label-two-pin-net.snap.svg +2 -2
- package/tests/solvers/InlineNetLabelSolver/__snapshots__/inline-net-label01.snap.svg +2 -2
- package/tests/solvers/InlineNetLabelSolver/__snapshots__/inline-net-label02.snap.svg +2 -2
- package/tests/solvers/InlineNetLabelSolver/__snapshots__/terminal-stub-trace-clearance.snap.svg +2 -2
- package/tests/solvers/SameNetJunctionAlignmentSolver/parallel-load-rails.test.ts +291 -0
- package/tests/solvers/SchematicTraceSingleLineSolver2/__snapshots__/SchematicTraceSingleLineSolver2_01-example17-d1_1-u1_1.snap.svg +2 -2
- package/tests/solvers/SchematicTraceSingleLineSolver2/__snapshots__/SchematicTraceSingleLineSolver2_repro47-short-opposing-pins.snap.svg +2 -2
- package/tests/solvers/TraceCleanupSolver/__snapshots__/TraceCleanupSolver.snap.svg +2 -2
- package/tests/solvers/TraceLabelOverlapAvoidanceSolver/__snapshots__/TraceLabelOverlapAvoidanceSolver.snap.svg +2 -2
- package/tests/solvers/TraceLabelOverlapAvoidanceSolver/sub-solver/__snapshots__/MergedNetLabelObstacles.snap.svg +2 -2
- package/tests/solvers/TraceLabelOverlapAvoidanceSolver/sub-solver/__snapshots__/OverlapAvoidanceStepSolver.snap.svg +2 -2
- package/tests/solvers/TraceLabelOverlapAvoidanceSolver/sub-solver/__snapshots__/SingleOverlapSolver.snap.svg +2 -2
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@@ -0,0 +1,858 @@
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{
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"chips": [
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{
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"chipId": "schematic_component_0",
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"center": {
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"x": -4.2,
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"y": 0
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"width": 4.6,
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"height": 8,
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"pins": [
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"pinId": "schematic_port_0",
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"displayName": "DVDD_MEM",
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"x": -1.9000000000000004,
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"y": 2.6050000000000004
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},
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{
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"pinId": "schematic_port_1",
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"displayName": "DVDD",
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"x": -1.9000000000000004,
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"y": 1.1849999999999996
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"pinId": "schematic_port_2",
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"displayName": "GATE",
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"x": -1.9000000000000004,
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"y": 3.5250000000000012
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"pinId": "schematic_port_3",
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"displayName": "VDD",
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"y": 3.075000000000001
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"pinId": "schematic_port_4",
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"displayName": "DACCAP",
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"pinId": "schematic_port_5",
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"displayName": "VOUT",
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"pinId": "schematic_port_6",
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"pinId": "schematic_port_7",
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"displayName": "GND",
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"x": -1.9000000000000004,
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"y": 1.8949999999999996
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"pinId": "schematic_port_8",
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"displayName": "FBN",
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"x": -1.9000000000000004,
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"y": -2.0850000000000013
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{
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"pinId": "schematic_port_9",
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"displayName": "FBP",
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"x": -1.9000000000000004,
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"y": -3.5250000000000012
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},
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{
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"pinId": "schematic_port_10",
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"displayName": "COMP",
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"x": -1.9000000000000004,
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{
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"pinId": "schematic_port_11",
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"displayName": "VBRGN",
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"x": -6.5,
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|
83
|
+
},
|
|
84
|
+
{
|
|
85
|
+
"pinId": "schematic_port_12",
|
|
86
|
+
"displayName": "VBRGP",
|
|
87
|
+
"x": -6.5,
|
|
88
|
+
"y": 1.4000000000000004
|
|
89
|
+
},
|
|
90
|
+
{
|
|
91
|
+
"pinId": "schematic_port_13",
|
|
92
|
+
"displayName": "REFCAP",
|
|
93
|
+
"x": -1.9000000000000004,
|
|
94
|
+
"y": 0.7249999999999996
|
|
95
|
+
},
|
|
96
|
+
{
|
|
97
|
+
"pinId": "schematic_port_14",
|
|
98
|
+
"displayName": "VINPN",
|
|
99
|
+
"x": -6.5,
|
|
100
|
+
"y": 0.2400000000000002
|
|
101
|
+
},
|
|
102
|
+
{
|
|
103
|
+
"pinId": "schematic_port_15",
|
|
104
|
+
"displayName": "VINPP",
|
|
105
|
+
"x": -6.5,
|
|
106
|
+
"y": 0.7500000000000004
|
|
107
|
+
},
|
|
108
|
+
{
|
|
109
|
+
"pinId": "schematic_port_16",
|
|
110
|
+
"displayName": "VINTP",
|
|
111
|
+
"x": -6.5,
|
|
112
|
+
"y": -1.17
|
|
113
|
+
},
|
|
114
|
+
{
|
|
115
|
+
"pinId": "schematic_port_17",
|
|
116
|
+
"displayName": "VINTN",
|
|
117
|
+
"x": -6.5,
|
|
118
|
+
"y": -1.6400000000000001
|
|
119
|
+
},
|
|
120
|
+
{
|
|
121
|
+
"pinId": "schematic_port_18",
|
|
122
|
+
"displayName": "AVSS",
|
|
123
|
+
"x": -1.9000000000000004,
|
|
124
|
+
"y": 2.365
|
|
125
|
+
},
|
|
126
|
+
{
|
|
127
|
+
"pinId": "schematic_port_19",
|
|
128
|
+
"displayName": "DVSS",
|
|
129
|
+
"x": -1.9000000000000004,
|
|
130
|
+
"y": 2.125
|
|
131
|
+
},
|
|
132
|
+
{
|
|
133
|
+
"pinId": "schematic_port_20",
|
|
134
|
+
"displayName": "PAD",
|
|
135
|
+
"x": -6.5,
|
|
136
|
+
"y": -2.5900000000000003
|
|
137
|
+
}
|
|
138
|
+
]
|
|
139
|
+
},
|
|
140
|
+
{
|
|
141
|
+
"chipId": "schematic_component_1",
|
|
142
|
+
"center": {
|
|
143
|
+
"x": -10.1,
|
|
144
|
+
"y": 0.9499999999999998
|
|
145
|
+
},
|
|
146
|
+
"width": 0.6000000000000014,
|
|
147
|
+
"height": 0.6799999999999999,
|
|
148
|
+
"pins": [
|
|
149
|
+
{
|
|
150
|
+
"pinId": "schematic_port_21",
|
|
151
|
+
"displayName": "anode",
|
|
152
|
+
"x": -10.4,
|
|
153
|
+
"y": 0.95,
|
|
154
|
+
"_facingDirection": "x-"
|
|
155
|
+
},
|
|
156
|
+
{
|
|
157
|
+
"pinId": "schematic_port_22",
|
|
158
|
+
"displayName": "cathode",
|
|
159
|
+
"x": -9.799999999999999,
|
|
160
|
+
"y": 0.95,
|
|
161
|
+
"_facingDirection": "x+"
|
|
162
|
+
}
|
|
163
|
+
]
|
|
164
|
+
},
|
|
165
|
+
{
|
|
166
|
+
"chipId": "schematic_component_2",
|
|
167
|
+
"center": {
|
|
168
|
+
"x": -10.1,
|
|
169
|
+
"y": 0.15
|
|
170
|
+
},
|
|
171
|
+
"width": 0.6000000000000014,
|
|
172
|
+
"height": 0.6799999999999999,
|
|
173
|
+
"pins": [
|
|
174
|
+
{
|
|
175
|
+
"pinId": "schematic_port_23",
|
|
176
|
+
"displayName": "anode",
|
|
177
|
+
"x": -10.4,
|
|
178
|
+
"y": 0.15,
|
|
179
|
+
"_facingDirection": "x-"
|
|
180
|
+
},
|
|
181
|
+
{
|
|
182
|
+
"pinId": "schematic_port_24",
|
|
183
|
+
"displayName": "cathode",
|
|
184
|
+
"x": -9.799999999999999,
|
|
185
|
+
"y": 0.15,
|
|
186
|
+
"_facingDirection": "x+"
|
|
187
|
+
}
|
|
188
|
+
]
|
|
189
|
+
},
|
|
190
|
+
{
|
|
191
|
+
"chipId": "schematic_component_3",
|
|
192
|
+
"center": {
|
|
193
|
+
"x": -8.377499999999998,
|
|
194
|
+
"y": 0.55
|
|
195
|
+
},
|
|
196
|
+
"width": 1.045,
|
|
197
|
+
"height": 0.7600000000000001,
|
|
198
|
+
"pins": [
|
|
199
|
+
{
|
|
200
|
+
"pinId": "schematic_port_25",
|
|
201
|
+
"displayName": "anode",
|
|
202
|
+
"x": -8.45,
|
|
203
|
+
"y": 0.9300000000000002,
|
|
204
|
+
"_facingDirection": "y+"
|
|
205
|
+
},
|
|
206
|
+
{
|
|
207
|
+
"pinId": "schematic_port_26",
|
|
208
|
+
"displayName": "cathode",
|
|
209
|
+
"x": -8.45,
|
|
210
|
+
"y": 0.16999999999999998,
|
|
211
|
+
"_facingDirection": "y-"
|
|
212
|
+
}
|
|
213
|
+
]
|
|
214
|
+
},
|
|
215
|
+
{
|
|
216
|
+
"chipId": "schematic_component_4",
|
|
217
|
+
"center": {
|
|
218
|
+
"x": 1.5825,
|
|
219
|
+
"y": 0.55
|
|
220
|
+
},
|
|
221
|
+
"width": 1.165,
|
|
222
|
+
"height": 0.7600000000000001,
|
|
223
|
+
"pins": [
|
|
224
|
+
{
|
|
225
|
+
"pinId": "schematic_port_27",
|
|
226
|
+
"displayName": "anode",
|
|
227
|
+
"x": 1.45,
|
|
228
|
+
"y": 0.9300000000000002,
|
|
229
|
+
"_facingDirection": "y+"
|
|
230
|
+
},
|
|
231
|
+
{
|
|
232
|
+
"pinId": "schematic_port_28",
|
|
233
|
+
"displayName": "cathode",
|
|
234
|
+
"x": 1.45,
|
|
235
|
+
"y": 0.16999999999999998,
|
|
236
|
+
"_facingDirection": "y-"
|
|
237
|
+
}
|
|
238
|
+
]
|
|
239
|
+
},
|
|
240
|
+
{
|
|
241
|
+
"chipId": "schematic_component_5",
|
|
242
|
+
"center": {
|
|
243
|
+
"x": 0.48249999999999993,
|
|
244
|
+
"y": 0.2
|
|
245
|
+
},
|
|
246
|
+
"width": 1.165,
|
|
247
|
+
"height": 0.7600000000000001,
|
|
248
|
+
"pins": [
|
|
249
|
+
{
|
|
250
|
+
"pinId": "schematic_port_29",
|
|
251
|
+
"displayName": "anode",
|
|
252
|
+
"x": 0.35,
|
|
253
|
+
"y": 0.5800000000000001,
|
|
254
|
+
"_facingDirection": "y+"
|
|
255
|
+
},
|
|
256
|
+
{
|
|
257
|
+
"pinId": "schematic_port_30",
|
|
258
|
+
"displayName": "cathode",
|
|
259
|
+
"x": 0.35,
|
|
260
|
+
"y": -0.18000000000000005,
|
|
261
|
+
"_facingDirection": "y-"
|
|
262
|
+
}
|
|
263
|
+
]
|
|
264
|
+
},
|
|
265
|
+
{
|
|
266
|
+
"chipId": "schematic_component_6",
|
|
267
|
+
"center": {
|
|
268
|
+
"x": -0.6174999999999999,
|
|
269
|
+
"y": -0.14999999999999997
|
|
270
|
+
},
|
|
271
|
+
"width": 1.165,
|
|
272
|
+
"height": 0.7600000000000001,
|
|
273
|
+
"pins": [
|
|
274
|
+
{
|
|
275
|
+
"pinId": "schematic_port_31",
|
|
276
|
+
"displayName": "anode",
|
|
277
|
+
"x": -0.75,
|
|
278
|
+
"y": 0.2300000000000001,
|
|
279
|
+
"_facingDirection": "y+"
|
|
280
|
+
},
|
|
281
|
+
{
|
|
282
|
+
"pinId": "schematic_port_32",
|
|
283
|
+
"displayName": "cathode",
|
|
284
|
+
"x": -0.75,
|
|
285
|
+
"y": -0.53,
|
|
286
|
+
"_facingDirection": "y-"
|
|
287
|
+
}
|
|
288
|
+
]
|
|
289
|
+
},
|
|
290
|
+
{
|
|
291
|
+
"chipId": "schematic_component_7",
|
|
292
|
+
"center": {
|
|
293
|
+
"x": 5.1375,
|
|
294
|
+
"y": 0.5247276749999998
|
|
295
|
+
},
|
|
296
|
+
"width": 0.9550000000000001,
|
|
297
|
+
"height": 1.1494553499999998,
|
|
298
|
+
"pins": [
|
|
299
|
+
{
|
|
300
|
+
"pinId": "schematic_port_33",
|
|
301
|
+
"displayName": "collector",
|
|
302
|
+
"x": 5.49,
|
|
303
|
+
"y": 1.0994553499999997,
|
|
304
|
+
"_facingDirection": "y+"
|
|
305
|
+
},
|
|
306
|
+
{
|
|
307
|
+
"pinId": "schematic_port_34",
|
|
308
|
+
"displayName": "emitter",
|
|
309
|
+
"x": 5.49,
|
|
310
|
+
"y": -0.050000000000000044,
|
|
311
|
+
"_facingDirection": "y-"
|
|
312
|
+
},
|
|
313
|
+
{
|
|
314
|
+
"pinId": "schematic_port_35",
|
|
315
|
+
"displayName": "base",
|
|
316
|
+
"x": 4.66,
|
|
317
|
+
"y": 0.5,
|
|
318
|
+
"_facingDirection": "x-"
|
|
319
|
+
},
|
|
320
|
+
{
|
|
321
|
+
"pinId": "schematic_port_36",
|
|
322
|
+
"displayName": "pin2_internal_1",
|
|
323
|
+
"x": 4.66,
|
|
324
|
+
"y": 0.5,
|
|
325
|
+
"_facingDirection": "x-"
|
|
326
|
+
}
|
|
327
|
+
]
|
|
328
|
+
},
|
|
329
|
+
{
|
|
330
|
+
"chipId": "schematic_component_8",
|
|
331
|
+
"center": {
|
|
332
|
+
"x": 5.585000000000001,
|
|
333
|
+
"y": -1.1
|
|
334
|
+
},
|
|
335
|
+
"width": 1.0900000000000007,
|
|
336
|
+
"height": 0.6000000000000001,
|
|
337
|
+
"pins": [
|
|
338
|
+
{
|
|
339
|
+
"pinId": "schematic_port_37",
|
|
340
|
+
"displayName": "anode",
|
|
341
|
+
"x": 5.49,
|
|
342
|
+
"y": -0.8,
|
|
343
|
+
"_facingDirection": "y+"
|
|
344
|
+
},
|
|
345
|
+
{
|
|
346
|
+
"pinId": "schematic_port_38",
|
|
347
|
+
"displayName": "cathode",
|
|
348
|
+
"x": 5.49,
|
|
349
|
+
"y": -1.4000000000000001,
|
|
350
|
+
"_facingDirection": "y-"
|
|
351
|
+
}
|
|
352
|
+
]
|
|
353
|
+
},
|
|
354
|
+
{
|
|
355
|
+
"chipId": "schematic_component_9",
|
|
356
|
+
"center": {
|
|
357
|
+
"x": -0.7,
|
|
358
|
+
"y": -2.815
|
|
359
|
+
},
|
|
360
|
+
"width": 0.6000000000000001,
|
|
361
|
+
"height": 0.8399999999999999,
|
|
362
|
+
"pins": [
|
|
363
|
+
{
|
|
364
|
+
"pinId": "schematic_port_39",
|
|
365
|
+
"displayName": "pos",
|
|
366
|
+
"x": -1,
|
|
367
|
+
"y": -2.815,
|
|
368
|
+
"_facingDirection": "x-"
|
|
369
|
+
},
|
|
370
|
+
{
|
|
371
|
+
"pinId": "schematic_port_40",
|
|
372
|
+
"displayName": "neg",
|
|
373
|
+
"x": -0.3999999999999999,
|
|
374
|
+
"y": -2.815,
|
|
375
|
+
"_facingDirection": "x+"
|
|
376
|
+
}
|
|
377
|
+
]
|
|
378
|
+
},
|
|
379
|
+
{
|
|
380
|
+
"chipId": "schematic_component_10",
|
|
381
|
+
"center": {
|
|
382
|
+
"x": 6.532500000000001,
|
|
383
|
+
"y": -0.25000000000000006
|
|
384
|
+
},
|
|
385
|
+
"width": 1.165,
|
|
386
|
+
"height": 0.7600000000000001,
|
|
387
|
+
"pins": [
|
|
388
|
+
{
|
|
389
|
+
"pinId": "schematic_port_41",
|
|
390
|
+
"displayName": "anode",
|
|
391
|
+
"x": 6.4,
|
|
392
|
+
"y": 0.13,
|
|
393
|
+
"_facingDirection": "y+"
|
|
394
|
+
},
|
|
395
|
+
{
|
|
396
|
+
"pinId": "schematic_port_42",
|
|
397
|
+
"displayName": "cathode",
|
|
398
|
+
"x": 6.4,
|
|
399
|
+
"y": -0.6300000000000001,
|
|
400
|
+
"_facingDirection": "y-"
|
|
401
|
+
}
|
|
402
|
+
]
|
|
403
|
+
},
|
|
404
|
+
{
|
|
405
|
+
"chipId": "schematic_component_11",
|
|
406
|
+
"center": {
|
|
407
|
+
"x": 7.3,
|
|
408
|
+
"y": 3.05
|
|
409
|
+
},
|
|
410
|
+
"width": 0.5999999999999996,
|
|
411
|
+
"height": 0.6800000000000006,
|
|
412
|
+
"pins": [
|
|
413
|
+
{
|
|
414
|
+
"pinId": "schematic_port_43",
|
|
415
|
+
"displayName": "anode",
|
|
416
|
+
"x": 7,
|
|
417
|
+
"y": 3.05,
|
|
418
|
+
"_facingDirection": "x-"
|
|
419
|
+
},
|
|
420
|
+
{
|
|
421
|
+
"pinId": "schematic_port_44",
|
|
422
|
+
"displayName": "cathode",
|
|
423
|
+
"x": 7.6,
|
|
424
|
+
"y": 3.05,
|
|
425
|
+
"_facingDirection": "x+"
|
|
426
|
+
}
|
|
427
|
+
]
|
|
428
|
+
},
|
|
429
|
+
{
|
|
430
|
+
"chipId": "schematic_component_12",
|
|
431
|
+
"center": {
|
|
432
|
+
"x": 7.3,
|
|
433
|
+
"y": -3.5
|
|
434
|
+
},
|
|
435
|
+
"width": 0.5999999999999996,
|
|
436
|
+
"height": 0.6800000000000006,
|
|
437
|
+
"pins": [
|
|
438
|
+
{
|
|
439
|
+
"pinId": "schematic_port_45",
|
|
440
|
+
"displayName": "anode",
|
|
441
|
+
"x": 7,
|
|
442
|
+
"y": -3.5,
|
|
443
|
+
"_facingDirection": "x-"
|
|
444
|
+
},
|
|
445
|
+
{
|
|
446
|
+
"pinId": "schematic_port_46",
|
|
447
|
+
"displayName": "cathode",
|
|
448
|
+
"x": 7.6,
|
|
449
|
+
"y": -3.5,
|
|
450
|
+
"_facingDirection": "x+"
|
|
451
|
+
}
|
|
452
|
+
]
|
|
453
|
+
},
|
|
454
|
+
{
|
|
455
|
+
"chipId": "schematic_component_13",
|
|
456
|
+
"center": {
|
|
457
|
+
"x": 8.350000000000001,
|
|
458
|
+
"y": 0.30000000000000004
|
|
459
|
+
},
|
|
460
|
+
"width": 0.7400000000000002,
|
|
461
|
+
"height": 1.04,
|
|
462
|
+
"pins": [
|
|
463
|
+
{
|
|
464
|
+
"pinId": "schematic_port_47",
|
|
465
|
+
"displayName": "pos",
|
|
466
|
+
"x": 8.25,
|
|
467
|
+
"y": 0.8200000000000001,
|
|
468
|
+
"_facingDirection": "y+"
|
|
469
|
+
},
|
|
470
|
+
{
|
|
471
|
+
"pinId": "schematic_port_48",
|
|
472
|
+
"displayName": "neg",
|
|
473
|
+
"x": 8.25,
|
|
474
|
+
"y": -0.22000000000000003,
|
|
475
|
+
"_facingDirection": "y-"
|
|
476
|
+
}
|
|
477
|
+
]
|
|
478
|
+
},
|
|
479
|
+
{
|
|
480
|
+
"chipId": "schematic_component_14",
|
|
481
|
+
"center": {
|
|
482
|
+
"x": 9.2,
|
|
483
|
+
"y": 1.63
|
|
484
|
+
},
|
|
485
|
+
"width": 1.0399999999999991,
|
|
486
|
+
"height": 0.6799999999999999,
|
|
487
|
+
"pins": [
|
|
488
|
+
{
|
|
489
|
+
"pinId": "schematic_port_49",
|
|
490
|
+
"displayName": "pos",
|
|
491
|
+
"x": 9.719999999999999,
|
|
492
|
+
"y": 1.7,
|
|
493
|
+
"_facingDirection": "x+"
|
|
494
|
+
},
|
|
495
|
+
{
|
|
496
|
+
"pinId": "schematic_port_50",
|
|
497
|
+
"displayName": "neg",
|
|
498
|
+
"x": 8.68,
|
|
499
|
+
"y": 1.7,
|
|
500
|
+
"_facingDirection": "x-"
|
|
501
|
+
}
|
|
502
|
+
]
|
|
503
|
+
},
|
|
504
|
+
{
|
|
505
|
+
"chipId": "schematic_component_15",
|
|
506
|
+
"center": {
|
|
507
|
+
"x": 10.3,
|
|
508
|
+
"y": 1.7000000000000002
|
|
509
|
+
},
|
|
510
|
+
"width": 0.6000000000000014,
|
|
511
|
+
"height": 0.6799999999999999,
|
|
512
|
+
"pins": [
|
|
513
|
+
{
|
|
514
|
+
"pinId": "schematic_port_51",
|
|
515
|
+
"displayName": "anode",
|
|
516
|
+
"x": 10,
|
|
517
|
+
"y": 1.7,
|
|
518
|
+
"_facingDirection": "x-"
|
|
519
|
+
},
|
|
520
|
+
{
|
|
521
|
+
"pinId": "schematic_port_52",
|
|
522
|
+
"displayName": "cathode",
|
|
523
|
+
"x": 10.600000000000001,
|
|
524
|
+
"y": 1.7,
|
|
525
|
+
"_facingDirection": "x+"
|
|
526
|
+
}
|
|
527
|
+
]
|
|
528
|
+
},
|
|
529
|
+
{
|
|
530
|
+
"chipId": "schematic_component_16",
|
|
531
|
+
"center": {
|
|
532
|
+
"x": 11,
|
|
533
|
+
"y": 0.30000000000000004
|
|
534
|
+
},
|
|
535
|
+
"width": 0.7400000000000002,
|
|
536
|
+
"height": 1.04,
|
|
537
|
+
"pins": [
|
|
538
|
+
{
|
|
539
|
+
"pinId": "schematic_port_53",
|
|
540
|
+
"displayName": "pos",
|
|
541
|
+
"x": 10.9,
|
|
542
|
+
"y": 0.8200000000000001,
|
|
543
|
+
"_facingDirection": "y+"
|
|
544
|
+
},
|
|
545
|
+
{
|
|
546
|
+
"pinId": "schematic_port_54",
|
|
547
|
+
"displayName": "neg",
|
|
548
|
+
"x": 10.9,
|
|
549
|
+
"y": -0.22000000000000003,
|
|
550
|
+
"_facingDirection": "y-"
|
|
551
|
+
}
|
|
552
|
+
]
|
|
553
|
+
}
|
|
554
|
+
],
|
|
555
|
+
"directConnections": [
|
|
556
|
+
{
|
|
557
|
+
"netId": "U1.GATE to U1.AVSS",
|
|
558
|
+
"pinIds": [
|
|
559
|
+
"schematic_port_2",
|
|
560
|
+
"schematic_port_18"
|
|
561
|
+
]
|
|
562
|
+
},
|
|
563
|
+
{
|
|
564
|
+
"netId": "U1.AVSS to U1.DVSS",
|
|
565
|
+
"pinIds": [
|
|
566
|
+
"schematic_port_18",
|
|
567
|
+
"schematic_port_19"
|
|
568
|
+
]
|
|
569
|
+
},
|
|
570
|
+
{
|
|
571
|
+
"netId": "U1.DVSS to U1.GND",
|
|
572
|
+
"pinIds": [
|
|
573
|
+
"schematic_port_19",
|
|
574
|
+
"schematic_port_7"
|
|
575
|
+
]
|
|
576
|
+
},
|
|
577
|
+
{
|
|
578
|
+
"netId": "U1.DVDD_MEM to U1.DVDD",
|
|
579
|
+
"pinIds": [
|
|
580
|
+
"schematic_port_0",
|
|
581
|
+
"schematic_port_1"
|
|
582
|
+
]
|
|
583
|
+
},
|
|
584
|
+
{
|
|
585
|
+
"netId": "U1.DVDD to C2.pin1",
|
|
586
|
+
"pinIds": [
|
|
587
|
+
"schematic_port_1",
|
|
588
|
+
"schematic_port_29"
|
|
589
|
+
]
|
|
590
|
+
},
|
|
591
|
+
{
|
|
592
|
+
"netId": "U1.AVDD to C1.pin1",
|
|
593
|
+
"pinIds": [
|
|
594
|
+
"schematic_port_6",
|
|
595
|
+
"schematic_port_27"
|
|
596
|
+
]
|
|
597
|
+
},
|
|
598
|
+
{
|
|
599
|
+
"netId": "U1.REFCAP to C3.pin1",
|
|
600
|
+
"pinIds": [
|
|
601
|
+
"schematic_port_13",
|
|
602
|
+
"schematic_port_31"
|
|
603
|
+
]
|
|
604
|
+
},
|
|
605
|
+
{
|
|
606
|
+
"netId": "U1.VINPP to R2.pin2",
|
|
607
|
+
"pinIds": [
|
|
608
|
+
"schematic_port_15",
|
|
609
|
+
"schematic_port_22"
|
|
610
|
+
]
|
|
611
|
+
},
|
|
612
|
+
{
|
|
613
|
+
"netId": "R2.pin2 to C6.pin1",
|
|
614
|
+
"pinIds": [
|
|
615
|
+
"schematic_port_22",
|
|
616
|
+
"schematic_port_25"
|
|
617
|
+
]
|
|
618
|
+
},
|
|
619
|
+
{
|
|
620
|
+
"netId": "U1.VINPN to R3.pin2",
|
|
621
|
+
"pinIds": [
|
|
622
|
+
"schematic_port_14",
|
|
623
|
+
"schematic_port_24"
|
|
624
|
+
]
|
|
625
|
+
},
|
|
626
|
+
{
|
|
627
|
+
"netId": "R3.pin2 to C6.pin2",
|
|
628
|
+
"pinIds": [
|
|
629
|
+
"schematic_port_24",
|
|
630
|
+
"schematic_port_26"
|
|
631
|
+
]
|
|
632
|
+
},
|
|
633
|
+
{
|
|
634
|
+
"netId": "U1.VDD to Q1.pin1",
|
|
635
|
+
"pinIds": [
|
|
636
|
+
"schematic_port_3",
|
|
637
|
+
"schematic_port_33"
|
|
638
|
+
]
|
|
639
|
+
},
|
|
640
|
+
{
|
|
641
|
+
"netId": "U1.VDD to R_L1.pin1",
|
|
642
|
+
"pinIds": [
|
|
643
|
+
"schematic_port_3",
|
|
644
|
+
"schematic_port_43"
|
|
645
|
+
]
|
|
646
|
+
},
|
|
647
|
+
{
|
|
648
|
+
"netId": "Q1.pin1 to C4.pin1",
|
|
649
|
+
"pinIds": [
|
|
650
|
+
"schematic_port_33",
|
|
651
|
+
"schematic_port_41"
|
|
652
|
+
]
|
|
653
|
+
},
|
|
654
|
+
{
|
|
655
|
+
"netId": "U1.VOUT to Q1.pin2",
|
|
656
|
+
"pinIds": [
|
|
657
|
+
"schematic_port_5",
|
|
658
|
+
"schematic_port_35"
|
|
659
|
+
]
|
|
660
|
+
},
|
|
661
|
+
{
|
|
662
|
+
"netId": "Q1.pin3 to R1.pin1",
|
|
663
|
+
"pinIds": [
|
|
664
|
+
"schematic_port_34",
|
|
665
|
+
"schematic_port_37"
|
|
666
|
+
]
|
|
667
|
+
},
|
|
668
|
+
{
|
|
669
|
+
"netId": "U1.COMP to R1.pin2",
|
|
670
|
+
"pinIds": [
|
|
671
|
+
"schematic_port_10",
|
|
672
|
+
"schematic_port_38"
|
|
673
|
+
]
|
|
674
|
+
},
|
|
675
|
+
{
|
|
676
|
+
"netId": "U1.DACCAP to C5.pin1",
|
|
677
|
+
"pinIds": [
|
|
678
|
+
"schematic_port_4",
|
|
679
|
+
"schematic_port_39"
|
|
680
|
+
]
|
|
681
|
+
},
|
|
682
|
+
{
|
|
683
|
+
"netId": "U1.FBP to C5.pin2",
|
|
684
|
+
"pinIds": [
|
|
685
|
+
"schematic_port_9",
|
|
686
|
+
"schematic_port_40"
|
|
687
|
+
]
|
|
688
|
+
},
|
|
689
|
+
{
|
|
690
|
+
"netId": "U1.FBP to R_L2.pin1",
|
|
691
|
+
"pinIds": [
|
|
692
|
+
"schematic_port_9",
|
|
693
|
+
"schematic_port_45"
|
|
694
|
+
]
|
|
695
|
+
},
|
|
696
|
+
{
|
|
697
|
+
"netId": "C4.pin2 to C5.pin2",
|
|
698
|
+
"pinIds": [
|
|
699
|
+
"schematic_port_42",
|
|
700
|
+
"schematic_port_40"
|
|
701
|
+
]
|
|
702
|
+
},
|
|
703
|
+
{
|
|
704
|
+
"netId": "R_L1.pin2 to D2.pin2",
|
|
705
|
+
"pinIds": [
|
|
706
|
+
"schematic_port_44",
|
|
707
|
+
"schematic_port_50"
|
|
708
|
+
]
|
|
709
|
+
},
|
|
710
|
+
{
|
|
711
|
+
"netId": "D1.pin1 to D2.pin2",
|
|
712
|
+
"pinIds": [
|
|
713
|
+
"schematic_port_47",
|
|
714
|
+
"schematic_port_50"
|
|
715
|
+
]
|
|
716
|
+
},
|
|
717
|
+
{
|
|
718
|
+
"netId": "D2.pin1 to R4.pin1",
|
|
719
|
+
"pinIds": [
|
|
720
|
+
"schematic_port_49",
|
|
721
|
+
"schematic_port_51"
|
|
722
|
+
]
|
|
723
|
+
},
|
|
724
|
+
{
|
|
725
|
+
"netId": "R_L2.pin2 to D1.pin2",
|
|
726
|
+
"pinIds": [
|
|
727
|
+
"schematic_port_46",
|
|
728
|
+
"schematic_port_48"
|
|
729
|
+
]
|
|
730
|
+
},
|
|
731
|
+
{
|
|
732
|
+
"netId": "D1.pin2 to D3.pin2",
|
|
733
|
+
"pinIds": [
|
|
734
|
+
"schematic_port_48",
|
|
735
|
+
"schematic_port_54"
|
|
736
|
+
]
|
|
737
|
+
},
|
|
738
|
+
{
|
|
739
|
+
"netId": "R4.pin2 to D3.pin1",
|
|
740
|
+
"pinIds": [
|
|
741
|
+
"schematic_port_52",
|
|
742
|
+
"schematic_port_53"
|
|
743
|
+
]
|
|
744
|
+
}
|
|
745
|
+
],
|
|
746
|
+
"netConnections": [
|
|
747
|
+
{
|
|
748
|
+
"netId": "GND",
|
|
749
|
+
"isGround": true,
|
|
750
|
+
"netLabelWidth": 0.42,
|
|
751
|
+
"netLabelHeight": 0.48,
|
|
752
|
+
"pinIds": [
|
|
753
|
+
"schematic_port_2",
|
|
754
|
+
"schematic_port_7",
|
|
755
|
+
"schematic_port_10",
|
|
756
|
+
"schematic_port_18",
|
|
757
|
+
"schematic_port_19",
|
|
758
|
+
"schematic_port_20",
|
|
759
|
+
"schematic_port_28",
|
|
760
|
+
"schematic_port_30",
|
|
761
|
+
"schematic_port_32",
|
|
762
|
+
"schematic_port_38"
|
|
763
|
+
]
|
|
764
|
+
},
|
|
765
|
+
{
|
|
766
|
+
"netId": "VBRGP",
|
|
767
|
+
"isGround": false,
|
|
768
|
+
"netLabelWidth": 0.42,
|
|
769
|
+
"netLabelHeight": 0.72,
|
|
770
|
+
"pinIds": [
|
|
771
|
+
"schematic_port_12"
|
|
772
|
+
]
|
|
773
|
+
},
|
|
774
|
+
{
|
|
775
|
+
"netId": "VINPP",
|
|
776
|
+
"isGround": false,
|
|
777
|
+
"netLabelWidth": 0.42,
|
|
778
|
+
"netLabelHeight": 0.72,
|
|
779
|
+
"pinIds": [
|
|
780
|
+
"schematic_port_21"
|
|
781
|
+
]
|
|
782
|
+
},
|
|
783
|
+
{
|
|
784
|
+
"netId": "VINPN",
|
|
785
|
+
"isGround": false,
|
|
786
|
+
"netLabelWidth": 0.42,
|
|
787
|
+
"netLabelHeight": 0.72,
|
|
788
|
+
"pinIds": [
|
|
789
|
+
"schematic_port_23"
|
|
790
|
+
]
|
|
791
|
+
},
|
|
792
|
+
{
|
|
793
|
+
"netId": "Ireturn",
|
|
794
|
+
"isGround": false,
|
|
795
|
+
"netLabelWidth": 0.96,
|
|
796
|
+
"pinIds": [
|
|
797
|
+
"schematic_port_46",
|
|
798
|
+
"schematic_port_48",
|
|
799
|
+
"schematic_port_54"
|
|
800
|
+
]
|
|
801
|
+
},
|
|
802
|
+
{
|
|
803
|
+
"netId": "Vdd",
|
|
804
|
+
"isGround": false,
|
|
805
|
+
"netLabelWidth": 0.42,
|
|
806
|
+
"netLabelHeight": 0.48,
|
|
807
|
+
"pinIds": [
|
|
808
|
+
"schematic_port_52",
|
|
809
|
+
"schematic_port_53"
|
|
810
|
+
]
|
|
811
|
+
}
|
|
812
|
+
],
|
|
813
|
+
"textBoxes": [
|
|
814
|
+
{
|
|
815
|
+
"chipId": "schematic_component_0",
|
|
816
|
+
"center": {
|
|
817
|
+
"x": -5.4399999999999995,
|
|
818
|
+
"y": -4.13
|
|
819
|
+
},
|
|
820
|
+
"width": 1.3200000000000003,
|
|
821
|
+
"height": 0.17999999999999972,
|
|
822
|
+
"text": "PGA300ARHHR"
|
|
823
|
+
},
|
|
824
|
+
{
|
|
825
|
+
"chipId": "schematic_component_0",
|
|
826
|
+
"center": {
|
|
827
|
+
"x": -5.9799999999999995,
|
|
828
|
+
"y": 4.115
|
|
829
|
+
},
|
|
830
|
+
"width": 0.35999999999999943,
|
|
831
|
+
"height": 0.2499999999999991,
|
|
832
|
+
"text": "U1"
|
|
833
|
+
}
|
|
834
|
+
],
|
|
835
|
+
"availableNetLabelOrientations": {
|
|
836
|
+
"VBRGP": [
|
|
837
|
+
"y+"
|
|
838
|
+
],
|
|
839
|
+
"VINPP": [
|
|
840
|
+
"y+"
|
|
841
|
+
],
|
|
842
|
+
"VINPN": [
|
|
843
|
+
"y+"
|
|
844
|
+
],
|
|
845
|
+
"Vdd": [
|
|
846
|
+
"y+"
|
|
847
|
+
],
|
|
848
|
+
"Ireturn": [
|
|
849
|
+
"x-",
|
|
850
|
+
"x+"
|
|
851
|
+
],
|
|
852
|
+
"GND": [
|
|
853
|
+
"y-"
|
|
854
|
+
]
|
|
855
|
+
},
|
|
856
|
+
"maxMspPairDistance": 100,
|
|
857
|
+
"_hideRatsNet": false
|
|
858
|
+
}
|