@tscircuit/schematic-trace-solver 0.0.137 → 0.0.141

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (21) hide show
  1. package/.github/workflows/bun-pver-release.yml +7 -3
  2. package/dist/index.d.ts +6 -0
  3. package/dist/index.js +304 -36
  4. package/lib/solvers/AvailableNetOrientationSolver/AvailableNetOrientationObstacleIndex.ts +182 -0
  5. package/lib/solvers/AvailableNetOrientationSolver/AvailableNetOrientationSolver.ts +67 -25
  6. package/lib/solvers/AvailableNetOrientationSolver/constants.ts +2 -0
  7. package/lib/solvers/Example28Solver/labelMovement.ts +71 -0
  8. package/lib/solvers/SchematicTracePipelineSolver/SchematicTracePipelineSolver.ts +12 -4
  9. package/lib/solvers/TraceOverlapShiftSolver/TraceOverlapShiftSolver.ts +60 -4
  10. package/package.json +5 -1
  11. package/tests/bug-reports/bug-report-20260819T091818Z/__snapshots__/bug-report-20260819T091818Z.snap.svg +237 -0
  12. package/tests/bug-reports/bug-report-20260819T091818Z/bug-report-20260819T091818Z.json +1052 -0
  13. package/tests/bug-reports/bug-report-20260819T091818Z/bug-report-20260819T091818Z.test.ts +33 -0
  14. package/tests/repros/__snapshots__/board-1273-trace-overlap-cycle.snap.svg +542 -0
  15. package/tests/repros/__snapshots__/repro-board-648-esp12f-section.snap.svg +124 -0
  16. package/tests/repros/assets/board-1273-trace-overlap-cycle.input.json +3519 -0
  17. package/tests/repros/assets/repro-board-648-esp12f-section.input.json +537 -0
  18. package/tests/repros/board-1273-trace-overlap-cycle.test.ts +30 -0
  19. package/tests/repros/repro-board-648-esp12f-section.test.ts +13 -0
  20. package/tests/repros/repro161-power-section-autolayout.test.ts +7 -0
  21. package/tests/solvers/AvailableNetOrientationSolver/AvailableNetOrientationObstacleIndex.test.ts +122 -0
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610
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611
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612
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613
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614
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615
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616
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617
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618
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619
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620
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621
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622
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623
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624
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625
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626
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627
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628
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629
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630
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631
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632
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633
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634
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635
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636
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637
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638
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639
+ "x": 2.98,
640
+ "y": 5.699999999999996
641
+ },
642
+ {
643
+ "pinId": "schematic_port_216",
644
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645
+ "y": 5.899999999999995
646
+ },
647
+ {
648
+ "pinId": "schematic_port_217",
649
+ "x": 2.98,
650
+ "y": 6.099999999999994
651
+ },
652
+ {
653
+ "pinId": "schematic_port_218",
654
+ "x": 2.98,
655
+ "y": 6.299999999999994
656
+ }
657
+ ],
658
+ "sectionId": "RV1106G2 core"
659
+ }
660
+ ],
661
+ "directConnections": [],
662
+ "netConnections": [
663
+ {
664
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665
+ "netLabelWidth": 0.42,
666
+ "netLabelHeight": 0.48,
667
+ "pinIds": [
668
+ "schematic_port_126",
669
+ "schematic_port_218"
670
+ ]
671
+ },
672
+ {
673
+ "netId": "VCC_3V3",
674
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675
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676
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677
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678
+ "schematic_port_108",
679
+ "schematic_port_117",
680
+ "schematic_port_132",
681
+ "schematic_port_150",
682
+ "schematic_port_170",
683
+ "schematic_port_177",
684
+ "schematic_port_190",
685
+ "schematic_port_197"
686
+ ]
687
+ },
688
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689
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690
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691
+ "netLabelHeight": 0.96,
692
+ "pinIds": [
693
+ "schematic_port_90",
694
+ "schematic_port_113",
695
+ "schematic_port_120",
696
+ "schematic_port_142",
697
+ "schematic_port_159",
698
+ "schematic_port_185"
699
+ ]
700
+ },
701
+ {
702
+ "netId": "VCC_DDR_1V35",
703
+ "netLabelWidth": 0.42,
704
+ "netLabelHeight": 1.56,
705
+ "pinIds": [
706
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707
+ "schematic_port_139",
708
+ "schematic_port_145"
709
+ ]
710
+ },
711
+ {
712
+ "netId": "VDD_0V9",
713
+ "netLabelWidth": 0.42,
714
+ "netLabelHeight": 0.96,
715
+ "pinIds": [
716
+ "schematic_port_99",
717
+ "schematic_port_140",
718
+ "schematic_port_143",
719
+ "schematic_port_144",
720
+ "schematic_port_156",
721
+ "schematic_port_160",
722
+ "schematic_port_171",
723
+ "schematic_port_192",
724
+ "schematic_port_204",
725
+ "schematic_port_205"
726
+ ]
727
+ },
728
+ {
729
+ "netId": "CAM_MCLK",
730
+ "netLabelWidth": 1.08,
731
+ "pinIds": [
732
+ "schematic_port_91"
733
+ ]
734
+ },
735
+ {
736
+ "netId": "CAM_RST",
737
+ "netLabelWidth": 0.96,
738
+ "pinIds": [
739
+ "schematic_port_92"
740
+ ]
741
+ },
742
+ {
743
+ "netId": "FSPI_IO3",
744
+ "netLabelWidth": 1.08,
745
+ "pinIds": [
746
+ "schematic_port_128"
747
+ ]
748
+ },
749
+ {
750
+ "netId": "FSPI_IO0",
751
+ "netLabelWidth": 1.08,
752
+ "pinIds": [
753
+ "schematic_port_130"
754
+ ]
755
+ },
756
+ {
757
+ "netId": "FSPI_IO2",
758
+ "netLabelWidth": 1.08,
759
+ "pinIds": [
760
+ "schematic_port_133"
761
+ ]
762
+ },
763
+ {
764
+ "netId": "FSPI_CS",
765
+ "netLabelWidth": 0.96,
766
+ "pinIds": [
767
+ "schematic_port_136"
768
+ ]
769
+ },
770
+ {
771
+ "netId": "FSPI_CLK",
772
+ "netLabelWidth": 1.08,
773
+ "pinIds": [
774
+ "schematic_port_137"
775
+ ]
776
+ },
777
+ {
778
+ "netId": "GPIO0_A2",
779
+ "netLabelWidth": 1.08,
780
+ "pinIds": [
781
+ "schematic_port_149"
782
+ ]
783
+ },
784
+ {
785
+ "netId": "I2C1_SCL",
786
+ "netLabelWidth": 1.08,
787
+ "pinIds": [
788
+ "schematic_port_153"
789
+ ]
790
+ },
791
+ {
792
+ "netId": "I2C1_SDA",
793
+ "netLabelWidth": 1.08,
794
+ "pinIds": [
795
+ "schematic_port_154"
796
+ ]
797
+ },
798
+ {
799
+ "netId": "RESET_N",
800
+ "netLabelWidth": 0.96,
801
+ "pinIds": [
802
+ "schematic_port_155"
803
+ ]
804
+ },
805
+ {
806
+ "netId": "GPIO1_A1",
807
+ "netLabelWidth": 1.08,
808
+ "pinIds": [
809
+ "schematic_port_162"
810
+ ]
811
+ },
812
+ {
813
+ "netId": "ETH_RXN",
814
+ "netLabelWidth": 0.96,
815
+ "pinIds": [
816
+ "schematic_port_186"
817
+ ]
818
+ },
819
+ {
820
+ "netId": "ETH_RXP",
821
+ "netLabelWidth": 0.96,
822
+ "pinIds": [
823
+ "schematic_port_187"
824
+ ]
825
+ },
826
+ {
827
+ "netId": "ETH_TXN",
828
+ "netLabelWidth": 0.96,
829
+ "pinIds": [
830
+ "schematic_port_188"
831
+ ]
832
+ },
833
+ {
834
+ "netId": "ETH_TXP",
835
+ "netLabelWidth": 0.96,
836
+ "pinIds": [
837
+ "schematic_port_189"
838
+ ]
839
+ },
840
+ {
841
+ "netId": "ETH_REXT",
842
+ "netLabelWidth": 1.08,
843
+ "pinIds": [
844
+ "schematic_port_191"
845
+ ]
846
+ }
847
+ ],
848
+ "textBoxes": [
849
+ {
850
+ "chipId": "schematic_component_30",
851
+ "center": {
852
+ "x": -0.14000000000000012,
853
+ "y": -6.63
854
+ },
855
+ "width": 0.96,
856
+ "height": 0.17999999999999972,
857
+ "text": "RV1106G2"
858
+ },
859
+ {
860
+ "chipId": "schematic_component_30",
861
+ "center": {
862
+ "x": -0.5000000000000001,
863
+ "y": 6.615
864
+ },
865
+ "width": 0.36000000000000004,
866
+ "height": 0.2499999999999991,
867
+ "text": "U1"
868
+ }
869
+ ],
870
+ "availableNetLabelOrientations": {
871
+ "FSPI_IO2": [
872
+ "x-",
873
+ "x+"
874
+ ],
875
+ "ETH_REXT": [
876
+ "x-",
877
+ "x+"
878
+ ],
879
+ "GND": [
880
+ "y-"
881
+ ],
882
+ "VBUS_5V": [
883
+ "y+"
884
+ ],
885
+ "VCC_3V3": [
886
+ "y+"
887
+ ],
888
+ "VCC_1V8": [
889
+ "y+"
890
+ ],
891
+ "VCC_DDR_1V35": [
892
+ "y+"
893
+ ],
894
+ "VDD_0V9": [
895
+ "y+"
896
+ ],
897
+ "B33_SW": [
898
+ "x-",
899
+ "x+"
900
+ ],
901
+ "B33_FB": [
902
+ "x-",
903
+ "x+"
904
+ ],
905
+ "B18_SW": [
906
+ "x-",
907
+ "x+"
908
+ ],
909
+ "B18_FB": [
910
+ "x-",
911
+ "x+"
912
+ ],
913
+ "BDD_SW": [
914
+ "x-",
915
+ "x+"
916
+ ],
917
+ "BDD_FB": [
918
+ "x-",
919
+ "x+"
920
+ ],
921
+ "B09_SW": [
922
+ "x-",
923
+ "x+"
924
+ ],
925
+ "B09_FB": [
926
+ "x-",
927
+ "x+"
928
+ ],
929
+ "RESET_N": [
930
+ "x-",
931
+ "x+"
932
+ ],
933
+ "POWER_LED": [
934
+ "x-",
935
+ "x+"
936
+ ],
937
+ "FSPI_IO3": [
938
+ "x-",
939
+ "x+"
940
+ ],
941
+ "FSPI_IO0": [
942
+ "x-",
943
+ "x+"
944
+ ],
945
+ "FSPI_CS": [
946
+ "x-",
947
+ "x+"
948
+ ],
949
+ "FSPI_CLK": [
950
+ "x-",
951
+ "x+"
952
+ ],
953
+ "USB_CC1": [
954
+ "x-",
955
+ "x+"
956
+ ],
957
+ "USB_CC2": [
958
+ "x-",
959
+ "x+"
960
+ ],
961
+ "USB_DM": [
962
+ "x-",
963
+ "x+"
964
+ ],
965
+ "USB_DP": [
966
+ "x-",
967
+ "x+"
968
+ ],
969
+ "ETH_RXN": [
970
+ "x-",
971
+ "x+"
972
+ ],
973
+ "ETH_RXP": [
974
+ "x-",
975
+ "x+"
976
+ ],
977
+ "ETH_TXN": [
978
+ "x-",
979
+ "x+"
980
+ ],
981
+ "ETH_TXP": [
982
+ "x-",
983
+ "x+"
984
+ ],
985
+ "ETH_TXP_J": [
986
+ "x-",
987
+ "x+"
988
+ ],
989
+ "ETH_TXN_J": [
990
+ "x-",
991
+ "x+"
992
+ ],
993
+ "ETH_RXP_J": [
994
+ "x-",
995
+ "x+"
996
+ ],
997
+ "ETH_RXN_J": [
998
+ "x-",
999
+ "x+"
1000
+ ],
1001
+ "ETH_CT_TX": [
1002
+ "x-",
1003
+ "x+"
1004
+ ],
1005
+ "ETH_CT_RX": [
1006
+ "x-",
1007
+ "x+"
1008
+ ],
1009
+ "CAM_MCLK": [
1010
+ "x-",
1011
+ "x+"
1012
+ ],
1013
+ "CAM_MCLK_J": [
1014
+ "x-",
1015
+ "x+"
1016
+ ],
1017
+ "CAM_RST": [
1018
+ "x-",
1019
+ "x+"
1020
+ ],
1021
+ "CAM_RST_J": [
1022
+ "x-",
1023
+ "x+"
1024
+ ],
1025
+ "I2C1_SCL_CAM": [
1026
+ "x-",
1027
+ "x+"
1028
+ ],
1029
+ "I2C1_SDA_CAM": [
1030
+ "x-",
1031
+ "x+"
1032
+ ],
1033
+ "GPIO0_A2": [
1034
+ "x-",
1035
+ "x+"
1036
+ ],
1037
+ "I2C1_SCL": [
1038
+ "x-",
1039
+ "x+"
1040
+ ],
1041
+ "I2C1_SDA": [
1042
+ "x-",
1043
+ "x+"
1044
+ ],
1045
+ "GPIO1_A1": [
1046
+ "x-",
1047
+ "x+"
1048
+ ]
1049
+ },
1050
+ "maxMspPairDistance": 2.4,
1051
+ "_hideRatsNet": false
1052
+ }