@tscircuit/schematic-trace-solver 0.0.120 → 0.0.122

package/tests/repros/assets/repro-nrf52810-clock-routing.input.json

@@ -0,0 +1,234 @@
+{
+  "chips": [
+    {
+      "chipId": "schematic_component_30",
+      "center": { "x": -7, "y": 5 },
+      "width": 3.1999999999999993,
+      "height": 0.5999999999999996,
+      "pins": [
+        { "pinId": "schematic_port_38", "x": -5.4, "y": 5.1 },
+        { "pinId": "schematic_port_39", "x": -5.4, "y": 4.9 }
+      ],
+      "sectionId": "hf-clock"
+    },
+    {
+      "chipId": "schematic_component_31",
+      "center": { "x": -4, "y": 5 },
+      "width": 1.08,
+      "height": 1.42,
+      "pins": [
+        {
+          "pinId": "schematic_port_40",
+          "x": -4,
+          "y": 5.71,
+          "_facingDirection": "y+"
+        },
+        {
+          "pinId": "schematic_port_41",
+          "x": -4.02,
+          "y": 4.29,
+          "_facingDirection": "y-"
+        },
+        {
+          "pinId": "schematic_port_42",
+          "x": -4.54,
+          "y": 4.99,
+          "_facingDirection": "x-"
+        },
+        {
+          "pinId": "schematic_port_43",
+          "x": -3.46,
+          "y": 4.99,
+          "_facingDirection": "x+"
+        }
+      ],
+      "sectionId": "hf-clock"
+    },
+    {
+      "chipId": "schematic_component_32",
+      "center": { "x": -4.9275, "y": 3 },
+      "width": 1.0450000000000008,
+      "height": 0.7600000000000007,
+      "pins": [
+        {
+          "pinId": "schematic_port_175",
+          "x": -5,
+          "y": 3.3800000000000003,
+          "_facingDirection": "y+"
+        },
+        {
+          "pinId": "schematic_port_176",
+          "x": -5,
+          "y": 2.6199999999999997,
+          "_facingDirection": "y-"
+        }
+      ],
+      "sectionId": "hf-clock"
+    },
+    {
+      "chipId": "schematic_component_33",
+      "center": { "x": -2.9275, "y": 3 },
+      "width": 1.0450000000000004,
+      "height": 0.7600000000000007,
+      "pins": [
+        {
+          "pinId": "schematic_port_177",
+          "x": -3,
+          "y": 3.3800000000000003,
+          "_facingDirection": "y+"
+        },
+        {
+          "pinId": "schematic_port_178",
+          "x": -3,
+          "y": 2.6199999999999997,
+          "_facingDirection": "y-"
+        }
+      ],
+      "sectionId": "hf-clock"
+    },
+    {
+      "chipId": "schematic_component_34",
+      "center": { "x": 3, "y": 5 },
+      "width": 3.1999999999999993,
+      "height": 0.5999999999999996,
+      "pins": [
+        { "pinId": "schematic_port_44", "x": 4.6, "y": 5.1 },
+        { "pinId": "schematic_port_45", "x": 4.6, "y": 4.9 }
+      ],
+      "sectionId": "lf-clock"
+    },
+    {
+      "chipId": "schematic_component_35",
+      "center": { "x": 6, "y": 5 },
+      "width": 1.0999999999999996,
+      "height": 0.8499999999999996,
+      "pins": [
+        {
+          "pinId": "schematic_port_46",
+          "x": 5.45,
+          "y": 5,
+          "_facingDirection": "x-"
+        },
+        {
+          "pinId": "schematic_port_47",
+          "x": 6.55,
+          "y": 5,
+          "_facingDirection": "x+"
+        }
+      ],
+      "sectionId": "lf-clock"
+    },
+    {
+      "chipId": "schematic_component_36",
+      "center": { "x": 5.0725, "y": 3 },
+      "width": 1.0450000000000008,
+      "height": 0.7600000000000007,
+      "pins": [
+        {
+          "pinId": "schematic_port_181",
+          "x": 5,
+          "y": 3.3800000000000003,
+          "_facingDirection": "y+"
+        },
+        {
+          "pinId": "schematic_port_182",
+          "x": 5,
+          "y": 2.6199999999999997,
+          "_facingDirection": "y-"
+        }
+      ],
+      "sectionId": "lf-clock"
+    },
+    {
+      "chipId": "schematic_component_37",
+      "center": { "x": 7.0725, "y": 3 },
+      "width": 1.0450000000000008,
+      "height": 0.7600000000000007,
+      "pins": [
+        {
+          "pinId": "schematic_port_183",
+          "x": 7,
+          "y": 3.3800000000000003,
+          "_facingDirection": "y+"
+        },
+        {
+          "pinId": "schematic_port_184",
+          "x": 7,
+          "y": 2.6199999999999997,
+          "_facingDirection": "y-"
+        }
+      ],
+      "sectionId": "lf-clock"
+    }
+  ],
+  "directConnections": [
+    {
+      "netId": ".U1 > .XC1 to .X1 > .XTAL1",
+      "pinIds": ["schematic_port_38", "schematic_port_42"]
+    },
+    {
+      "netId": ".U1 > .XC2 to .X1 > .XTAL2",
+      "pinIds": ["schematic_port_39", "schematic_port_43"]
+    },
+    {
+      "netId": ".X1 > .XTAL1 to .C1 > .pin1",
+      "pinIds": ["schematic_port_42", "schematic_port_175"]
+    },
+    {
+      "netId": ".X1 > .XTAL2 to .C2 > .pin1",
+      "pinIds": ["schematic_port_43", "schematic_port_177"]
+    },
+    {
+      "netId": ".U1 > .XL1 to .X2 > .OSC1",
+      "pinIds": ["schematic_port_44", "schematic_port_46"]
+    },
+    {
+      "netId": ".U1 > .XL2 to .X2 > .OSC2",
+      "pinIds": ["schematic_port_45", "schematic_port_47"]
+    },
+    {
+      "netId": ".X2 > .OSC1 to .C11 > .pin1",
+      "pinIds": ["schematic_port_46", "schematic_port_181"]
+    },
+    {
+      "netId": ".X2 > .OSC2 to .C12 > .pin1",
+      "pinIds": ["schematic_port_47", "schematic_port_183"]
+    }
+  ],
+  "netConnections": [
+    {
+      "netId": "GND",
+      "netLabelWidth": 0.42,
+      "netLabelHeight": 0.48,
+      "pinIds": [
+        "schematic_port_40",
+        "schematic_port_41",
+        "schematic_port_176",
+        "schematic_port_178",
+        "schematic_port_182",
+        "schematic_port_184"
+      ]
+    }
+  ],
+  "textBoxes": [
+    {
+      "chipId": "schematic_component_30",
+      "center": { "x": -7.539999999999999, "y": 5.43 },
+      "width": 1.3200000000000003,
+      "height": 0.17999999999999972,
+      "text": "U1 HF Clock"
+    },
+    {
+      "chipId": "schematic_component_34",
+      "center": { "x": 2.46, "y": 5.43 },
+      "width": 1.32,
+      "height": 0.17999999999999972,
+      "text": "U1 LF Clock"
+    }
+  ],
+  "availableNetLabelOrientations": {
+    "GND": ["y-"]
+  },
+  "maxMspPairDistance": 2.4,
+  "_hideRatsNet": false
+}

package/tests/repros/repro-bq25895-cross-net-trace-overlap.test.ts

@@ -0,0 +1,88 @@
+import { expect, test } from "bun:test"
+import { SchematicTracePipelineSolver } from "lib/solvers/SchematicTracePipelineSolver/SchematicTracePipelineSolver"
+import type { SolvedTracePath } from "lib/solvers/SchematicTraceLinesSolver/SchematicTraceLinesSolver"
+import { getTraceCorners } from "lib/solvers/RailNetLabelCornerPlacementSolver/geometry"
+import { SCHEMATIC_TRACE_MIN_VISUAL_CENTERLINE_CLEARANCE } from "lib/utils/doesPathCoincideWithTraces"
+import "tests/fixtures/matcher"
+import inputProblem from "./assets/repro-bq25895-cross-net-trace-overlap.input.json"
+
+const EPSILON = 1e-6
+
+const tracesHaveInsufficientParallelClearance = (
+  firstTrace: SolvedTracePath,
+  secondTrace: SolvedTracePath,
+) => {
+  for (
+    let firstPointIndex = 0;
+    firstPointIndex < firstTrace.tracePath.length - 1;
+    firstPointIndex++
+  ) {
+    const firstStart = firstTrace.tracePath[firstPointIndex]!
+    const firstEnd = firstTrace.tracePath[firstPointIndex + 1]!
+    const firstIsVertical = Math.abs(firstStart.x - firstEnd.x) < EPSILON
+    if (!firstIsVertical) continue
+
+    for (
+      let secondPointIndex = 0;
+      secondPointIndex < secondTrace.tracePath.length - 1;
+      secondPointIndex++
+    ) {
+      const secondStart = secondTrace.tracePath[secondPointIndex]!
+      const secondEnd = secondTrace.tracePath[secondPointIndex + 1]!
+      const secondIsVertical = Math.abs(secondStart.x - secondEnd.x) < EPSILON
+      if (!secondIsVertical) continue
+
+      const xSeparation = Math.abs(firstStart.x - secondStart.x)
+      const verticalOverlap =
+        Math.min(
+          Math.max(firstStart.y, firstEnd.y),
+          Math.max(secondStart.y, secondEnd.y),
+        ) -
+        Math.max(
+          Math.min(firstStart.y, firstEnd.y),
+          Math.min(secondStart.y, secondEnd.y),
+        )
+
+      if (
+        xSeparation + EPSILON <
+          SCHEMATIC_TRACE_MIN_VISUAL_CENTERLINE_CLEARANCE &&
+        verticalOverlap > EPSILON
+      ) {
+        return true
+      }
+    }
+  }
+
+  return false
+}
+
+test("BQ25895 CE and GND traces keep visible parallel clearance", () => {
+  const solver = new SchematicTracePipelineSolver(inputProblem as any)
+  solver.solve()
+
+  const traces = solver.netLabelTraceCollisionSolver!.getOutput().traces
+  const ceTraces = traces.filter(
+    (trace) => trace.userNetId === "J3.pin6 to U1.CE",
+  )
+  const groundTraces = traces.filter((trace) => trace.userNetId === "GND")
+  const hasInsufficientCeAndGroundClearance = ceTraces.some((ceTrace) =>
+    groundTraces.some((groundTrace) =>
+      tracesHaveInsufficientParallelClearance(ceTrace, groundTrace),
+    ),
+  )
+
+  expect(hasInsufficientCeAndGroundClearance).toBe(false)
+
+  const output = solver.netLabelTraceCollisionSolver!.getOutput()
+  const groundLabel = output.netLabelPlacements.find(
+    (label) => label.netId === "GND",
+  )!
+  const groundLabelTrace = output.traces.find((trace) =>
+    groundLabel.mspConnectionPairIds.includes(trace.mspPairId),
+  )!
+
+  expect(getTraceCorners(groundLabelTrace.tracePath)).toContainEqual(
+    groundLabel.anchorPoint,
+  )
+  expect(solver).toMatchSolverSnapshot(import.meta.path)
+})

package/tests/repros/repro-missing-trace-netlabel.test.ts

@@ -1,4 +1,5 @@
 import { expect, test } from "bun:test"
+import { getTraceCorners } from "lib/solvers/RailNetLabelCornerPlacementSolver/geometry"
 import { SchematicTracePipelineSolver } from "lib/solvers/SchematicTracePipelineSolver/SchematicTracePipelineSolver"
 import inputProblem from "./assets/repro-missing-trace-netlabel.input.json"
 import "tests/fixtures/matcher"
@@ -10,5 +11,16 @@ test("repro148 missing trace becomes net labels", () => {
 
   solver.solve()
 
+  const output = solver.sameNetJunctionAlignmentSolver!.getOutput()
+  const powerLabel = output.netLabelPlacements.find(
+    (label) => label.netId === "V3V3",
+  )!
+  const powerTrace = output.traces.find((trace) =>
+    powerLabel.mspConnectionPairIds.includes(trace.mspPairId),
+  )!
+
+  expect(getTraceCorners(powerTrace.tracePath)).toContainEqual(
+    powerLabel.anchorPoint,
+  )
   expect(solver).toMatchSolverSnapshot(import.meta.path)
 })

package/tests/repros/repro-netlabel-overlap-trace.test.ts

@@ -1,4 +1,10 @@
 import { expect, test } from "bun:test"
+import { traceCrossesBoundsInterior } from "lib/solvers/AvailableNetOrientationSolver/geometry"
+import {
+  getTraceCorners,
+  rectsOverlap,
+} from "lib/solvers/RailNetLabelCornerPlacementSolver/geometry"
+import { getRectBounds } from "lib/solvers/NetLabelPlacementSolver/SingleNetLabelPlacementSolver/geometry"
 import { SchematicTracePipelineSolver } from "lib/solvers/SchematicTracePipelineSolver/SchematicTracePipelineSolver"
 import inputProblem from "./assets/repro-netlabel-overlap-trace.input.json"
 import "tests/fixtures/matcher"
@@ -10,5 +16,37 @@ test("repro147 netlabel overlaps trace", () => {
 
   solver.solve()
 
+  const output = solver.sameNetJunctionAlignmentSolver!.getOutput()
+  const groundLabel = output.netLabelPlacements.find(
+    (label) => label.netId === "GND",
+  )!
+  const groundTrace = output.traces.find((trace) =>
+    groundLabel.mspConnectionPairIds.includes(trace.mspPairId),
+  )!
+  const groundLabelBounds = getRectBounds(
+    groundLabel.center,
+    groundLabel.width,
+    groundLabel.height,
+  )
+
+  expect(getTraceCorners(groundTrace.tracePath)).toContainEqual(
+    groundLabel.anchorPoint,
+  )
+  expect(
+    inputProblem.chips.some((chip) =>
+      rectsOverlap(
+        groundLabelBounds,
+        getRectBounds(chip.center, chip.width, chip.height),
+      ),
+    ),
+  ).toBe(false)
+  expect(
+    traceCrossesBoundsInterior(
+      groundLabelBounds,
+      Object.fromEntries(
+        output.traces.map((trace) => [trace.mspPairId, trace]),
+      ),
+    ),
+  ).toBe(false)
   expect(solver).toMatchSolverSnapshot(import.meta.path)
 })

package/tests/repros/repro-nrf52810-clock-routing.test.ts

@@ -0,0 +1,28 @@
+import { expect, test } from "bun:test"
+import { SchematicTracePipelineSolver } from "lib/solvers/SchematicTracePipelineSolver/SchematicTracePipelineSolver"
+import "tests/fixtures/matcher"
+import inputProblem from "./assets/repro-nrf52810-clock-routing.input.json"
+
+// Extracted from the nRF52810 clock-source schematic shown in the reproduction:
+// a four-pin 32 MHz crystal and a two-pin 32.768 kHz crystal, each connected
+// to an MCU schematic box, two load capacitors, and section-local GND labels.
+test("repro nRF52810 HF and LF crystal trace/net-label routing", () => {
+  const solver = new SchematicTracePipelineSolver(inputProblem as any)
+
+  solver.solve()
+
+  expect(solver.mspConnectionPairSolver?.mspConnectionPairs).toHaveLength(11)
+  expect(
+    solver.schematicTraceLinesSolver?.failedConnectionPairs.map(
+      (pair) => pair.mspPairId,
+    ),
+  ).toEqual([
+    "schematic_port_39-schematic_port_43", // U1.XC2 -> X1.XTAL2
+    "schematic_port_45-schematic_port_47", // U1.XL2 -> X2.OSC2
+    "schematic_port_41-schematic_port_40", // X1.GND2 -> X1.GND1
+  ])
+  expect(
+    solver.sameNetJunctionAlignmentSolver?.getOutput().netLabelPlacements,
+  ).toHaveLength(10)
+  expect(solver).toMatchSolverSnapshot(import.meta.path)
+})

package/tests/solvers/TraceCleanupSolver/alignSameNetRails-trace-clearance.test.ts

@@ -0,0 +1,68 @@
+import { expect, test } from "bun:test"
+import {
+  SCHEMATIC_TRACE_MIN_VISUAL_CENTERLINE_CLEARANCE,
+  SCHEMATIC_TRACE_STROKE_WIDTH,
+} from "lib/utils/doesPathCoincideWithTraces"
+import {
+  align,
+  createTrace,
+  getVerticalRailTraces,
+} from "./fixtures/alignSameNetRails"
+
+test("aligns same-net rails at a safe coordinate beside different-net traces", () => {
+  const rails = getVerticalRailTraces()
+  const foreignLowerTrace = createTrace(
+    "foreign-lower",
+    [
+      { x: -2.02, y: -2 },
+      { x: -2.02, y: -0.2 },
+    ],
+    [
+      { pinId: "X1.1", chipId: "X1", x: -2.02, y: -2 },
+      { pinId: "X2.1", chipId: "X2", x: -2.02, y: -0.2 },
+    ],
+    "foreign-lower-net",
+  )
+  const foreignUpperTrace = createTrace(
+    "foreign-upper",
+    [
+      { x: -3.02, y: 0.2 },
+      { x: -3.02, y: 2 },
+    ],
+    [
+      { pinId: "X3.1", chipId: "X3", x: -3.02, y: 0.2 },
+      { pinId: "X4.1", chipId: "X4", x: -3.02, y: 2 },
+    ],
+    "foreign-upper-net",
+  )
+  const traces = [...rails, foreignLowerTrace, foreignUpperTrace]
+
+  const result = align(traces, {
+    eligibleTraceIds: new Set(rails.map((trace) => trace.mspPairId)),
+  })
+
+  expect(result.alignedRailGroupCount).toBe(1)
+
+  const alignedUpper = result.traces.find(
+    (trace) => trace.mspPairId === "upper",
+  )!
+  const alignedLower = result.traces.find(
+    (trace) => trace.mspPairId === "lower",
+  )!
+  const upperRailX = alignedUpper.tracePath[1]!.x
+  const lowerRailX = alignedLower.tracePath[1]!.x
+
+  expect(upperRailX).toBe(lowerRailX)
+  expect(
+    Math.abs(upperRailX - foreignLowerTrace.tracePath[0]!.x),
+  ).toBeGreaterThan(SCHEMATIC_TRACE_STROKE_WIDTH)
+  expect(
+    Math.abs(upperRailX - foreignUpperTrace.tracePath[0]!.x),
+  ).toBeGreaterThan(SCHEMATIC_TRACE_STROKE_WIDTH)
+  expect(
+    Math.min(
+      Math.abs(upperRailX - foreignLowerTrace.tracePath[0]!.x),
+      Math.abs(upperRailX - foreignUpperTrace.tracePath[0]!.x),
+    ),
+  ).toBeCloseTo(SCHEMATIC_TRACE_MIN_VISUAL_CENTERLINE_CLEARANCE, 6)
+})