@tscircuit/schematic-trace-solver 0.0.114 → 0.0.116
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/dist/index.d.ts +22 -9
- package/dist/index.js +248 -3
- package/lib/solvers/SameNetJunctionAlignmentSolver/SameNetJunctionAlignmentSolver.ts +71 -0
- package/lib/solvers/SameNetJunctionAlignmentSolver/alignSameNetJunctions.ts +223 -0
- package/lib/solvers/SameNetJunctionAlignmentSolver/pathIntersectsAnyNetLabel.ts +22 -0
- package/lib/solvers/SchematicTraceLinesSolver/SchematicTraceSingleLineSolver2/SchematicTraceSingleLineSolver2.ts +9 -9
- package/lib/solvers/SchematicTraceLinesSolver/SchematicTraceSingleLineSolver2/rect.ts +25 -9
- package/lib/solvers/SchematicTracePipelineSolver/SchematicTracePipelineSolver.ts +17 -0
- package/package.json +2 -2
- package/site/bug-reports/bug-report-20260730T061837Z.page.tsx +4 -0
- package/tests/bug-reports/bug-report-20260721T221026Z/__snapshots__/bug-report-20260721T221026Z.snap.svg +1 -1
- package/tests/bug-reports/bug-report-20260728T144234Z/__snapshots__/bug-report-20260728T144234Z.snap.svg +1 -1
- package/tests/bug-reports/bug-report-20260728T144234Z/bug-report-20260728T144234Z.test.ts +6 -0
- package/tests/bug-reports/bug-report-20260730T061837Z/__snapshots__/bug-report-20260730T061837Z.snap.svg +123 -0
- package/tests/bug-reports/bug-report-20260730T061837Z/bug-report-20260730T061837Z.json +614 -0
- package/tests/bug-reports/bug-report-20260730T061837Z/bug-report-20260730T061837Z.test.ts +34 -0
- package/tests/repros/__snapshots__/board-15984-same-net-junction.snap.svg +110 -0
- package/tests/repros/__snapshots__/repro-type-c-16pin-self-connection.snap.svg +54 -0
- package/tests/repros/__snapshots__/repro-type-c-16pin-to-resistor.snap.svg +56 -0
- package/tests/repros/__snapshots__/repro48-555-timer-vcc-rail-label.snap.svg +87 -0
- package/tests/repros/assets/board-15984-schematic-trace-input.json +518 -0
- package/tests/repros/assets/repro48-555-timer-vcc-rail-label.input.json +276 -0
- package/tests/repros/board-15984-same-net-junction.test.ts +30 -0
- package/tests/repros/repro-type-c-16pin-self-connection.test.ts +97 -0
- package/tests/repros/repro-type-c-16pin-to-resistor.test.ts +120 -0
- package/tests/repros/repro48-555-timer-vcc-rail-label.test.ts +23 -0
- package/tests/solvers/SchematicTraceSingleLineSolver2/text-box-obstacle-gap.test.ts +43 -0
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"x": -1.1449999999999996,
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"y": -2.319999999999999,
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"_facingDirection": "y+"
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},
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{
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"pinId": "schematic_port_13",
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"x": -1.1449999999999996,
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"y": -3.0799999999999996,
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"_facingDirection": "y-"
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}
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"chipId": "schematic_component_4",
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"center": {
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"y": -0.4950000000000002
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"width": 0.9200000000000004,
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"height": 0.76,
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"pins": [
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"pinId": "schematic_port_14",
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"x": -2.19,
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"_facingDirection": "y+"
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],
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"directConnections": [
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"netId": "U1.CTRL to C2.pin1",
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"pinIds": [
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"schematic_port_4",
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"schematic_port_14"
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"pinIds": [
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"schematic_port_9",
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"netId": "U1.DISCH to R2.pin1",
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"schematic_port_6",
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"netConnections": [
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"netId": "GND",
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"netLabelWidth": 0.42,
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"netLabelHeight": 0.48,
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"pinIds": [
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"schematic_port_0",
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"schematic_port_13",
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"schematic_port_15",
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"schematic_port_18"
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"netId": "NODE",
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"netLabelWidth": 0.6,
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"pinIds": [
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"schematic_port_1",
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"schematic_port_5",
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"schematic_port_11",
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"schematic_port_12"
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]
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},
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{
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"netId": "OUT",
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"netLabelWidth": 0.48,
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"pinIds": [
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"schematic_port_2",
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"schematic_port_17"
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]
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},
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{
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"netId": "VCC",
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"netLabelWidth": 0.42,
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"netLabelHeight": 0.48,
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"pinIds": [
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"schematic_port_3",
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"schematic_port_7",
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"schematic_port_8",
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"schematic_port_16"
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]
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}
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],
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"textBoxes": [
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"chipId": "schematic_component_0",
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"center": {
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"x": -0.6,
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"y": 0.31999999999999995
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},
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"width": 0.36000000000000004,
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"height": 0.24999999999999994,
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"text": "U1"
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},
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{
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"chipId": "schematic_component_5",
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"center": {
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"x": 1,
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"y": -2.6799999999999997
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},
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"width": 0.3600000000000001,
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"height": 0.24999999999999956,
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"text": "J1"
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}
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],
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"availableNetLabelOrientations": {
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"VCC": [
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"y+"
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],
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"GND": [
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"y-"
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],
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"OUT": [
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"x-",
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"x+"
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],
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"NODE": [
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"x-",
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"x+"
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]
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},
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"maxMspPairDistance": 2.4,
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"_hideRatsNet": false
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}
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import { expect, test } from "bun:test"
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import { isPathCollidingWithObstacles } from "lib/solvers/SchematicTraceLinesSolver/SchematicTraceSingleLineSolver2/collisions"
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import { getObstacleRects } from "lib/solvers/SchematicTraceLinesSolver/SchematicTraceSingleLineSolver2/rect"
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import { SchematicTracePipelineSolver } from "lib/solvers/SchematicTracePipelineSolver/SchematicTracePipelineSolver"
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import type { InputProblem } from "lib/types/InputProblem"
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import inputProblemJson from "./assets/board-15984-schematic-trace-input.json"
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import "tests/fixtures/matcher"
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test("board 15984 extends the V3V3 rail through schematic component 8", () => {
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const inputProblem: InputProblem = JSON.parse(
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JSON.stringify(inputProblemJson),
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)
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const solver = new SchematicTracePipelineSolver(inputProblem)
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solver.solve()
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const component8Trace =
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solver.sameNetJunctionAlignmentSolver!.outputTraces.find(
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(trace) => trace.mspPairId === "schematic_port_34-schematic_port_33",
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)!
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expect(component8Trace.tracePath[1]!.y).toBeCloseTo(-3.105)
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expect(component8Trace.tracePath[2]!.y).toBeCloseTo(-3.105)
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const obstacles = getObstacleRects(inputProblem)
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const tracesCrossingComponents =
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solver.sameNetJunctionAlignmentSolver!.outputTraces.filter((trace) =>
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isPathCollidingWithObstacles(trace.tracePath, obstacles),
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)
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expect(tracesCrossingComponents).toHaveLength(0)
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expect(solver).toMatchSolverSnapshot(import.meta.path)
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})
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@@ -0,0 +1,97 @@
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1
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import { expect, test } from "bun:test"
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2
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import { SchematicTracePipelineSolver } from "lib/solvers/SchematicTracePipelineSolver/SchematicTracePipelineSolver"
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3
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import type { InputProblem } from "lib/types/InputProblem"
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4
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import "tests/fixtures/matcher"
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5
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6
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// Captured from @tscircuit/core for a TYPE_C_16PIN_2MD chip whose pin 4 is
|
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7
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// connected directly to pin 5 on the same schematic component.
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8
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const inputProblem: InputProblem = {
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9
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chips: [
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{
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chipId: "schematic_component_0",
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center: { x: 0, y: 0 },
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width: 2.6,
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height: 1,
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pins: [
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{
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pinId: "schematic_port_0",
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x: -1.3,
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y: 0.30000000000000004,
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},
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{
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pinId: "schematic_port_1",
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x: -1.3,
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y: 0.10000000000000003,
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},
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{
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pinId: "schematic_port_2",
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x: -1.3,
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y: -0.09999999999999998,
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+
},
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{
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pinId: "schematic_port_3",
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x: -1.3,
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y: -0.30000000000000004,
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+
},
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36
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+
{
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pinId: "schematic_port_4",
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x: 1.3,
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y: -0.30000000000000004,
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+
},
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41
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+
{
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42
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+
pinId: "schematic_port_5",
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43
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x: 1.3,
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44
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+
y: -0.10000000000000003,
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45
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+
},
|
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46
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+
{
|
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47
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+
pinId: "schematic_port_6",
|
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48
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+
x: 1.3,
|
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49
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+
y: 0.09999999999999998,
|
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50
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+
},
|
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51
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+
{
|
|
52
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+
pinId: "schematic_port_7",
|
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53
|
+
x: 1.3,
|
|
54
|
+
y: 0.30000000000000004,
|
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55
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+
},
|
|
56
|
+
],
|
|
57
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+
},
|
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58
|
+
],
|
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59
|
+
directConnections: [
|
|
60
|
+
{
|
|
61
|
+
netId: ".U1 > .pin4 to U1.pin5",
|
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62
|
+
netLabelWidth: 0.96,
|
|
63
|
+
pinIds: ["schematic_port_3", "schematic_port_4"],
|
|
64
|
+
},
|
|
65
|
+
],
|
|
66
|
+
netConnections: [],
|
|
67
|
+
textBoxes: [
|
|
68
|
+
{
|
|
69
|
+
chipId: "schematic_component_0",
|
|
70
|
+
center: { x: 0.06, y: -0.63 },
|
|
71
|
+
width: 1.92,
|
|
72
|
+
height: 0.17999999999999994,
|
|
73
|
+
text: "TYPE_C_16PIN_2MD",
|
|
74
|
+
},
|
|
75
|
+
{
|
|
76
|
+
chipId: "schematic_component_0",
|
|
77
|
+
center: { x: -0.78, y: 0.615 },
|
|
78
|
+
width: 0.3599999999999999,
|
|
79
|
+
height: 0.25,
|
|
80
|
+
text: "U1",
|
|
81
|
+
},
|
|
82
|
+
],
|
|
83
|
+
availableNetLabelOrientations: {},
|
|
84
|
+
maxMspPairDistance: 2.4,
|
|
85
|
+
_hideRatsNet: false,
|
|
86
|
+
}
|
|
87
|
+
|
|
88
|
+
test("TYPE_C_16PIN_2MD routes pin 4 to pin 5 on the same chip", () => {
|
|
89
|
+
const solver = new SchematicTracePipelineSolver(inputProblem)
|
|
90
|
+
|
|
91
|
+
solver.solve()
|
|
92
|
+
|
|
93
|
+
expect(solver.netLabelTraceCollisionSolver!.getOutput().traces).toHaveLength(
|
|
94
|
+
1,
|
|
95
|
+
)
|
|
96
|
+
expect(solver).toMatchSolverSnapshot(import.meta.path)
|
|
97
|
+
})
|
|
@@ -0,0 +1,120 @@
|
|
|
1
|
+
import { expect, test } from "bun:test"
|
|
2
|
+
import { SchematicTracePipelineSolver } from "lib/solvers/SchematicTracePipelineSolver/SchematicTracePipelineSolver"
|
|
3
|
+
import type { InputProblem } from "lib/types/InputProblem"
|
|
4
|
+
import "tests/fixtures/matcher"
|
|
5
|
+
|
|
6
|
+
// Captured from @tscircuit/core for a TYPE_C_16PIN_2MD chip whose pin 5 is
|
|
7
|
+
// connected directly to a resistor on the opposite side of the chip.
|
|
8
|
+
const inputProblem: InputProblem = {
|
|
9
|
+
chips: [
|
|
10
|
+
{
|
|
11
|
+
chipId: "schematic_component_0",
|
|
12
|
+
center: { x: 0, y: 0 },
|
|
13
|
+
width: 2.6,
|
|
14
|
+
height: 1,
|
|
15
|
+
pins: [
|
|
16
|
+
{
|
|
17
|
+
pinId: "schematic_port_0",
|
|
18
|
+
x: -1.3,
|
|
19
|
+
y: 0.30000000000000004,
|
|
20
|
+
},
|
|
21
|
+
{
|
|
22
|
+
pinId: "schematic_port_1",
|
|
23
|
+
x: -1.3,
|
|
24
|
+
y: 0.10000000000000003,
|
|
25
|
+
},
|
|
26
|
+
{
|
|
27
|
+
pinId: "schematic_port_2",
|
|
28
|
+
x: -1.3,
|
|
29
|
+
y: -0.09999999999999998,
|
|
30
|
+
},
|
|
31
|
+
{
|
|
32
|
+
pinId: "schematic_port_3",
|
|
33
|
+
x: -1.3,
|
|
34
|
+
y: -0.30000000000000004,
|
|
35
|
+
},
|
|
36
|
+
{
|
|
37
|
+
pinId: "schematic_port_4",
|
|
38
|
+
x: 1.3,
|
|
39
|
+
y: -0.30000000000000004,
|
|
40
|
+
},
|
|
41
|
+
{
|
|
42
|
+
pinId: "schematic_port_5",
|
|
43
|
+
x: 1.3,
|
|
44
|
+
y: -0.10000000000000003,
|
|
45
|
+
},
|
|
46
|
+
{
|
|
47
|
+
pinId: "schematic_port_6",
|
|
48
|
+
x: 1.3,
|
|
49
|
+
y: 0.09999999999999998,
|
|
50
|
+
},
|
|
51
|
+
{
|
|
52
|
+
pinId: "schematic_port_7",
|
|
53
|
+
x: 1.3,
|
|
54
|
+
y: 0.30000000000000004,
|
|
55
|
+
},
|
|
56
|
+
],
|
|
57
|
+
},
|
|
58
|
+
{
|
|
59
|
+
chipId: "schematic_component_1",
|
|
60
|
+
center: { x: -2, y: 0 },
|
|
61
|
+
width: 0.6000000000000001,
|
|
62
|
+
height: 0.6799999999999999,
|
|
63
|
+
pins: [
|
|
64
|
+
{
|
|
65
|
+
pinId: "schematic_port_8",
|
|
66
|
+
x: -2.3,
|
|
67
|
+
y: 0,
|
|
68
|
+
},
|
|
69
|
+
{
|
|
70
|
+
pinId: "schematic_port_9",
|
|
71
|
+
x: -1.7,
|
|
72
|
+
y: 0,
|
|
73
|
+
},
|
|
74
|
+
],
|
|
75
|
+
},
|
|
76
|
+
],
|
|
77
|
+
directConnections: [
|
|
78
|
+
{
|
|
79
|
+
netId: ".U1 > .pin5 to R1.pin1",
|
|
80
|
+
netLabelWidth: 0.96,
|
|
81
|
+
pinIds: ["schematic_port_4", "schematic_port_8"],
|
|
82
|
+
},
|
|
83
|
+
],
|
|
84
|
+
netConnections: [],
|
|
85
|
+
textBoxes: [
|
|
86
|
+
{
|
|
87
|
+
chipId: "schematic_component_0",
|
|
88
|
+
center: { x: 0.06, y: -0.63 },
|
|
89
|
+
width: 1.92,
|
|
90
|
+
height: 0.17999999999999994,
|
|
91
|
+
text: "TYPE_C_16PIN_2MD",
|
|
92
|
+
},
|
|
93
|
+
{
|
|
94
|
+
chipId: "schematic_component_0",
|
|
95
|
+
center: { x: -0.78, y: 0.615 },
|
|
96
|
+
width: 0.3599999999999999,
|
|
97
|
+
height: 0.25,
|
|
98
|
+
text: "U1",
|
|
99
|
+
},
|
|
100
|
+
],
|
|
101
|
+
availableNetLabelOrientations: {},
|
|
102
|
+
maxMspPairDistance: 2.4,
|
|
103
|
+
_hideRatsNet: false,
|
|
104
|
+
}
|
|
105
|
+
|
|
106
|
+
test("TYPE_C_16PIN_2MD routes pin 5 to R1 below the MPN text", () => {
|
|
107
|
+
const solver = new SchematicTracePipelineSolver(inputProblem)
|
|
108
|
+
|
|
109
|
+
solver.solve()
|
|
110
|
+
|
|
111
|
+
const traces = solver.netLabelTraceCollisionSolver!.getOutput().traces
|
|
112
|
+
const mpnTextBox = inputProblem.textBoxes![0]!
|
|
113
|
+
const mpnBottom = mpnTextBox.center.y - mpnTextBox.height / 2
|
|
114
|
+
|
|
115
|
+
expect(traces).toHaveLength(1)
|
|
116
|
+
expect(
|
|
117
|
+
Math.min(...traces[0]!.tracePath.map((point) => point.y)),
|
|
118
|
+
).toBeLessThan(mpnBottom)
|
|
119
|
+
expect(solver).toMatchSolverSnapshot(import.meta.path)
|
|
120
|
+
})
|
|
@@ -0,0 +1,23 @@
|
|
|
1
|
+
import { expect, test } from "bun:test"
|
|
2
|
+
import { SchematicTracePipelineSolver } from "lib/solvers/SchematicTracePipelineSolver/SchematicTracePipelineSolver"
|
|
3
|
+
import inputProblem from "./assets/repro48-555-timer-vcc-rail-label.input.json"
|
|
4
|
+
import "tests/fixtures/matcher"
|
|
5
|
+
|
|
6
|
+
// Captured from @tscircuit/core repro48. U1 pin 4 is a port-only member of the
|
|
7
|
+
// VCC net, but its required y+ rail placement falls back to a horizontal label.
|
|
8
|
+
test("core repro48 U1 pin4 VCC rail label falls back horizontally", () => {
|
|
9
|
+
const solver = new SchematicTracePipelineSolver(inputProblem as any)
|
|
10
|
+
|
|
11
|
+
solver.solve()
|
|
12
|
+
|
|
13
|
+
const u1Pin4VccLabel = solver.netLabelNetLabelCollisionSolver
|
|
14
|
+
?.getOutput()
|
|
15
|
+
.netLabelPlacements.find((placement) =>
|
|
16
|
+
placement.pinIds.includes("schematic_port_3"),
|
|
17
|
+
)
|
|
18
|
+
|
|
19
|
+
expect(inputProblem.availableNetLabelOrientations.VCC).toEqual(["y+"])
|
|
20
|
+
expect(u1Pin4VccLabel?.netId).toBe("VCC")
|
|
21
|
+
expect(u1Pin4VccLabel?.orientation).toBe("x-")
|
|
22
|
+
expect(solver).toMatchSolverSnapshot(import.meta.path)
|
|
23
|
+
})
|
|
@@ -0,0 +1,43 @@
|
|
|
1
|
+
import { expect, test } from "bun:test"
|
|
2
|
+
import { getObstacleRects } from "lib/solvers/SchematicTraceLinesSolver/SchematicTraceSingleLineSolver2/rect"
|
|
3
|
+
import type { InputProblem } from "lib/types/InputProblem"
|
|
4
|
+
|
|
5
|
+
test("closes a sub-minimum gap between a chip and its attached text", () => {
|
|
6
|
+
const inputProblem: InputProblem = {
|
|
7
|
+
chips: [
|
|
8
|
+
{
|
|
9
|
+
chipId: "U1",
|
|
10
|
+
center: { x: 0, y: 0 },
|
|
11
|
+
width: 2.6,
|
|
12
|
+
height: 1,
|
|
13
|
+
pins: [],
|
|
14
|
+
},
|
|
15
|
+
],
|
|
16
|
+
directConnections: [],
|
|
17
|
+
netConnections: [],
|
|
18
|
+
textBoxes: [
|
|
19
|
+
{
|
|
20
|
+
chipId: "U1",
|
|
21
|
+
center: { x: 0.06, y: -0.63 },
|
|
22
|
+
width: 1.92,
|
|
23
|
+
height: 0.18,
|
|
24
|
+
text: "TYPE_C_16PIN_2MD",
|
|
25
|
+
},
|
|
26
|
+
{
|
|
27
|
+
chipId: "U1",
|
|
28
|
+
center: { x: 0, y: -0.9 },
|
|
29
|
+
width: 1,
|
|
30
|
+
height: 0.2,
|
|
31
|
+
text: "clear gap",
|
|
32
|
+
},
|
|
33
|
+
],
|
|
34
|
+
availableNetLabelOrientations: {},
|
|
35
|
+
}
|
|
36
|
+
|
|
37
|
+
const textObstacles = getObstacleRects(inputProblem).filter(
|
|
38
|
+
(obstacle) => obstacle.kind === "text_box",
|
|
39
|
+
)
|
|
40
|
+
|
|
41
|
+
expect(textObstacles[0]!.maxY).toBe(-0.5)
|
|
42
|
+
expect(textObstacles[1]!.maxY).toBe(-0.8)
|
|
43
|
+
})
|