@tscircuit/matchpack 0.0.4 → 0.0.6

package/LICENSE

@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2025 tscircuit Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

package/README.md

@@ -12,9 +12,6 @@ This is roughly the hierarchy of solvers:
 LayoutPipelineSolver: Runs pipeline
 ↳ ChipPartitionsSolver: Creates partitions (small subset groups) surrounding complex chips
   ↳ SingleChipPartitionSolver: Creates a single partition for a single chip
-↳ PinRangeMatchSolver: Finds pin ranges on each chip in the partition, constructs a subset group with just that pin range, then matches a laid out design from the corpus
-↳ PinRangeLayoutSolver: Applies the matched layout to the pin ranges, moving passives that are connected to each pin range
-↳ PinRangeOverlapSolver: Finds overlaps between laid out boxes from each pin range and fixes them
 ↳ PartitionPackingSolver: Packs the laid out chip partitions into a single layout
 ```
 

package/dist/index.d.ts

@@ -65,8 +65,6 @@ type Net = {
 type InputProblem = {
     chipMap: Record<ChipId, Chip>;
     chipPinMap: Record<PinId, ChipPin>;
-    groupMap: Record<GroupId, Group>;
-    groupPinMap: Record<PinId, GroupPin>;
     netMap: Record<NetId, Net>;
     /** This is a two-way map */
     pinStrongConnMap: Record<`${PinId}-${PinId}`, boolean>;
@@ -92,7 +90,7 @@ declare class ChipPartitionsSolver extends BaseSolver {
      */
     private createPartitions;
     /**
-     * Finds the owner (chip or group) of a given pin
+     * Finds the owner chip of a given pin
      */
     private findPinOwner;
     /**
@@ -115,151 +113,65 @@ type OutputLayout = {
 };
 
 /**
- * Packs the laid out chip partitions into a single layout.
- * Combines all the individually processed partitions into the final schematic layout.
+ * Packs components within a single partition to create an optimal internal layout.
+ * Uses a packing algorithm to arrange chips and their connections within the partition.
  */
 
-type LaidOutPartition = InputProblem;
-interface PartitionPackingSolverInput {
-    resolvedLayout: OutputLayout;
-    laidOutPartitions: LaidOutPartition[];
+declare class SingleInnerPartitionPackingSolver extends BaseSolver {
     inputProblem: InputProblem;
-}
-declare class PartitionPackingSolver extends BaseSolver {
-    resolvedLayout: OutputLayout;
-    laidOutPartitions: LaidOutPartition[];
-    inputProblem: InputProblem;
-    finalLayout: OutputLayout | null;
+    layout: OutputLayout | null;
     phasedPackSolver: PhasedPackSolver | null;
-    constructor(input: PartitionPackingSolverInput);
-    _step(): void;
-    private organizeComponentsByPartition;
-    private createPackInput;
-    private applyPackingResult;
-    visualize(): GraphicsObject;
-    getConstructorParams(): PartitionPackingSolverInput;
-}
-
-/**
- * Sub-solver for processing pin ranges within a single partition
- */
-
-type PinRange = {
-    pinIds: PinId[];
-    side: Side;
-    chipId?: ChipId;
-    groupId?: GroupId;
-    connectedPins?: PinId[];
-    connectedChips?: ChipId[];
-};
-declare class PartitionPinRangeMatchSolver extends BaseSolver {
-    inputProblem: InputProblem;
-    pinRanges: PinRange[];
     constructor(inputProblem: InputProblem);
     _step(): void;
-    private createPinRanges;
-    private createPinRangesForChip;
-    private createPinRangesForGroup;
-    private createPinRangesForSide;
-    private sortPinsBySide;
-    private calculateDistance;
-    private findConnectedPassives;
+    private createPackInput;
+    private createLayoutFromPackingResult;
     visualize(): GraphicsObject;
-    getConstructorParams(): {
-        inputProblem: InputProblem;
-    };
+    getConstructorParams(): [InputProblem];
 }
 
 /**
- * Solves the layout for a single pin range and its connected passive components.
- * This solver takes a pin range and applies layout patterns to position the
- * connected components optimally around the pin range.
+ * Packs the internal layout of each partition using SingleInnerPartitionPackingSolver.
+ * This stage takes the partitions from ChipPartitionsSolver and creates optimized
+ * internal layouts for each partition before they are packed together.
  */
 
-declare class SinglePinRangeLayoutSolver extends BaseSolver {
-    pinRange: PinRange;
+type PackedPartition = {
     inputProblem: InputProblem;
-    layoutApplied: boolean;
-    layout: OutputLayout | null;
-    constructor(pinRange: PinRange, inputProblem: InputProblem);
-    _step(): void;
-    /**
-     * Build a connectivity map that normalizes network IDs by finding connected components.
-     * All pins in the same connected component get the same network ID.
-     */
-    protected buildNetworkConnectivityMap(relevantPins: Set<string>): Map<string, string>;
-    protected createPinRangeLayout(): OutputLayout;
-    visualize(): GraphicsObject;
-    getConstructorParams(): {
-        pinRange: PinRange;
-        inputProblem: InputProblem;
-    };
-}
-
-/**
- * Applies the matched layout to the pin ranges.
- * Moves passives that are connected to each pin range according to the matched design.
- */
-
-declare class PinRangeLayoutSolver extends BaseSolver {
-    pinRanges: PinRange[];
-    inputProblems: InputProblem[];
-    currentRangeIndex: number;
-    activeSolver: SinglePinRangeLayoutSolver | null;
-    completedSolvers: SinglePinRangeLayoutSolver[];
-    constructor(pinRanges: PinRange[], inputProblems: InputProblem[]);
-    _step(): void;
-    private findInputProblemForRange;
-    visualize(): GraphicsObject;
-    getConstructorParams(): {
-        pinRanges: PinRange[];
-        inputProblems: InputProblem[];
-    };
-}
-
-/**
- * Finds pin ranges on each chip in the partition and matches layouts from the corpus.
- * Creates subset groups with pin ranges and finds pre-laid-out designs that match.
- */
-
-declare class PinRangeMatchSolver extends BaseSolver {
+    layout: OutputLayout;
+};
+declare class PackInnerPartitionsSolver extends BaseSolver {
     partitions: InputProblem[];
+    packedPartitions: PackedPartition[];
+    completedSolvers: SingleInnerPartitionPackingSolver[];
+    activeSolver: SingleInnerPartitionPackingSolver | null;
     currentPartitionIndex: number;
-    activeSubSolver: PartitionPinRangeMatchSolver | null;
-    partitionResults: PinRange[][];
     constructor(partitions: InputProblem[]);
     _step(): void;
-    getAllPinRanges(): PinRange[];
     visualize(): GraphicsObject;
-    getConstructorParams(): {
-        partitions: InputProblem[];
-    };
+    getConstructorParams(): [InputProblem[]];
 }
 
 /**
- * Finds overlaps between laid out boxes from each pin range and fixes them.
- * Resolves spatial conflicts between different pin range layouts.
+ * Packs the laid out chip partitions into a single layout.
+ * Combines all the individually processed partitions into the final schematic layout.
  */
 
-declare class PinRangeOverlapSolver extends BaseSolver {
-    pinRangeLayoutSolver: PinRangeLayoutSolver | null;
-    inputProblems: InputProblem[];
-    resolvedLayout: OutputLayout | null;
-    constructor(pinRangeLayoutSolver: PinRangeLayoutSolver, inputProblems: InputProblem[]);
+interface PartitionPackingSolverInput {
+    packedPartitions: PackedPartition[];
+    inputProblem: InputProblem;
+}
+declare class PartitionPackingSolver extends BaseSolver {
+    packedPartitions: PackedPartition[];
+    inputProblem: InputProblem;
+    finalLayout: OutputLayout | null;
+    phasedPackSolver: PhasedPackSolver | null;
+    constructor(input: PartitionPackingSolverInput);
     _step(): void;
-    private groupPlacementsByPartition;
-    private findPartitionIndexForSolver;
-    private resolvePartitionOverlaps;
-    private positionPartitionsHorizontally;
-    private findOverlaps;
-    private getComponentBounds;
-    private boundsOverlap;
-    private resolveOverlaps;
+    private organizePackedPartitions;
+    private createPackInput;
+    private applyPackingResult;
     visualize(): GraphicsObject;
-    getConstructorParams(): {
-        pinRangeLayoutSolver: PinRangeLayoutSolver | null;
-        inputProblems: InputProblem[];
-    };
+    getConstructorParams(): PartitionPackingSolverInput;
 }
 
 /**
@@ -275,9 +187,7 @@ type PipelineStep<T extends new (...args: any[]) => BaseSolver> = {
 };
 declare class LayoutPipelineSolver extends BaseSolver {
     chipPartitionsSolver?: ChipPartitionsSolver;
-    pinRangeMatchSolver?: PinRangeMatchSolver;
-    pinRangeLayoutSolver?: PinRangeLayoutSolver;
-    pinRangeOverlapSolver?: PinRangeOverlapSolver;
+    packInnerPartitionsSolver?: PackInnerPartitionsSolver;
     partitionPackingSolver?: PartitionPackingSolver;
     startTimeOfPhase: Record<string, number>;
     endTimeOfPhase: Record<string, number>;
@@ -285,8 +195,8 @@ declare class LayoutPipelineSolver extends BaseSolver {
     firstIterationOfPhase: Record<string, number>;
     inputProblem: InputProblem;
     chipPartitions?: ChipPartitionsSolver["partitions"];
-    pinRanges?: ReturnType<PinRangeMatchSolver["getAllPinRanges"]>;
-    pipelineDef: (PipelineStep<typeof ChipPartitionsSolver> | PipelineStep<typeof PinRangeMatchSolver> | PipelineStep<typeof PinRangeLayoutSolver> | PipelineStep<typeof PinRangeOverlapSolver> | PipelineStep<typeof PartitionPackingSolver>)[];
+    packedPartitions?: PackedPartition[];
+    pipelineDef: (PipelineStep<typeof ChipPartitionsSolver> | PipelineStep<typeof PackInnerPartitionsSolver> | PipelineStep<typeof PartitionPackingSolver>)[];
     constructor(inputProblem: InputProblem);
     currentPipelineStepIndex: number;
     _step(): void;