@tscircuit/core 0.0.660 → 0.0.662

package/dist/index.d.ts

@@ -12,7 +12,7 @@ import { CircuitJsonUtilObjects } from '@tscircuit/circuit-json-util';
 import { ConnectivityMap } from 'circuit-json-to-connectivity-map';
 import { GraphicsObject } from 'graphics-debug';
 
-declare const orderedRenderPhases: readonly ["ReactSubtreesRender", "PcbFootprintStringRender", "InitializePortsFromChildren", "CreateNetsFromProps", "AssignFallbackProps", "CreateTracesFromProps", "CreateTracesFromNetLabels", "CreateTraceHintsFromProps", "SourceGroupRender", "AssignNameToUnnamedComponents", "SourceRender", "SourceParentAttachment", "PortMatching", "OptimizeSelectorCache", "SourceTraceRender", "SourceAddConnectivityMapKey", "SimulationRender", "SchematicComponentRender", "SchematicPortRender", "SchematicPrimitiveRender", "SchematicLayout", "SchematicTraceRender", "SchematicReplaceNetLabelsWithSymbols", "PcbComponentRender", "PcbPrimitiveRender", "PcbFootprintLayout", "PcbPortRender", "PcbPortAttachment", "PcbComponentSizeCalculation", "PcbLayout", "PcbBoardAutoSize", "PcbTraceHintRender", "PcbManualTraceRender", "PcbTraceRender", "PcbRouteNetIslands", "PcbDesignRuleChecks", "CadModelRender", "PartsEngineRender"];
+declare const orderedRenderPhases: readonly ["ReactSubtreesRender", "PcbFootprintStringRender", "InitializePortsFromChildren", "CreateNetsFromProps", "AssignFallbackProps", "CreateTracesFromProps", "CreateTracesFromNetLabels", "CreateTraceHintsFromProps", "SourceGroupRender", "AssignNameToUnnamedComponents", "SourceRender", "SourceParentAttachment", "PortMatching", "OptimizeSelectorCache", "SourceTraceRender", "SourceAddConnectivityMapKey", "SourceDesignRuleChecks", "SimulationRender", "SchematicComponentRender", "SchematicPortRender", "SchematicPrimitiveRender", "SchematicLayout", "SchematicTraceRender", "SchematicReplaceNetLabelsWithSymbols", "PcbComponentRender", "PcbPrimitiveRender", "PcbFootprintLayout", "PcbPortRender", "PcbPortAttachment", "PcbComponentSizeCalculation", "PcbLayout", "PcbBoardAutoSize", "PcbTraceHintRender", "PcbManualTraceRender", "PcbTraceRender", "PcbRouteNetIslands", "PcbDesignRuleChecks", "CadModelRender", "PartsEngineRender"];
 type RenderPhase = (typeof orderedRenderPhases)[number];
 type RenderPhaseFn<K extends RenderPhase = RenderPhase> = `doInitial${K}` | `update${K}` | `remove${K}`;
 type RenderPhaseStates = Record<RenderPhase, {
@@ -1104,6 +1104,7 @@ declare class NormalComponent<ZodProps extends z.ZodType = any, PortNames extend
     doInitialAssignFallbackProps(): void;
     doInitialCreateTracesFromProps(): void;
     _createTracesFromConnectionsProp(): void;
+    doInitialSourceDesignRuleChecks(): void;
     /**
      * Get the minimum flex container size for this component on PCB
      */

package/dist/index.js

@@ -99,6 +99,7 @@ var orderedRenderPhases = [
   "OptimizeSelectorCache",
   "SourceTraceRender",
   "SourceAddConnectivityMapKey",
+  "SourceDesignRuleChecks",
   "SimulationRender",
   "SchematicComponentRender",
   "SchematicPortRender",
@@ -6229,6 +6230,54 @@ var NormalComponent__repositionOnPcb = (component, position) => {
   );
 };
 
+// lib/components/base-components/NormalComponent/NormalComponent_doInitialSourceDesignRuleChecks.ts
+var NormalComponent_doInitialSourceDesignRuleChecks = (component) => {
+  const { db } = component.root;
+  if (!component.source_component_id) return;
+  const ports = component.selectAll("port");
+  const traces = db.source_trace.list();
+  const connected = /* @__PURE__ */ new Set();
+  for (const trace of traces) {
+    for (const id of trace.connected_source_port_ids) {
+      connected.add(id);
+    }
+  }
+  const internalGroups = component._getInternallyConnectedPins();
+  for (const group of internalGroups) {
+    if (group.some((p) => p.source_port_id && connected.has(p.source_port_id))) {
+      for (const p of group) {
+        if (p.source_port_id) connected.add(p.source_port_id);
+      }
+    }
+  }
+  for (const port of ports) {
+    if (!port.source_port_id) continue;
+    if (!shouldCheckPortForMissingTrace(component, port)) continue;
+    if (connected.has(port.source_port_id)) continue;
+    db.source_pin_missing_trace_warning.insert({
+      message: `Port ${port.getNameAndAliases()[0]} on ${component.props.name} is missing a trace`,
+      source_component_id: component.source_component_id,
+      source_port_id: port.source_port_id,
+      subcircuit_id: component.getSubcircuit().subcircuit_id ?? void 0,
+      warning_type: "source_pin_missing_trace_warning"
+    });
+  }
+};
+var shouldCheckPortForMissingTrace = (component, port) => {
+  if (component.config.componentName === "Chip") {
+    const pinAttributes = component.props.pinAttributes;
+    if (!pinAttributes) return false;
+    for (const alias of port.getNameAndAliases()) {
+      const attrs = pinAttributes[alias];
+      if (attrs?.requiresPower || attrs?.requiresGround || attrs?.requiresVoltage !== void 0) {
+        return true;
+      }
+    }
+    return false;
+  }
+  return true;
+};
+
 // lib/components/base-components/NormalComponent/NormalComponent.ts
 var debug3 = Debug4("tscircuit:core");
 var rotation3 = z8.object({
@@ -7101,6 +7150,9 @@ var NormalComponent = class extends PrimitiveComponent2 {
       }
     }
   }
+  doInitialSourceDesignRuleChecks() {
+    NormalComponent_doInitialSourceDesignRuleChecks(this);
+  }
   /**
    * Get the minimum flex container size for this component on PCB
    */
@@ -9282,7 +9334,8 @@ var Group_doInitialPcbLayoutPack = (group) => {
   const packInput = {
     ...convertPackOutputToPackInput(
       convertCircuitJsonToPackOutput(db.toArray(), {
-        source_group_id: group.source_group_id
+        source_group_id: group.source_group_id,
+        shouldAddInnerObstacles: true
       })
     ),
     // @ts-expect-error we're missing some pack order strategies
@@ -9290,6 +9343,13 @@ var Group_doInitialPcbLayoutPack = (group) => {
     placementStrategy: packPlacementStrategy ?? "minimum_sum_squared_distance_to_network",
     minGap: gapMm
   };
+  if (debug6.enabled) {
+    global.debugOutputs?.add(
+      `packInput-circuitjson-${group.name}`,
+      JSON.stringify(db.toArray())
+    );
+    global.debugOutputs?.add(`packInput-${group.name}`, packInput);
+  }
   const packOutput = pack(packInput);
   if (debug6.enabled) {
     const graphics = getGraphicsFromPackOutput(packOutput);
@@ -13767,7 +13827,7 @@ import { identity as identity5 } from "transformation-matrix";
 var package_default = {
   name: "@tscircuit/core",
   type: "module",
-  version: "0.0.659",
+  version: "0.0.661",
   types: "dist/index.d.ts",
   main: "dist/index.js",
   module: "dist/index.js",
@@ -13820,7 +13880,7 @@ var package_default = {
     "bun-match-svg": "0.0.12",
     "calculate-elbow": "^0.0.9",
     "chokidar-cli": "^3.0.0",
-    "circuit-json": "^0.0.233",
+    "circuit-json": "^0.0.235",
     "circuit-json-to-bpc": "^0.0.13",
     "circuit-json-to-connectivity-map": "^0.0.22",
     "circuit-json-to-simple-3d": "^0.0.6",
@@ -13861,7 +13921,7 @@ var package_default = {
   dependencies: {
     "@flatten-js/core": "^1.6.2",
     "@lume/kiwi": "^0.4.3",
-    "calculate-packing": "0.0.28",
+    "calculate-packing": "0.0.29",
     "css-select": "5.1.0",
     "format-si-unit": "^0.0.3",
     nanoid: "^5.0.7",

package/package.json

@@ -1,7 +1,7 @@
 {
   "name": "@tscircuit/core",
   "type": "module",
-  "version": "0.0.660",
+  "version": "0.0.662",
   "types": "dist/index.d.ts",
   "main": "dist/index.js",
   "module": "dist/index.js",
@@ -54,7 +54,7 @@
     "bun-match-svg": "0.0.12",
     "calculate-elbow": "^0.0.9",
     "chokidar-cli": "^3.0.0",
-    "circuit-json": "^0.0.233",
+    "circuit-json": "^0.0.235",
     "circuit-json-to-bpc": "^0.0.13",
     "circuit-json-to-connectivity-map": "^0.0.22",
     "circuit-json-to-simple-3d": "^0.0.6",
@@ -95,7 +95,7 @@
   "dependencies": {
     "@flatten-js/core": "^1.6.2",
     "@lume/kiwi": "^0.4.3",
-    "calculate-packing": "0.0.28",
+    "calculate-packing": "0.0.29",
     "css-select": "5.1.0",
     "format-si-unit": "^0.0.3",
     "nanoid": "^5.0.7",