@tscircuit/core 0.0.651 → 0.0.652

package/dist/index.d.ts

@@ -459,7 +459,7 @@ declare abstract class PrimitiveComponent<ZodProps extends ZodType = any> extend
     doInitialAssignNameToUnnamedComponents(): void;
     doInitialOptimizeSelectorCache(): void;
     _cachedSelectAllQueries: Map<string, PrimitiveComponent[]>;
-    selectAll(selectorRaw: string): PrimitiveComponent[];
+    selectAll<T extends PrimitiveComponent = PrimitiveComponent>(selectorRaw: string): T[];
     _cachedSelectOneQueries: Map<string, PrimitiveComponent | null>;
     selectOne<T = PrimitiveComponent>(selectorRaw: string, options?: {
         type?: string;
@@ -956,11 +956,18 @@ declare class Port extends PrimitiveComponent<typeof portProps> {
     doInitialSourceParentAttachment(): void;
     doInitialPcbPortRender(): void;
     doInitialSchematicPortRender(): void;
+    _getSubcircuitConnectivityKey(): string | undefined;
     _setPositionFromLayout(newCenter: {
         x: number;
         y: number;
     }): void;
     _hasMatchedPcbPrimitive(): boolean;
+    /**
+     * Return the text that should be used for the net label for this port if a
+     * trace can't be drawn. This net label text usually doesn't appear at this
+     * port, but appears at the port it connects to.
+     */
+    _getNetLabelText(): string | undefined;
 }
 
 interface INormalComponent {

package/dist/index.js

@@ -1033,12 +1033,14 @@ var PrimitiveComponent2 = class extends Renderable {
   _cachedSelectAllQueries = /* @__PURE__ */ new Map();
   selectAll(selectorRaw) {
     if (this._cachedSelectAllQueries.has(selectorRaw)) {
-      return this._cachedSelectAllQueries.get(
-        selectorRaw
-      );
+      return this._cachedSelectAllQueries.get(selectorRaw);
     }
     const selector = preprocessSelector(selectorRaw);
-    const result = selectAll(selector, this, cssSelectOptionsInsideSubcircuit);
+    const result = selectAll(
+      selector,
+      this,
+      cssSelectOptionsInsideSubcircuit
+    );
     if (result.length > 0) {
       this._cachedSelectAllQueries.set(selectorRaw, result);
       return result;
@@ -3305,6 +3307,9 @@ var Port = class extends PrimitiveComponent2 {
     });
     this.schematic_port_id = schematic_port.schematic_port_id;
   }
+  _getSubcircuitConnectivityKey() {
+    return this.root?.db.source_port.get(this.source_port_id)?.subcircuit_connectivity_map_key;
+  }
   _setPositionFromLayout(newCenter) {
     const { db } = this.root;
     if (!this.pcb_port_id) return;
@@ -3316,6 +3321,14 @@ var Port = class extends PrimitiveComponent2 {
   _hasMatchedPcbPrimitive() {
     return this.matchedComponents.some((c) => c.isPcbPrimitive);
   }
+  /**
+   * Return the text that should be used for the net label for this port if a
+   * trace can't be drawn. This net label text usually doesn't appear at this
+   * port, but appears at the port it connects to.
+   */
+  _getNetLabelText() {
+    return `${this.parent?.props.name}_${this.props.name}`;
+  }
 };
 
 // lib/utils/getPortFromHints.ts
@@ -10041,6 +10054,12 @@ var oppositeSide = (input) => {
   }
 };
 
+// lib/components/primitive-components/Group/Group_doInitialSchematicTraceRender/getNetNameFromPorts.ts
+var getNetNameFromPorts = (ports) => {
+  const netName = ports.map((p) => p._getNetLabelText()).join("/");
+  return netName;
+};
+
 // lib/components/primitive-components/Group/Group_doInitialSchematicTraceRender/applyNetLabelPlacements.ts
 function applyNetLabelPlacements(args) {
   const {
@@ -10050,7 +10069,10 @@ function applyNetLabelPlacements(args) {
     allScks,
     allSourceAndSchematicPortIdsInScope,
     schPortIdToSourcePortId,
-    userNetIdToSck
+    userNetIdToSck,
+    pinIdToSchematicPortId,
+    schematicPortIdsWithPreExistingNetLabels,
+    schematicPortIdsWithRoutedTraces
   } = args;
   const { db } = group.root;
   const netLabelPlacements = solver.netLabelPlacementSolver?.netLabelPlacements ?? [];
@@ -10062,18 +10084,38 @@ function applyNetLabelPlacements(args) {
     const orientation = placement.orientation;
     const anchor_side = oppositeSide(orientation);
     const sourceNet = placementSck ? sckToSourceNet.get(placementSck) : void 0;
-    if (!sourceNet) {
+    const schPortIds = placement.pinIds.map(
+      (pinId) => pinIdToSchematicPortId.get(pinId)
+    );
+    if (schPortIds.some(
+      (schPortId) => schematicPortIdsWithPreExistingNetLabels.has(schPortId)
+    )) {
       continue;
     }
-    const text = sourceNet.name;
-    const hasExistingLabelForNet = db.schematic_net_label.list().some((nl) => {
-      if (sourceNet?.source_net_id && nl.source_net_id) {
-        return nl.source_net_id === sourceNet.source_net_id;
-      }
-      return nl.text === text;
-    });
-    if (hasExistingLabelForNet) continue;
-    const center = placement.center ?? computeSchematicNetLabelCenter({
+    if (sourceNet) {
+      const text2 = sourceNet.name;
+      const center2 = computeSchematicNetLabelCenter({
+        anchor_position,
+        anchor_side,
+        text: text2
+      });
+      db.schematic_net_label.insert({
+        text: text2,
+        anchor_position,
+        center: center2,
+        anchor_side,
+        ...sourceNet?.source_net_id ? { source_net_id: sourceNet.source_net_id } : {}
+      });
+      return;
+    }
+    if (schPortIds.some(
+      (schPortId) => schematicPortIdsWithRoutedTraces.has(schPortId)
+    )) {
+      continue;
+    }
+    const ports = group.selectAll("port").filter((p) => p._getSubcircuitConnectivityKey() === placementSck);
+    const text = getNetNameFromPorts(ports);
+    const center = computeSchematicNetLabelCenter({
       anchor_position,
       anchor_side,
       text
@@ -10082,8 +10124,7 @@ function applyNetLabelPlacements(args) {
       text,
       anchor_position,
       center,
-      anchor_side,
-      ...sourceNet?.source_net_id ? { source_net_id: sourceNet.source_net_id } : {}
+      anchor_side
     });
   }
 }
@@ -10091,7 +10132,12 @@ function applyNetLabelPlacements(args) {
 // lib/components/primitive-components/Group/Group_doInitialSchematicTraceRender/insertNetLabelsForTracesExcludedFromRouting.ts
 import "@tscircuit/schematic-trace-solver";
 function insertNetLabelsForTracesExcludedFromRouting(args) {
-  const { group, displayLabelTraces } = args;
+  const {
+    group,
+    displayLabelTraces,
+    pinIdToSchematicPortId,
+    schematicPortIdsWithPreExistingNetLabels
+  } = args;
   const { db } = group.root;
   for (const trace of displayLabelTraces) {
     const label = trace._parsedProps?.schDisplayLabel;
@@ -10126,7 +10172,9 @@ var insertNetLabelsForPortsMissingTrace = ({
   allSourceAndSchematicPortIdsInScope,
   group,
   schPortIdToSourcePortId,
-  sckToSourceNet: connKeyToNet
+  sckToSourceNet: connKeyToNet,
+  pinIdToSchematicPortId,
+  schematicPortIdsWithPreExistingNetLabels
 }) => {
   const { db } = group.root;
   for (const schOrSrcPortId of Array.from(
@@ -10144,13 +10192,6 @@ var insertNetLabelsForPortsMissingTrace = ({
     if (!sourceNet) {
       continue;
     }
-    const hasLabelForNet = db.schematic_net_label.list().some((nl) => {
-      if (sourceNet.source_net_id && nl.source_net_id) {
-        return nl.source_net_id === sourceNet.source_net_id;
-      }
-      return nl.text === (sourceNet.name || key);
-    });
-    if (hasLabelForNet) continue;
     const existingAtPort = db.schematic_net_label.list().some((nl) => {
       const samePos = Math.abs(nl.anchor_position.x - sp.center.x) < 1e-6 && Math.abs(nl.anchor_position.y - sp.center.y) < 1e-6;
       if (!samePos) return false;
@@ -10177,6 +10218,38 @@ var insertNetLabelsForPortsMissingTrace = ({
   }
 };
 
+// lib/components/primitive-components/Group/Group_doInitialSchematicTraceRender/getSchematicPortIdsWithAssignedNetLabels.ts
+var getSchematicPortIdsWithAssignedNetLabels = (group) => {
+  const schematicPortIdsWithNetLabels = /* @__PURE__ */ new Set();
+  const netLabels = group.selectAll("netlabel");
+  for (const netLabel of netLabels) {
+    const netLabelPorts = netLabel._getConnectedPorts();
+    for (const port of netLabelPorts) {
+      if (!port.schematic_port_id) continue;
+      schematicPortIdsWithNetLabels.add(port.schematic_port_id);
+    }
+  }
+  return schematicPortIdsWithNetLabels;
+};
+
+// lib/components/primitive-components/Group/Group_doInitialSchematicTraceRender/getSchematicPortIdsWithRoutedTraces.ts
+var getSchematicPortIdsWithRoutedTraces = ({
+  solver,
+  pinIdToSchematicPortId
+}) => {
+  const solvedTraces = solver.schematicTraceLinesSolver.solvedTracePaths;
+  const schematicPortIdsWithRoutedTraces = /* @__PURE__ */ new Set();
+  for (const solvedTrace of solvedTraces) {
+    for (const pinId of solvedTrace.pinIds) {
+      const schPortId = pinIdToSchematicPortId.get(pinId);
+      if (schPortId) {
+        schematicPortIdsWithRoutedTraces.add(schPortId);
+      }
+    }
+  }
+  return schematicPortIdsWithRoutedTraces;
+};
+
 // lib/components/primitive-components/Group/Group_doInitialSchematicTraceRender/Group_doInitialSchematicTraceRender.ts
 var debug7 = Debug8("Group_doInitialSchematicTraceRender");
 var Group_doInitialSchematicTraceRender = (group) => {
@@ -10194,6 +10267,7 @@ var Group_doInitialSchematicTraceRender = (group) => {
     allScks,
     userNetIdToSck
   } = createSchematicTraceSolverInputProblem(group);
+  const schematicPortIdsWithPreExistingNetLabels = getSchematicPortIdsWithAssignedNetLabels(group);
   if (debug7.enabled) {
     globalThis.debugOutputs?.add(
       "group-trace-render-input-problem",
@@ -10202,6 +10276,10 @@ var Group_doInitialSchematicTraceRender = (group) => {
   }
   const solver = new SchematicTracePipelineSolver4(inputProblem);
   solver.solve();
+  const schematicPortIdsWithRoutedTraces = getSchematicPortIdsWithRoutedTraces({
+    solver,
+    pinIdToSchematicPortId
+  });
   applyTracesFromSolverOutput({
     group,
     solver,
@@ -10214,19 +10292,26 @@ var Group_doInitialSchematicTraceRender = (group) => {
     sckToSourceNet,
     allSourceAndSchematicPortIdsInScope,
     schPortIdToSourcePortId,
+    pinIdToSchematicPortId,
     allScks,
-    userNetIdToSck
+    userNetIdToSck,
+    schematicPortIdsWithPreExistingNetLabels,
+    schematicPortIdsWithRoutedTraces
   });
   insertNetLabelsForPortsMissingTrace({
     group,
     allSourceAndSchematicPortIdsInScope,
     schPortIdToSourcePortId,
-    sckToSourceNet
+    sckToSourceNet,
+    pinIdToSchematicPortId,
+    schematicPortIdsWithPreExistingNetLabels
   });
   insertNetLabelsForTracesExcludedFromRouting({
     group,
     solver,
-    displayLabelTraces
+    displayLabelTraces,
+    pinIdToSchematicPortId,
+    schematicPortIdsWithPreExistingNetLabels
   });
 };
 
@@ -13669,7 +13754,7 @@ import { identity as identity5 } from "transformation-matrix";
 var package_default = {
   name: "@tscircuit/core",
   type: "module",
-  version: "0.0.650",
+  version: "0.0.651",
   types: "dist/index.d.ts",
   main: "dist/index.js",
   module: "dist/index.js",
@@ -13711,7 +13796,7 @@ var package_default = {
     "@tscircuit/props": "^0.0.287",
     "@tscircuit/schematic-autolayout": "^0.0.6",
     "@tscircuit/schematic-match-adapt": "^0.0.16",
-    "@tscircuit/schematic-trace-solver": "^0.0.12",
+    "@tscircuit/schematic-trace-solver": "^0.0.17",
     "@tscircuit/simple-3d-svg": "^0.0.38",
     "@types/bun": "^1.2.16",
     "@types/debug": "^4.1.12",

package/package.json

@@ -1,7 +1,7 @@
 {
   "name": "@tscircuit/core",
   "type": "module",
-  "version": "0.0.651",
+  "version": "0.0.652",
   "types": "dist/index.d.ts",
   "main": "dist/index.js",
   "module": "dist/index.js",
@@ -43,7 +43,7 @@
     "@tscircuit/props": "^0.0.287",
     "@tscircuit/schematic-autolayout": "^0.0.6",
     "@tscircuit/schematic-match-adapt": "^0.0.16",
-    "@tscircuit/schematic-trace-solver": "^0.0.12",
+    "@tscircuit/schematic-trace-solver": "^0.0.17",
     "@tscircuit/simple-3d-svg": "^0.0.38",
     "@types/bun": "^1.2.16",
     "@types/debug": "^4.1.12",