@tscircuit/core 0.0.611 → 0.0.612

package/dist/index.d.ts

@@ -11,7 +11,7 @@ import { CircuitJsonUtilObjects } from '@tscircuit/circuit-json-util';
 import { ConnectivityMap } from 'circuit-json-to-connectivity-map';
 import { GraphicsObject } from 'graphics-debug';
 
-declare const orderedRenderPhases: readonly ["ReactSubtreesRender", "PcbFootprintStringRender", "InitializePortsFromChildren", "CreateNetsFromProps", "CreateTracesFromProps", "CreateTracesFromNetLabels", "CreateTraceHintsFromProps", "SourceGroupRender", "AssignNameToUnnamedComponents", "SourceRender", "SourceParentAttachment", "PortMatching", "OptimizeSelectorCache", "SourceTraceRender", "SourceAddConnectivityMapKey", "SchematicComponentRender", "SchematicPortRender", "SchematicPrimitiveRender", "SchematicLayout", "SchematicTraceRender", "SchematicReplaceNetLabelsWithSymbols", "PcbComponentRender", "PcbPrimitiveRender", "PcbFootprintLayout", "PcbPortRender", "PcbPortAttachment", "PcbComponentSizeCalculation", "PcbLayout", "PcbBoardAutoSize", "PcbTraceHintRender", "PcbTraceRender", "PcbRouteNetIslands", "PcbDesignRuleChecks", "CadModelRender", "PartsEngineRender"];
+declare const orderedRenderPhases: readonly ["ReactSubtreesRender", "PcbFootprintStringRender", "InitializePortsFromChildren", "CreateNetsFromProps", "CreateTracesFromProps", "CreateTracesFromNetLabels", "CreateTraceHintsFromProps", "SourceGroupRender", "AssignNameToUnnamedComponents", "SourceRender", "SourceParentAttachment", "PortMatching", "OptimizeSelectorCache", "SourceTraceRender", "SourceAddConnectivityMapKey", "SimulationRender", "SchematicComponentRender", "SchematicPortRender", "SchematicPrimitiveRender", "SchematicLayout", "SchematicTraceRender", "SchematicReplaceNetLabelsWithSymbols", "PcbComponentRender", "PcbPrimitiveRender", "PcbFootprintLayout", "PcbPortRender", "PcbPortAttachment", "PcbComponentSizeCalculation", "PcbLayout", "PcbBoardAutoSize", "PcbTraceHintRender", "PcbTraceRender", "PcbRouteNetIslands", "PcbDesignRuleChecks", "CadModelRender", "PartsEngineRender"];
 type RenderPhase = (typeof orderedRenderPhases)[number];
 type RenderPhaseFn<K extends RenderPhase = RenderPhase> = `doInitial${K}` | `update${K}` | `remove${K}`;
 type RenderPhaseStates = Record<RenderPhase, {
@@ -3467,6 +3467,7 @@ declare class Chip<PinLabels extends string = never> extends NormalComponent<typ
     doInitialSourceRender(): void;
     doInitialPcbComponentRender(): void;
     doInitialCreateTracesFromProps(): void;
+    doInitialSimulationRender(): void;
 }
 
 declare class Diode extends NormalComponent<typeof diodeProps, PolarizedPassivePorts> {

package/dist/index.js

@@ -98,6 +98,7 @@ var orderedRenderPhases = [
   "OptimizeSelectorCache",
   "SourceTraceRender",
   "SourceAddConnectivityMapKey",
+  "SimulationRender",
   "SchematicComponentRender",
   "SchematicPortRender",
   "SchematicPrimitiveRender",
@@ -9536,6 +9537,54 @@ var Chip = class extends NormalComponent {
     }
     this._createTracesFromConnectionsProp();
   }
+  doInitialSimulationRender() {
+    const { db } = this.root;
+    const { pinAttributes } = this.props;
+    if (!pinAttributes) return;
+    let powerPort = null;
+    let groundPort = null;
+    let voltage;
+    const ports = this.selectAll("port");
+    for (const port of ports) {
+      for (const alias of port.getNameAndAliases()) {
+        if (pinAttributes[alias]) {
+          const attributes = pinAttributes[alias];
+          if (attributes.providesPower) {
+            powerPort = port;
+            voltage = attributes.providesVoltage;
+          }
+          if (attributes.providesGround) {
+            groundPort = port;
+          }
+        }
+      }
+    }
+    if (!powerPort || !groundPort || voltage === void 0) {
+      return;
+    }
+    const powerSourcePort = db.source_port.get(powerPort.source_port_id);
+    if (!powerSourcePort?.subcircuit_connectivity_map_key) return;
+    const groundSourcePort = db.source_port.get(groundPort.source_port_id);
+    if (!groundSourcePort?.subcircuit_connectivity_map_key) return;
+    const powerNet = db.source_net.getWhere({
+      subcircuit_connectivity_map_key: powerSourcePort.subcircuit_connectivity_map_key
+    });
+    const groundNet = db.source_net.getWhere({
+      subcircuit_connectivity_map_key: groundSourcePort.subcircuit_connectivity_map_key
+    });
+    if (!powerNet || !groundNet) {
+      return;
+    }
+    ;
+    db.simulation_voltage_source.insert({
+      type: "simulation_voltage_source",
+      positive_source_port_id: powerPort.source_port_id,
+      positive_source_net_id: powerNet.source_net_id,
+      negative_source_port_id: groundPort.source_port_id,
+      negative_source_net_id: groundNet.source_net_id,
+      voltage
+    });
+  }
 };
 
 // lib/components/normal-components/Diode.ts
@@ -11546,7 +11595,7 @@ import { identity as identity5 } from "transformation-matrix";
 var package_default = {
   name: "@tscircuit/core",
   type: "module",
-  version: "0.0.610",
+  version: "0.0.611",
   types: "dist/index.d.ts",
   main: "dist/index.js",
   module: "dist/index.js",
@@ -11592,7 +11641,7 @@ var package_default = {
     "bun-match-svg": "0.0.12",
     "calculate-elbow": "^0.0.5",
     "chokidar-cli": "^3.0.0",
-    "circuit-json": "^0.0.224",
+    "circuit-json": "^0.0.226",
     "circuit-json-to-bpc": "^0.0.13",
     "circuit-json-to-connectivity-map": "^0.0.22",
     "circuit-json-to-simple-3d": "^0.0.6",

package/package.json

@@ -1,7 +1,7 @@
 {
   "name": "@tscircuit/core",
   "type": "module",
-  "version": "0.0.611",
+  "version": "0.0.612",
   "types": "dist/index.d.ts",
   "main": "dist/index.js",
   "module": "dist/index.js",
@@ -47,7 +47,7 @@
     "bun-match-svg": "0.0.12",
     "calculate-elbow": "^0.0.5",
     "chokidar-cli": "^3.0.0",
-    "circuit-json": "^0.0.224",
+    "circuit-json": "^0.0.226",
     "circuit-json-to-bpc": "^0.0.13",
     "circuit-json-to-connectivity-map": "^0.0.22",
     "circuit-json-to-simple-3d": "^0.0.6",