@tscircuit/core 0.0.1437 → 0.0.1438

package/dist/index.d.ts

@@ -2135,10 +2135,12 @@ declare class Port extends PrimitiveComponent<typeof portProps> {
      * Return traces that are explicitly connected to this port (not via a net)
      */
     _getDirectlyConnectedTraces(): Trace[];
+    doInitialCreateTracesFromProps(): void;
     doInitialSourceRender(): void;
     doInitialSourceParentAttachment(): void;
     doInitialPcbPortRender(): void;
     updatePcbPortRender(): void;
+    doInitialPcbPortAttachment(): void;
     /**
      * Get the best display label for this port based on port_hints
      * Filters out generic patterns and applies showPinAliases logic

package/dist/index.js

@@ -3664,25 +3664,29 @@ function getPcbSelectorErrorForTracePort(selector, port) {
     const siblingPorts = (parentNormalComponent?.children ?? []).filter(
       (child) => child.componentName === "Port" && child.isMatchingAnyOf([selectorToken])
     );
-    const internallyConnectedGroups = parentNormalComponent?._getInternallyConnectedPins?.() ?? [];
-    const matchingPortsAreInternallyConnected = internallyConnectedGroups.some(
-      (group) => siblingPorts.every((siblingPort) => group.includes(siblingPort))
-    );
-    if (siblingPorts.length > 1 && !matchingPortsAreInternallyConnected) {
-      const rawPinSelectors2 = Array.from(
-        new Set(
-          siblingPorts.flatMap(
-            (siblingPort) => siblingPort.getNameAndAliases().filter((alias) => /^pin\d+$/.test(alias)).map((alias) => `${parentName}.${alias}`)
-          )
+    if (siblingPorts.length > 1) {
+      const internallyConnectedGroups = parentNormalComponent?._getInternallyConnectedPins?.() ?? [];
+      const matchingPortsAreInternallyConnected = internallyConnectedGroups.some(
+        (group) => siblingPorts.every(
+          (siblingPort) => group.includes(siblingPort)
         )
       );
-      const suggestion = rawPinSelectors2.length > 0 ? ` Use a raw pin selector like ${rawPinSelectors2.map((s) => `"${s}"`).join(" or ")}.` : "";
-      const siblingPcbMatches = siblingPorts.flatMap(
-        (siblingPort) => siblingPort.matchedComponents.filter(
-          (component) => component.isPcbPrimitive
-        )
-      );
-      return `Trace selector "${selector}" resolved to "${parentName}.${port.props.name}", but alias "${selectorToken}" matches multiple PCB pads: ${siblingPcbMatches.map((component) => formatPcbPrimitiveForError(component)).join(", ")}.${suggestion}`;
+      if (!matchingPortsAreInternallyConnected) {
+        const rawPinSelectors2 = Array.from(
+          new Set(
+            siblingPorts.flatMap(
+              (siblingPort) => siblingPort.getNameAndAliases().filter((alias) => /^pin\d+$/.test(alias)).map((alias) => `${parentName}.${alias}`)
+            )
+          )
+        );
+        const suggestion = rawPinSelectors2.length > 0 ? ` Use a raw pin selector like ${rawPinSelectors2.map((s) => `"${s}"`).join(" or ")}.` : "";
+        const siblingPcbMatches = siblingPorts.flatMap(
+          (siblingPort) => siblingPort.matchedComponents.filter(
+            (component) => component.isPcbPrimitive
+          )
+        );
+        return `Trace selector "${selector}" resolved to "${parentName}.${port.props.name}", but alias "${selectorToken}" matches multiple PCB pads: ${siblingPcbMatches.map((component) => formatPcbPrimitiveForError(component)).join(", ")}.${suggestion}`;
+      }
     }
   }
   if (port.pcb_port_id) return null;
@@ -9558,6 +9562,62 @@ var applyPinAttributesToSourcePort = (sourcePortProps, attributes) => {
   }
 };
 
+// lib/components/primitive-components/Port/Port_doInitialCreateTracesFromProps.ts
+var getConnectionTargets = (target) => {
+  if (!target) return [];
+  return typeof target === "string" ? [target] : [...target];
+};
+function Port_doInitialCreateTracesFromProps(port) {
+  if (!port.isGroupPort()) return;
+  const connectsTo = port._parsedProps.connectsTo;
+  if (!connectsTo) return;
+  const parent = port.parent;
+  if (!parent) return;
+  const parentConnections = parent._parsedProps?.connections;
+  const connectionIsCreatedByParent = Object.keys(parentConnections ?? {}).some(
+    (pinName) => port.isMatchingAnyOf([pinName])
+  );
+  if (connectionIsCreatedByParent) return;
+  const parentName = parent.name;
+  const portName = port.name;
+  if (!parentName || !portName) return;
+  const from = `.${parentName} > .${portName}`;
+  for (const target of getConnectionTargets(connectsTo)) {
+    const traceAlreadyExists = parent.children.some((child) => {
+      if (!(child instanceof Trace3)) return false;
+      const traceProps2 = child._parsedProps;
+      if (!("from" in traceProps2) || !("to" in traceProps2)) return false;
+      return traceProps2.from === from && traceProps2.to === target || traceProps2.from === target && traceProps2.to === from;
+    });
+    if (traceAlreadyExists) continue;
+    parent.add(new Trace3({ from, to: target }));
+  }
+}
+
+// lib/components/primitive-components/Port/Port_tryRenderGroupPcbPort.ts
+function Port_tryRenderGroupPcbPort(port) {
+  if (port.root?.pcbDisabled) return false;
+  if (port.pcb_port_id) return true;
+  const { db } = port.root;
+  const connectedPort = port._getConnectedPortsFromConnectsTo()[0];
+  if (!connectedPort?.pcb_port_id) return false;
+  const connectedPcbPort = db.pcb_port.get(connectedPort.pcb_port_id);
+  if (!connectedPcbPort) return false;
+  const subcircuit = port.getSubcircuit();
+  const pcbPort = db.pcb_port.insert({
+    pcb_component_id: void 0,
+    layers: connectedPort.getAvailablePcbLayers(),
+    subcircuit_id: subcircuit?.subcircuit_id ?? void 0,
+    pcb_group_id: port.getGroup()?.pcb_group_id ?? void 0,
+    x: connectedPcbPort.x,
+    y: connectedPcbPort.y,
+    source_port_id: port.source_port_id,
+    is_board_pinout: false
+  });
+  port.pcb_port_id = pcbPort.pcb_port_id;
+  return true;
+}
+
 // lib/components/primitive-components/Port/Port.ts
 var Port = class extends PrimitiveComponent2 {
   source_port_id = null;
@@ -9827,6 +9887,9 @@ var Port = class extends PrimitiveComponent2 {
     const connectedTraces = allSubcircuitTraces.filter((trace) => !trace._couldNotFindPort).filter((trace) => trace._isExplicitlyConnectedToPort(this));
     return connectedTraces;
   }
+  doInitialCreateTracesFromProps() {
+    Port_doInitialCreateTracesFromProps(this);
+  }
   doInitialSourceRender() {
     const { db } = this.root;
     const { _parsedProps: props } = this;
@@ -9876,27 +9939,7 @@ var Port = class extends PrimitiveComponent2 {
     const { db } = this.root;
     const { matchedComponents } = this;
     if (this.isGroupPort()) {
-      const connectedPorts = this._getConnectedPortsFromConnectsTo();
-      if (connectedPorts.length === 0) {
-        return;
-      }
-      const connectedPort = connectedPorts[0];
-      if (!connectedPort.pcb_port_id) {
-        return;
-      }
-      const connectedPcbPort = db.pcb_port.get(connectedPort.pcb_port_id);
-      const matchCenter2 = { x: connectedPcbPort.x, y: connectedPcbPort.y };
-      const subcircuit = this.getSubcircuit();
-      const pcb_port = db.pcb_port.insert({
-        pcb_component_id: void 0,
-        layers: connectedPort.getAvailablePcbLayers(),
-        subcircuit_id: subcircuit?.subcircuit_id ?? void 0,
-        pcb_group_id: this.getGroup()?.pcb_group_id ?? void 0,
-        ...matchCenter2,
-        source_port_id: this.source_port_id,
-        is_board_pinout: false
-      });
-      this.pcb_port_id = pcb_port.pcb_port_id;
+      Port_tryRenderGroupPcbPort(this);
       return;
     }
     const parentNormalComponent = this.getParentNormalComponent();
@@ -9956,23 +9999,7 @@ var Port = class extends PrimitiveComponent2 {
     const { db } = this.root;
     if (this.pcb_port_id) return;
     if (this.isGroupPort()) {
-      const connectedPorts = this._getConnectedPortsFromConnectsTo();
-      if (connectedPorts.length === 0) return;
-      const connectedPort = connectedPorts[0];
-      if (!connectedPort.pcb_port_id) return;
-      const connectedPcbPort = db.pcb_port.get(connectedPort.pcb_port_id);
-      const matchCenter2 = { x: connectedPcbPort.x, y: connectedPcbPort.y };
-      const subcircuit2 = this.getSubcircuit();
-      const pcb_port2 = db.pcb_port.insert({
-        pcb_component_id: void 0,
-        layers: connectedPort.getAvailablePcbLayers(),
-        subcircuit_id: subcircuit2?.subcircuit_id ?? void 0,
-        pcb_group_id: this.getGroup()?.pcb_group_id ?? void 0,
-        ...matchCenter2,
-        source_port_id: this.source_port_id,
-        is_board_pinout: false
-      });
-      this.pcb_port_id = pcb_port2.pcb_port_id;
+      Port_tryRenderGroupPcbPort(this);
       return;
     }
     const pcbMatches = this.matchedComponents.filter((c) => c.isPcbPrimitive);
@@ -10006,6 +10033,10 @@ var Port = class extends PrimitiveComponent2 {
     });
     this.pcb_port_id = pcb_port.pcb_port_id;
   }
+  doInitialPcbPortAttachment() {
+    if (!this.isGroupPort() || this.pcb_port_id) return;
+    Port_tryRenderGroupPcbPort(this);
+  }
   /**
    * Get the best display label for this port based on port_hints
    * Filters out generic patterns and applies showPinAliases logic
@@ -21526,7 +21557,7 @@ var getSourcePortNetLabelText = (db, sourcePortId) => {
   if (!sourceComponent?.name || !sourcePort.name) return void 0;
   return `${sourceComponent.name}_${sourcePort.name}`;
 };
-var getDirectCrossSubcircuitConnectionLabelText = (db, sourcePortId) => {
+var getDirectCrossSubcircuitConnectedSourcePortId = (db, sourcePortId) => {
   const sourcePort = db.source_port.get(sourcePortId);
   if (!sourcePort) return void 0;
   for (const sourceTrace of db.source_trace.list()) {
@@ -21541,9 +21572,17 @@ var getDirectCrossSubcircuitConnectionLabelText = (db, sourcePortId) => {
     const otherSourcePort = db.source_port.get(otherSourcePortId);
     if (!otherSourcePort) continue;
     if (otherSourcePort.subcircuit_id === sourcePort.subcircuit_id) continue;
-    return getSourcePortNetLabelText(db, otherSourcePortId);
+    return otherSourcePortId;
   }
 };
+var getDirectCrossSubcircuitConnectionLabelText = (db, sourcePortId) => {
+  const otherSourcePortId = getDirectCrossSubcircuitConnectedSourcePortId(
+    db,
+    sourcePortId
+  );
+  if (!otherSourcePortId) return void 0;
+  return getSourcePortNetLabelText(db, otherSourcePortId);
+};
 var insertNetLabelsForPortsMissingTrace = ({
   allSourceAndSchematicPortIdsInScope,
   group,
@@ -21560,6 +21599,9 @@ var insertNetLabelsForPortsMissingTrace = ({
     const srcPortId = schPortIdToSourcePortId.get(schOrSrcPortId);
     if (!srcPortId) continue;
     const sourcePort = db.source_port.get(srcPortId);
+    if (group._parsedProps.showAsSchematicBox && sourcePort?.subcircuit_id === group.subcircuit_id && !sourcePort.source_component_id && getDirectCrossSubcircuitConnectedSourcePortId(db, srcPortId)) {
+      continue;
+    }
     const connKey = sourcePort?.subcircuit_connectivity_map_key;
     if (!connKey) continue;
     const sourceNet = connKeyToSourceNet.get(connKey);
@@ -22515,7 +22557,7 @@ function Group_getRoutingPhasePlans(group) {
 var package_default = {
   name: "@tscircuit/core",
   type: "module",
-  version: "0.0.1436",
+  version: "0.0.1437",
   types: "dist/index.d.ts",
   main: "dist/index.js",
   module: "dist/index.js",

package/package.json

@@ -1,7 +1,7 @@
 {
   "name": "@tscircuit/core",
   "type": "module",
-  "version": "0.0.1437",
+  "version": "0.0.1438",
   "types": "dist/index.d.ts",
   "main": "dist/index.js",
   "module": "dist/index.js",