@tscircuit/copper-pour-solver 0.0.9 → 0.0.11
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/dist/index.d.ts +8 -2
- package/dist/index.js +188 -23
- package/lib/circuit-json/convert-circuit-json-to-input-problem.ts +115 -15
- package/lib/solvers/CopperPourPipelineSolver.ts +1 -0
- package/lib/solvers/copper-pour/process-obstacles.ts +109 -7
- package/lib/types.ts +11 -1
- package/package.json +1 -1
- package/tests/__snapshots__/hole-and-cutouts.snap.svg +1 -0
- package/tests/__snapshots__/via.snap.svg +1 -0
- package/tests/assets/hole-and-cutouts.json +772 -0
- package/tests/assets/via.json +716 -0
- package/tests/hole-and-cutouts.test.ts +16 -0
- package/tests/utils/run-solver-and-render-to-svg.ts +1 -0
- package/tests/via.test.ts +15 -0
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[
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{
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"type": "source_project_metadata",
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"source_project_metadata_id": "source_project_metadata_0",
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"software_used_string": "@tscircuit/core@0.0.849"
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},
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{
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"type": "source_group",
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"source_group_id": "source_group_0",
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"is_subcircuit": true,
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"was_automatically_named": true,
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"subcircuit_id": "subcircuit_source_group_0"
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},
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{
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"type": "source_net",
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"source_net_id": "source_net_0",
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"name": "GND",
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"member_source_group_ids": [],
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"is_ground": true,
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"is_power": false,
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"is_positive_voltage_source": false,
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"subcircuit_id": "subcircuit_source_group_0",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit917_connectivity_net0"
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},
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{
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"type": "source_port",
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"source_port_id": "source_port_0",
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"name": "pin1",
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"pin_number": 1,
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"port_hints": ["pin1", "anode", "pos", "left", "1"],
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"source_component_id": "source_component_0",
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"subcircuit_id": "subcircuit_source_group_0",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit917_connectivity_net1"
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},
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{
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"type": "source_port",
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"source_port_id": "source_port_1",
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"name": "pin2",
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"pin_number": 2,
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"port_hints": ["pin2", "cathode", "neg", "right", "2"],
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"source_component_id": "source_component_0",
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"subcircuit_id": "subcircuit_source_group_0",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit917_connectivity_net0"
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},
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{
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"type": "source_component",
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"source_component_id": "source_component_0",
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"ftype": "simple_resistor",
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"name": "R1",
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"supplier_part_numbers": {
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"jlcpcb": ["C11702", "C25543", "C2906864"]
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},
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"resistance": 1000,
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"display_resistance": "1kΩ",
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"are_pins_interchangeable": true,
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"source_group_id": "source_group_0"
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},
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{
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"type": "source_port",
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"source_port_id": "source_port_2",
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"name": "pin1",
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"pin_number": 1,
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"port_hints": ["pin1", "pos", "anode", "1"],
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"source_component_id": "source_component_1",
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"subcircuit_id": "subcircuit_source_group_0",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit917_connectivity_net1"
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},
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{
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"type": "source_port",
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"source_port_id": "source_port_3",
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"name": "pin2",
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"pin_number": 2,
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"port_hints": ["pin2", "neg", "cathode", "2"],
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"source_component_id": "source_component_1",
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"subcircuit_id": "subcircuit_source_group_0"
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},
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{
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"type": "source_component",
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"source_component_id": "source_component_1",
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"ftype": "simple_capacitor",
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"name": "C1",
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"supplier_part_numbers": {
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"jlcpcb": ["C1523", "C696907", "C5137470"]
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},
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"capacitance": 1e-9,
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"display_capacitance": "1000pF",
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"are_pins_interchangeable": true,
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"source_group_id": "source_group_0"
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},
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{
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"type": "source_net",
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"source_net_id": "source_net_1",
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"name": "VCC",
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"member_source_group_ids": [],
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"is_ground": false,
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"is_power": true,
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"is_positive_voltage_source": true,
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"subcircuit_id": "subcircuit_source_group_0",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit917_connectivity_net1"
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},
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{
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"type": "source_board",
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"source_board_id": "source_board_0",
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"source_group_id": "source_group_0"
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},
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{
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"type": "source_trace",
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"source_trace_id": "source_trace_0",
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"connected_source_port_ids": ["source_port_1"],
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"connected_source_net_ids": ["source_net_0"],
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"subcircuit_id": "subcircuit_source_group_0",
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"display_name": ".R1 > .pin2 to net.GND",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit917_connectivity_net0"
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},
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{
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"type": "source_trace",
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"source_trace_id": "source_trace_1",
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"connected_source_port_ids": ["source_port_0"],
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"connected_source_net_ids": ["source_net_1"],
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"subcircuit_id": "subcircuit_source_group_0",
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"display_name": ".R1 > .pin1 to net.VCC",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit917_connectivity_net1"
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},
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{
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"type": "source_trace",
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"source_trace_id": "source_trace_2",
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"connected_source_port_ids": ["source_port_2"],
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"connected_source_net_ids": ["source_net_1"],
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"subcircuit_id": "subcircuit_source_group_0",
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"max_length": null,
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"display_name": ".C1 > .pin1 to net.VCC",
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"subcircuit_connectivity_map_key": "unnamedsubcircuit917_connectivity_net1"
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},
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{
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"type": "source_pin_missing_trace_warning",
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"source_pin_missing_trace_warning_id": "source_pin_missing_trace_warning_0",
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"message": "Port pin2 on C1 is missing a trace",
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"source_component_id": "source_component_1",
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"source_port_id": "source_port_3",
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"subcircuit_id": "subcircuit_source_group_0",
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"warning_type": "source_pin_missing_trace_warning"
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},
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{
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"type": "schematic_component",
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"schematic_component_id": "schematic_component_0",
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"center": {
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"x": 0,
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"y": 0
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},
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"size": {
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"width": 1.1,
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"height": 0.388910699999999
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},
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"source_component_id": "source_component_0",
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"is_box_with_pins": true,
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"symbol_name": "boxresistor_right",
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"symbol_display_value": "1kΩ",
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"schematic_group_id": "schematic_group_0"
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},
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{
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"type": "schematic_component",
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"schematic_component_id": "schematic_component_1",
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"center": {
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"x": 0,
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"y": -1.8144553499999994
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},
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"size": {
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"width": 1.1,
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"height": 0.84
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},
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"source_component_id": "source_component_1",
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"is_box_with_pins": true,
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"symbol_name": "capacitor_right",
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"symbol_display_value": "1000pF",
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"schematic_group_id": "schematic_group_0"
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},
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{
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"type": "schematic_group",
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"schematic_group_id": "schematic_group_0",
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"is_subcircuit": true,
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"subcircuit_id": "subcircuit_source_group_0",
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"name": "unnamed_board1",
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"center": {
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"x": 0,
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"y": 0
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},
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"width": 0,
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"height": 0,
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"schematic_component_ids": [],
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"source_group_id": "source_group_0"
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},
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{
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"type": "schematic_port",
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"schematic_port_id": "schematic_port_0",
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"schematic_component_id": "schematic_component_0",
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"center": {
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"x": -0.55,
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"y": 0
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},
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"source_port_id": "source_port_0",
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"facing_direction": "left",
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"distance_from_component_edge": 0.4,
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"pin_number": 1,
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"display_pin_label": "anode",
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"is_connected": true
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},
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{
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"type": "schematic_port",
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"schematic_port_id": "schematic_port_1",
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"schematic_component_id": "schematic_component_0",
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"center": {
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"x": 0.55,
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"y": 0
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},
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"source_port_id": "source_port_1",
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"facing_direction": "right",
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"distance_from_component_edge": 0.4,
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"pin_number": 2,
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"display_pin_label": "cathode",
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"is_connected": false
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},
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{
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"type": "schematic_port",
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"schematic_port_id": "schematic_port_2",
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"schematic_component_id": "schematic_component_1",
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"center": {
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"x": -0.55,
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"y": -1.8144553499999994
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},
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"source_port_id": "source_port_2",
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"facing_direction": "left",
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"distance_from_component_edge": 0.4,
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"pin_number": 1,
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"display_pin_label": "pos",
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"is_connected": true
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},
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{
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"type": "schematic_port",
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"schematic_port_id": "schematic_port_3",
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"schematic_component_id": "schematic_component_1",
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"center": {
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"x": 0.55,
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"y": -1.8144553499999994
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},
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"source_port_id": "source_port_3",
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"facing_direction": "right",
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"distance_from_component_edge": 0.4,
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"pin_number": 2,
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"display_pin_label": "neg",
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"is_connected": false
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},
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{
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"type": "schematic_trace",
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"schematic_trace_id": "schematic_trace_0",
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"source_trace_id": "solver_R1.1-C1.1",
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"edges": [
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{
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"from": {
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"x": -0.55,
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"y": 0
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"to": {
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"x": -0.75,
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"y": 0
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{
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"x": -0.75,
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"x": -0.75,
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"y": -1.8144553499999994
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}
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},
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{
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"x": -0.75,
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"y": -1.8144553499999994
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"to": {
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"x": -0.55,
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"y": -1.8144553499999994
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}
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}
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],
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"junctions": [],
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"subcircuit_connectivity_map_key": "unnamedsubcircuit917_connectivity_net1"
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},
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{
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"type": "schematic_net_label",
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"schematic_net_label_id": "schematic_net_label_0",
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"text": "VCC",
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"anchor_position": {
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"x": -0.75,
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"y": 0
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"center": {
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"x": -0.75,
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"y": 0.09
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},
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"anchor_side": "bottom",
|
|
304
|
+
"source_net_id": "source_net_1",
|
|
305
|
+
"symbol_name": "rail_up"
|
|
306
|
+
},
|
|
307
|
+
{
|
|
308
|
+
"type": "schematic_net_label",
|
|
309
|
+
"schematic_net_label_id": "schematic_net_label_1",
|
|
310
|
+
"text": "GND",
|
|
311
|
+
"anchor_position": {
|
|
312
|
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"x": 0.55,
|
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313
|
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314
|
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|
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315
|
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|
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316
|
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|
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317
|
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|
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318
|
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},
|
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319
|
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"anchor_side": "left",
|
|
320
|
+
"source_net_id": "source_net_0"
|
|
321
|
+
},
|
|
322
|
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{
|
|
323
|
+
"type": "pcb_component",
|
|
324
|
+
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|
|
325
|
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|
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326
|
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|
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327
|
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|
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328
|
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},
|
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329
|
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|
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330
|
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|
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331
|
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"layer": "top",
|
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332
|
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"rotation": 0,
|
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333
|
+
"source_component_id": "source_component_0",
|
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334
|
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"subcircuit_id": "subcircuit_source_group_0",
|
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335
|
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|
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336
|
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"obstructs_within_bounds": true
|
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337
|
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|
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338
|
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{
|
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339
|
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"type": "pcb_component",
|
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340
|
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|
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341
|
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|
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342
|
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"x": -2.5600000000000005,
|
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343
|
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344
|
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345
|
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|
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346
|
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|
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347
|
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"layer": "bottom",
|
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348
|
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|
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349
|
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|
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350
|
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"subcircuit_id": "subcircuit_source_group_0",
|
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351
|
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|
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352
|
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|
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353
|
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},
|
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354
|
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{
|
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355
|
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|
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356
|
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|
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357
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358
|
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359
|
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360
|
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361
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|
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362
|
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|
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363
|
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"width": 10,
|
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364
|
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"height": 10,
|
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365
|
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"material": "fr4"
|
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366
|
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},
|
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367
|
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{
|
|
368
|
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"type": "pcb_smtpad",
|
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369
|
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|
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370
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371
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|
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372
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373
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374
|
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375
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376
|
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377
|
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|
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378
|
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|
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379
|
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|
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380
|
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|
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381
|
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},
|
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382
|
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{
|
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383
|
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"type": "pcb_solder_paste",
|
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384
|
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|
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385
|
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"layer": "top",
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386
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387
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388
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389
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390
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391
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|
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392
|
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"pcb_smtpad_id": "pcb_smtpad_0",
|
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393
|
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"subcircuit_id": "subcircuit_source_group_0"
|
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394
|
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},
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395
|
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{
|
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396
|
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"type": "pcb_smtpad",
|
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397
|
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|
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398
|
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|
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399
|
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"pcb_port_id": "pcb_port_1",
|
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400
|
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401
|
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402
|
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403
|
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404
|
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"port_hints": ["2", "right"],
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405
|
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406
|
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"x": 0.51,
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407
|
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408
|
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"subcircuit_id": "subcircuit_source_group_0"
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409
|
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},
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410
|
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{
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411
|
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"type": "pcb_solder_paste",
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412
|
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413
|
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"layer": "top",
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414
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415
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"width": 0.378,
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416
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417
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"x": 0.51,
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418
|
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419
|
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"pcb_component_id": "pcb_component_0",
|
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420
|
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"pcb_smtpad_id": "pcb_smtpad_1",
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421
|
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"subcircuit_id": "subcircuit_source_group_0"
|
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422
|
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},
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423
|
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{
|
|
424
|
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"type": "pcb_silkscreen_path",
|
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425
|
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|
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|
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"pcb_component_id": "pcb_component_0",
|
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427
|
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428
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429
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{
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430
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431
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432
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433
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{
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434
|
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435
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436
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437
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{
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438
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439
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440
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441
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{
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442
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443
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444
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445
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446
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447
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|
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448
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},
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449
|
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{
|
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450
|
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|
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451
|
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|
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452
|
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453
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454
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455
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456
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},
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457
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458
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459
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460
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461
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462
|
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463
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464
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465
|
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{
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466
|
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467
|
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468
|
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469
|
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|
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470
|
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471
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472
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473
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474
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475
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476
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477
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478
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479
|
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480
|
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{
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481
|
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482
|
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483
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484
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485
|
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486
|
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487
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488
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489
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490
|
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491
|
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492
|
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493
|
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{
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494
|
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495
|
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496
|
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497
|
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|
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498
|
+
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499
|
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500
|
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501
|
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502
|
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503
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504
|
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505
|
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506
|
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507
|
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},
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508
|
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{
|
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509
|
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510
|
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|
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511
|
+
"layer": "bottom",
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512
|
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513
|
+
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514
|
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515
|
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516
|
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517
|
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|
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518
|
+
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|
|
519
|
+
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|
|
520
|
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},
|
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521
|
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{
|
|
522
|
+
"type": "pcb_silkscreen_path",
|
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523
|
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|
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524
|
+
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|
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525
|
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526
|
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527
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{
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528
|
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529
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530
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531
|
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{
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532
|
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533
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534
|
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535
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{
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536
|
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537
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538
|
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539
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{
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540
|
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541
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542
|
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543
|
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544
|
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545
|
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546
|
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547
|
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{
|
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548
|
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|
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549
|
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|
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550
|
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551
|
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552
|
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553
|
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554
|
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},
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555
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556
|
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|
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557
|
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558
|
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559
|
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|
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560
|
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|
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561
|
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|
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562
|
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},
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563
|
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{
|
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564
|
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|
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565
|
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|
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566
|
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567
|
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568
|
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|
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569
|
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|
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570
|
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|
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571
|
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},
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572
|
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{
|
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573
|
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|
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574
|
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|
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575
|
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576
|
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577
|
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578
|
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579
|
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580
|
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|
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581
|
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|
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582
|
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|
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583
|
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},
|
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584
|
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{
|
|
585
|
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"type": "pcb_cutout",
|
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586
|
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|
|
587
|
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|
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588
|
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589
|
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|
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590
|
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|
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591
|
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|
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592
|
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|
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593
|
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|
|
594
|
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},
|
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595
|
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{
|
|
596
|
+
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|
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597
|
+
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|
|
598
|
+
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|
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599
|
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600
|
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{
|
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601
|
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|
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602
|
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603
|
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|
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604
|
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{
|
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605
|
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|
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606
|
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607
|
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|
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608
|
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{
|
|
609
|
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|
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610
|
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611
|
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},
|
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612
|
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{
|
|
613
|
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|
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614
|
+
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|
|
615
|
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}
|
|
616
|
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|
|
617
|
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|
|
618
|
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},
|
|
619
|
+
{
|
|
620
|
+
"type": "pcb_port",
|
|
621
|
+
"pcb_port_id": "pcb_port_0",
|
|
622
|
+
"pcb_component_id": "pcb_component_0",
|
|
623
|
+
"layers": ["top"],
|
|
624
|
+
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|
|
625
|
+
"x": -0.51,
|
|
626
|
+
"y": 0,
|
|
627
|
+
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|
|
628
|
+
},
|
|
629
|
+
{
|
|
630
|
+
"type": "pcb_port",
|
|
631
|
+
"pcb_port_id": "pcb_port_1",
|
|
632
|
+
"pcb_component_id": "pcb_component_0",
|
|
633
|
+
"layers": ["top"],
|
|
634
|
+
"subcircuit_id": "subcircuit_source_group_0",
|
|
635
|
+
"x": 0.51,
|
|
636
|
+
"y": 0,
|
|
637
|
+
"source_port_id": "source_port_1"
|
|
638
|
+
},
|
|
639
|
+
{
|
|
640
|
+
"type": "pcb_port",
|
|
641
|
+
"pcb_port_id": "pcb_port_2",
|
|
642
|
+
"pcb_component_id": "pcb_component_1",
|
|
643
|
+
"layers": ["bottom"],
|
|
644
|
+
"subcircuit_id": "subcircuit_source_group_0",
|
|
645
|
+
"x": -2.0500000000000007,
|
|
646
|
+
"y": 0,
|
|
647
|
+
"source_port_id": "source_port_2"
|
|
648
|
+
},
|
|
649
|
+
{
|
|
650
|
+
"type": "pcb_port",
|
|
651
|
+
"pcb_port_id": "pcb_port_3",
|
|
652
|
+
"pcb_component_id": "pcb_component_1",
|
|
653
|
+
"layers": ["bottom"],
|
|
654
|
+
"subcircuit_id": "subcircuit_source_group_0",
|
|
655
|
+
"x": -3.0700000000000003,
|
|
656
|
+
"y": 0,
|
|
657
|
+
"source_port_id": "source_port_3"
|
|
658
|
+
},
|
|
659
|
+
{
|
|
660
|
+
"type": "cad_component",
|
|
661
|
+
"cad_component_id": "cad_component_0",
|
|
662
|
+
"position": {
|
|
663
|
+
"x": 0,
|
|
664
|
+
"y": 0,
|
|
665
|
+
"z": 0.7
|
|
666
|
+
},
|
|
667
|
+
"rotation": {
|
|
668
|
+
"x": 0,
|
|
669
|
+
"y": 0,
|
|
670
|
+
"z": 0
|
|
671
|
+
},
|
|
672
|
+
"pcb_component_id": "pcb_component_0",
|
|
673
|
+
"source_component_id": "source_component_0",
|
|
674
|
+
"footprinter_string": "0402"
|
|
675
|
+
},
|
|
676
|
+
{
|
|
677
|
+
"type": "cad_component",
|
|
678
|
+
"cad_component_id": "cad_component_1",
|
|
679
|
+
"position": {
|
|
680
|
+
"x": -2.5600000000000005,
|
|
681
|
+
"y": 0,
|
|
682
|
+
"z": -0.7
|
|
683
|
+
},
|
|
684
|
+
"rotation": {
|
|
685
|
+
"x": 0,
|
|
686
|
+
"y": 180,
|
|
687
|
+
"z": 0
|
|
688
|
+
},
|
|
689
|
+
"pcb_component_id": "pcb_component_1",
|
|
690
|
+
"source_component_id": "source_component_1",
|
|
691
|
+
"footprinter_string": "0402"
|
|
692
|
+
},
|
|
693
|
+
{
|
|
694
|
+
"type": "pcb_trace",
|
|
695
|
+
"pcb_trace_id": "source_net_1_0",
|
|
696
|
+
"connection_name": "source_net_1",
|
|
697
|
+
"route": [
|
|
698
|
+
{
|
|
699
|
+
"route_type": "wire",
|
|
700
|
+
"x": -2.0500000000000007,
|
|
701
|
+
"y": 0,
|
|
702
|
+
"width": 0.15,
|
|
703
|
+
"layer": "bottom",
|
|
704
|
+
"start_pcb_port_id": "pcb_port_2"
|
|
705
|
+
},
|
|
706
|
+
{
|
|
707
|
+
"route_type": "wire",
|
|
708
|
+
"x": -2.0500000000000007,
|
|
709
|
+
"y": -1.5790447323308274,
|
|
710
|
+
"width": 0.15,
|
|
711
|
+
"layer": "bottom"
|
|
712
|
+
},
|
|
713
|
+
{
|
|
714
|
+
"route_type": "wire",
|
|
715
|
+
"x": -1.929170149633294,
|
|
716
|
+
"y": -1.699874582697534,
|
|
717
|
+
"width": 0.15,
|
|
718
|
+
"layer": "bottom"
|
|
719
|
+
},
|
|
720
|
+
{
|
|
721
|
+
"route_type": "wire",
|
|
722
|
+
"x": -1.875,
|
|
723
|
+
"y": -1.875,
|
|
724
|
+
"width": 0.15,
|
|
725
|
+
"layer": "bottom"
|
|
726
|
+
},
|
|
727
|
+
{
|
|
728
|
+
"route_type": "via",
|
|
729
|
+
"x": -1.875,
|
|
730
|
+
"y": -1.875,
|
|
731
|
+
"from_layer": "bottom",
|
|
732
|
+
"to_layer": "top"
|
|
733
|
+
},
|
|
734
|
+
{
|
|
735
|
+
"route_type": "wire",
|
|
736
|
+
"x": -1.875,
|
|
737
|
+
"y": -1.875,
|
|
738
|
+
"width": 0.15,
|
|
739
|
+
"layer": "top"
|
|
740
|
+
},
|
|
741
|
+
{
|
|
742
|
+
"route_type": "wire",
|
|
743
|
+
"x": -1.875,
|
|
744
|
+
"y": -1.365,
|
|
745
|
+
"width": 0.15,
|
|
746
|
+
"layer": "top"
|
|
747
|
+
},
|
|
748
|
+
{
|
|
749
|
+
"route_type": "wire",
|
|
750
|
+
"x": -0.51,
|
|
751
|
+
"y": 0,
|
|
752
|
+
"width": 0.15,
|
|
753
|
+
"layer": "top",
|
|
754
|
+
"end_pcb_port_id": "pcb_port_0"
|
|
755
|
+
}
|
|
756
|
+
],
|
|
757
|
+
"subcircuit_id": "subcircuit_source_group_0",
|
|
758
|
+
"source_trace_id": "source_net_1"
|
|
759
|
+
},
|
|
760
|
+
{
|
|
761
|
+
"type": "pcb_via",
|
|
762
|
+
"pcb_via_id": "pcb_via_0",
|
|
763
|
+
"pcb_trace_id": "source_net_1_0",
|
|
764
|
+
"x": -1.875,
|
|
765
|
+
"y": -1.875,
|
|
766
|
+
"hole_diameter": 0.3,
|
|
767
|
+
"outer_diameter": 0.6,
|
|
768
|
+
"layers": ["bottom", "top"],
|
|
769
|
+
"from_layer": "bottom",
|
|
770
|
+
"to_layer": "top"
|
|
771
|
+
}
|
|
772
|
+
]
|