@tscircuit/copper-pour-solver 0.0.33 → 0.0.35

package/tests/__snapshots__/tsx-subcircuit-connectivity01.snap.svg

@@ -0,0 +1 @@
+<svg xmlns="http://www.w3.org/2000/svg" width="800" height="600" data-software-used-string="@tscircuit/core@0.0.988"><style></style><rect class="boundary" x="0" y="0" fill="#000" width="800" height="600" data-type="pcb_background" data-pcb-layer="global"/><rect class="pcb-boundary" fill="none" stroke="#fff" stroke-width="0.3" x="66.66666666666669" y="66.6666666666666" width="666.6666666666667" height="466.66666666666663" data-type="pcb_boundary" data-pcb-layer="global"/><path class="pcb-board" d="M 66.66666666666669 533.3333333333333 L 733.3333333333335 533.3333333333333 L 733.3333333333335 66.6666666666666 L 66.66666666666669 66.6666666666666 Z" fill="none" stroke="rgba(255, 255, 255, 0.5)" stroke-width="6.666666666666668" data-type="pcb_board" data-pcb-layer="board"/><path class="pcb-trace" stroke="rgb(200, 52, 52)" fill="none" d="M 200.00000000000006 299.99999999999994 L 332.00000000000006 299.99999999999994" stroke-width="10.666666666666668" stroke-linecap="round" stroke-linejoin="round" shape-rendering="crispEdges" data-type="pcb_trace" data-pcb-layer="top"/><path class="pcb-trace" stroke="rgb(200, 52, 52)" fill="none" d="M 332.00000000000006 299.99999999999994 L 332.00000000000006 183.33333333333326" stroke-width="10.666666666666668" stroke-linecap="round" stroke-linejoin="round" shape-rendering="crispEdges" data-type="pcb_trace" data-pcb-layer="top"/><path class="pcb-trace" stroke="rgb(200, 52, 52)" fill="none" d="M 332.00000000000006 183.33333333333326 L 618.0000000000001 183.33333333333326" stroke-width="10.666666666666668" stroke-linecap="round" stroke-linejoin="round" shape-rendering="crispEdges" data-type="pcb_trace" data-pcb-layer="top"/><path class="pcb-trace" stroke="rgb(200, 52, 52)" fill="none" d="M 618.0000000000001 183.33333333333326 L 618.0000000000001 299.99999999999994" stroke-width="10.666666666666668" stroke-linecap="round" stroke-linejoin="round" shape-rendering="crispEdges" data-type="pcb_trace" data-pcb-layer="top"/><path class="pcb-copper-pour pcb-copper-pour-brep" d="M 733.3333333333335 533.3333333333333 L 66.66666666666669 533.3333333333333 L 66.66666666666669 66.6666666666666 L 733.3333333333335 66.6666666666666 L 733.3333333333335 533.3333333333333 Z M 382.00000000000006 366.66666666666663 L 515.3333333333334 366.66666666666663 L 515.3333333333334 233.33333333333326 L 382.00000000000006 233.33333333333326 L 382.00000000000006 366.66666666666663 Z" fill="rgb(200, 52, 52)" fill-rule="evenodd" fill-opacity="0.5" data-type="pcb_copper_pour" data-pcb-layer="top"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,200.00000000000006,224.99999999999994)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_0" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">A</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="46.666666666666664" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,200.00000000000006,130.6666666666666)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_1" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">J1</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,448.66666666666674,224.99999999999994)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_2" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">B</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,618.0000000000001,224.99999999999994)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_3" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">C</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="46.666666666666664" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,533.3333333333334,130.6666666666666)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_4" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">J2</text><g data-type="pcb_plated_hole" data-pcb-layer="through"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="150.00000000000006" y="249.99999999999994" width="100" height="100" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="200.00000000000006" cy="299.99999999999994" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="398.66666666666674" y="249.99999999999994" width="100" height="100" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="448.66666666666674" cy="299.99999999999994" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="618.0000000000001" cy="299.99999999999994" r="50" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="618.0000000000001" cy="299.99999999999994" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><text x="400.00000000000006" y="9.999999999999943" fill="#ffffff" font-family="Arial, sans-serif" font-size="14.666666666666668" text-anchor="middle" dominant-baseline="central" class="pcb-note-text" data-type="pcb_note_text" data-pcb-note-text-id="pcb_note_text_0" data-pcb-layer="overlay">Expected: copper pour connects to A and C, but clears around B.</text><text x="400.00000000000006" y="29.999999999999943" fill="#ffffff" font-family="Arial, sans-serif" font-size="14.666666666666668" text-anchor="middle" dominant-baseline="central" class="pcb-note-text" data-type="pcb_note_text" data-pcb-note-text-id="pcb_note_text_1" data-pcb-layer="overlay">A is parent net.GND; C is child net.GND reached through the parent-to-child net.</text><text x="400.00000000000006" y="49.999999999999915" fill="#ffffff" font-family="Arial, sans-serif" font-size="14.666666666666668" text-anchor="middle" dominant-baseline="central" class="pcb-note-text" data-type="pcb_note_text" data-pcb-note-text-id="pcb_note_text_2" data-pcb-layer="overlay">B is a separate child pin, so the pour should clear around it.</text></svg>

package/tests/__snapshots__/tsx-subcircuit-connectivity02.snap.svg

@@ -0,0 +1 @@
+<svg xmlns="http://www.w3.org/2000/svg" width="800" height="600" data-software-used-string="@tscircuit/core@0.0.988"><style></style><rect class="boundary" x="0" y="0" fill="#000" width="800" height="600" data-type="pcb_background" data-pcb-layer="global"/><rect class="pcb-boundary" fill="none" stroke="#fff" stroke-width="0.3" x="66.66666666666669" y="66.6666666666666" width="666.6666666666667" height="466.66666666666663" data-type="pcb_boundary" data-pcb-layer="global"/><path class="pcb-board" d="M 66.66666666666669 533.3333333333333 L 733.3333333333335 533.3333333333333 L 733.3333333333335 66.6666666666666 L 66.66666666666669 66.6666666666666 Z" fill="none" stroke="rgba(255, 255, 255, 0.5)" stroke-width="6.666666666666668" data-type="pcb_board" data-pcb-layer="board"/><path class="pcb-copper-pour pcb-copper-pour-brep" d="M 733.3333333333335 533.3333333333333 L 66.66666666666669 533.3333333333333 L 66.66666666666669 66.6666666666666 L 733.3333333333335 66.6666666666666 L 733.3333333333335 533.3333333333333 Z M 382.00000000000006 366.66666666666663 L 515.3333333333334 366.66666666666663 L 515.3333333333334 233.33333333333326 L 382.00000000000006 233.33333333333326 L 382.00000000000006 366.66666666666663 Z M 618.0000000000001 366.66666666666663 L 631.0060000000001 365.3856666666666 L 643.5122000000001 361.5919999999999 L 655.038 355.43133333333327 L 665.1404666666667 347.1404666666666 L 673.4313333333334 337.03799999999995 L 679.5920000000001 325.51219999999995 L 683.3856666666668 313.006 L 684.6666666666667 299.99999999999994 L 683.3856666666668 286.9939999999999 L 679.5920000000001 274.48779999999994 L 673.4313333333334 262.96199999999993 L 665.1404666666667 252.85953333333327 L 655.038 244.56866666666662 L 643.5122000000001 238.40799999999993 L 631.0060000000001 234.61433333333326 L 618.0000000000001 233.33333333333326 L 604.9940000000001 234.61433333333326 L 592.4878000000001 238.40799999999993 L 580.9620000000001 244.56866666666662 L 570.8595333333334 252.85953333333327 L 562.5686666666668 262.96199999999993 L 556.4080000000001 274.48779999999994 L 552.6143333333334 286.9939999999999 L 551.3333333333334 299.99999999999994 L 552.6143333333334 313.006 L 556.4080000000001 325.51219999999995 L 562.5686666666668 337.03799999999995 L 570.8595333333334 347.1404666666666 L 580.9620000000001 355.43133333333327 L 592.4878000000001 361.5919999999999 L 604.9940000000001 365.3856666666666 L 618.0000000000001 366.66666666666663 Z" fill="rgb(200, 52, 52)" fill-rule="evenodd" fill-opacity="0.5" data-type="pcb_copper_pour" data-pcb-layer="top"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,200.00000000000006,224.99999999999994)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_0" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">A</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="46.666666666666664" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,200.00000000000006,130.6666666666666)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_1" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">J1</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,448.66666666666674,224.99999999999994)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_2" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">B</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="33.333333333333336" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,618.0000000000001,224.99999999999994)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_3" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">C</text><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="46.666666666666664" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,533.3333333333334,130.6666666666666)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_silkscreen_text_4" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">J2</text><g data-type="pcb_plated_hole" data-pcb-layer="through"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="150.00000000000006" y="249.99999999999994" width="100" height="100" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="200.00000000000006" cy="299.99999999999994" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through"><rect class="pcb-hole-outer-pad" fill="rgb(200, 52, 52)" x="398.66666666666674" y="249.99999999999994" width="100" height="100" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="448.66666666666674" cy="299.99999999999994" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><g data-type="pcb_plated_hole" data-pcb-layer="through"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="618.0000000000001" cy="299.99999999999994" r="50" data-type="pcb_plated_hole" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="618.0000000000001" cy="299.99999999999994" r="33.333333333333336" data-type="pcb_plated_hole_drill" data-pcb-layer="drill"/></g><text x="400.00000000000006" y="9.999999999999943" fill="#ffffff" font-family="Arial, sans-serif" font-size="14.666666666666668" text-anchor="middle" dominant-baseline="central" class="pcb-note-text" data-type="pcb_note_text" data-pcb-note-text-id="pcb_note_text_0" data-pcb-layer="overlay">Expected: copper pour connects to A, but clears around B and C.</text><text x="400.00000000000006" y="29.999999999999943" fill="#ffffff" font-family="Arial, sans-serif" font-size="14.666666666666668" text-anchor="middle" dominant-baseline="central" class="pcb-note-text" data-type="pcb_note_text" data-pcb-note-text-id="pcb_note_text_1" data-pcb-layer="overlay">A is parent net.GND; C is child net.GND with no parent-to-child net.</text><text x="400.00000000000006" y="49.999999999999915" fill="#ffffff" font-family="Arial, sans-serif" font-size="14.666666666666668" text-anchor="middle" dominant-baseline="central" class="pcb-note-text" data-type="pcb_note_text" data-pcb-note-text-id="pcb_note_text_2" data-pcb-layer="overlay">B is a separate child pin, so the pour should clear around it.</text></svg>

package/tests/assets/subcircuit-connectivity-scope.json

@@ -0,0 +1,126 @@
+[
+  {
+    "type": "pcb_board",
+    "pcb_board_id": "pcb_board_0",
+    "center": { "x": 0, "y": 0 },
+    "width": 8,
+    "height": 4,
+    "thickness": 1.4,
+    "num_layers": 2,
+    "material": "fr4"
+  },
+  {
+    "type": "source_group",
+    "source_group_id": "source_group_parent",
+    "is_subcircuit": true,
+    "subcircuit_id": "subcircuit_parent"
+  },
+  {
+    "type": "source_group",
+    "source_group_id": "source_group_child_a",
+    "is_subcircuit": true,
+    "subcircuit_id": "subcircuit_child_a",
+    "parent_subcircuit_id": "subcircuit_parent"
+  },
+  {
+    "type": "source_group",
+    "source_group_id": "source_group_child_b",
+    "is_subcircuit": true,
+    "subcircuit_id": "subcircuit_child_b",
+    "parent_subcircuit_id": "subcircuit_parent"
+  },
+  {
+    "type": "source_net",
+    "source_net_id": "source_net_child_a_gnd",
+    "name": "GND",
+    "member_source_group_ids": ["source_group_child_a"],
+    "subcircuit_id": "subcircuit_child_a",
+    "subcircuit_connectivity_map_key": "net0"
+  },
+  {
+    "type": "source_trace",
+    "source_trace_id": "source_trace_child_a_gnd",
+    "connected_source_net_ids": ["source_net_child_a_gnd"],
+    "connected_source_port_ids": ["source_port_child_a_gnd"],
+    "subcircuit_id": "subcircuit_child_a",
+    "subcircuit_connectivity_map_key": "net0"
+  },
+  {
+    "type": "source_port",
+    "source_port_id": "source_port_child_a_gnd",
+    "source_component_id": "source_component_child_a",
+    "name": "1",
+    "subcircuit_id": "subcircuit_child_a",
+    "subcircuit_connectivity_map_key": "net0"
+  },
+  {
+    "type": "pcb_port",
+    "pcb_port_id": "pcb_port_child_a_gnd",
+    "pcb_component_id": "pcb_component_child_a",
+    "source_port_id": "source_port_child_a_gnd",
+    "x": -2,
+    "y": 0,
+    "layers": ["top"],
+    "subcircuit_id": "subcircuit_child_a"
+  },
+  {
+    "type": "pcb_smtpad",
+    "pcb_smtpad_id": "pcb_smtpad_child_a_gnd",
+    "pcb_component_id": "pcb_component_child_a",
+    "pcb_port_id": "pcb_port_child_a_gnd",
+    "layer": "top",
+    "shape": "rect",
+    "x": -2,
+    "y": 0,
+    "width": 0.8,
+    "height": 0.8,
+    "subcircuit_id": "subcircuit_child_a"
+  },
+  {
+    "type": "source_net",
+    "source_net_id": "source_net_child_b_gnd",
+    "name": "GND",
+    "member_source_group_ids": ["source_group_child_b"],
+    "subcircuit_id": "subcircuit_child_b",
+    "subcircuit_connectivity_map_key": "net0"
+  },
+  {
+    "type": "source_trace",
+    "source_trace_id": "source_trace_child_b_gnd",
+    "connected_source_net_ids": ["source_net_child_b_gnd"],
+    "connected_source_port_ids": ["source_port_child_b_gnd"],
+    "subcircuit_id": "subcircuit_child_b",
+    "subcircuit_connectivity_map_key": "net0"
+  },
+  {
+    "type": "source_port",
+    "source_port_id": "source_port_child_b_gnd",
+    "source_component_id": "source_component_child_b",
+    "name": "1",
+    "subcircuit_id": "subcircuit_child_b",
+    "subcircuit_connectivity_map_key": "net0"
+  },
+  {
+    "type": "pcb_port",
+    "pcb_port_id": "pcb_port_child_b_gnd",
+    "pcb_component_id": "pcb_component_child_b",
+    "source_port_id": "source_port_child_b_gnd",
+    "x": 2,
+    "y": 0,
+    "layers": ["top"],
+    "subcircuit_id": "subcircuit_child_b"
+  },
+  {
+    "type": "pcb_smtpad",
+    "pcb_smtpad_id": "pcb_smtpad_child_b_gnd",
+    "pcb_component_id": "pcb_component_child_b",
+    "pcb_port_id": "pcb_port_child_b_gnd",
+    "layer": "top",
+    "shape": "rect",
+    "x": 2,
+    "y": 0,
+    "width": 0.8,
+    "height": 0.8,
+    "subcircuit_id": "subcircuit_child_b"
+  }
+]

package/tests/connectivity-key-api.test.ts

@@ -0,0 +1,146 @@
+import { expect, test } from "bun:test"
+import type { AnyCircuitElement } from "circuit-json"
+import { getFullConnectivityMapFromCircuitJson } from "circuit-json-to-connectivity-map"
+import { convertCircuitJsonToInputProblem } from "lib/circuit-json/convert-circuit-json-to-input-problem"
+import subcircuitConnectivityScopeCircuitJson from "./assets/subcircuit-connectivity-scope.json"
+
+const circuitJson = [
+  {
+    type: "pcb_board",
+    pcb_board_id: "pcb_board_0",
+    center: { x: 0, y: 0 },
+    width: 10,
+    height: 10,
+    thickness: 1.4,
+    num_layers: 2,
+    material: "fr4",
+  },
+  {
+    type: "source_net",
+    source_net_id: "source_net_gnd",
+    name: "GND",
+    subcircuit_connectivity_map_key: "stable_subcircuit_net_gnd",
+  },
+  {
+    type: "source_trace",
+    source_trace_id: "source_trace_gnd",
+    connected_source_net_ids: ["source_net_gnd"],
+    connected_source_port_ids: ["source_port_gnd"],
+    subcircuit_connectivity_map_key: "stable_subcircuit_net_gnd",
+  },
+  {
+    type: "source_port",
+    source_port_id: "source_port_gnd",
+    source_component_id: "source_component_r1",
+    name: "1",
+    subcircuit_connectivity_map_key: "stable_subcircuit_net_gnd",
+  },
+  {
+    type: "pcb_port",
+    pcb_port_id: "pcb_port_gnd",
+    pcb_component_id: "pcb_component_r1",
+    source_port_id: "source_port_gnd",
+    x: 0,
+    y: 0,
+    layers: ["top"],
+  },
+  {
+    type: "pcb_smtpad",
+    pcb_smtpad_id: "pcb_smtpad_gnd",
+    pcb_component_id: "pcb_component_r1",
+    pcb_port_id: "pcb_port_gnd",
+    layer: "top",
+    shape: "rect",
+    x: 0,
+    y: 0,
+    width: 1,
+    height: 1,
+    port_hints: ["1"],
+  },
+] as AnyCircuitElement[]
+
+test("circuit-json adapter resolves pours to subcircuit connectivity keys", () => {
+  const connectivityMap = getFullConnectivityMapFromCircuitJson(circuitJson)
+  const generatedConnectivityMapKey =
+    connectivityMap.getNetConnectedToId("source_net_gnd")
+
+  expect(generatedConnectivityMapKey).toBeDefined()
+  expect(generatedConnectivityMapKey).not.toBe("stable_subcircuit_net_gnd")
+
+  const inputProblem = convertCircuitJsonToInputProblem(circuitJson, {
+    layer: "top",
+    source_net_id: "source_net_gnd",
+    pad_margin: 0.2,
+    trace_margin: 0.2,
+  })
+
+  expect(inputProblem.regionsForPour[0]?.connectivityKey).toBe(
+    "stable_subcircuit_net_gnd",
+  )
+  expect(
+    inputProblem.pads.find((pad) => pad.padId === "pcb_smtpad_gnd"),
+  ).toMatchObject({
+    connectivityKey: "stable_subcircuit_net_gnd",
+  })
+})
+
+test("circuit-json adapter rejects generated connectivity map keys", () => {
+  const generatedConnectivityMapKey =
+    getFullConnectivityMapFromCircuitJson(circuitJson).getNetConnectedToId(
+      "source_net_gnd",
+    )
+
+  expect(() =>
+    convertCircuitJsonToInputProblem(circuitJson, {
+      layer: "top",
+      pour_connectivity_key: generatedConnectivityMapKey!,
+      pad_margin: 0.2,
+      trace_margin: 0.2,
+    }),
+  ).toThrow(/subcircuit_connectivity_map_key/)
+})
+
+test("subcircuit_id scopes repeated subcircuit connectivity keys", () => {
+  const inputProblem = convertCircuitJsonToInputProblem(
+    subcircuitConnectivityScopeCircuitJson as AnyCircuitElement[],
+    {
+      layer: "top",
+      subcircuit_id: "subcircuit_child_a",
+      subcircuit_connectivity_map_key: "net0",
+      pad_margin: 0.2,
+      trace_margin: 0.2,
+    },
+  )
+
+  const childAPad = inputProblem.pads.find(
+    (pad) => pad.padId === "pcb_smtpad_child_a_gnd",
+  )
+  const childBPad = inputProblem.pads.find(
+    (pad) => pad.padId === "pcb_smtpad_child_b_gnd",
+  )
+
+  expect(inputProblem.regionsForPour[0]?.connectivityKey).toBe(
+    "subcircuit:subcircuit_child_a:connectivity:net0",
+  )
+  expect(childAPad?.connectivityKey).toBe(
+    inputProblem.regionsForPour[0]?.connectivityKey,
+  )
+  expect(childBPad?.connectivityKey).not.toBe(
+    inputProblem.regionsForPour[0]?.connectivityKey,
+  )
+})
+
+test("parent subcircuit selection rejects ambiguous child connectivity keys", () => {
+  expect(() =>
+    convertCircuitJsonToInputProblem(
+      subcircuitConnectivityScopeCircuitJson as AnyCircuitElement[],
+      {
+        layer: "top",
+        subcircuit_id: "subcircuit_parent",
+        subcircuit_connectivity_map_key: "net0",
+        pad_margin: 0.2,
+        trace_margin: 0.2,
+      },
+    ),
+  ).toThrow(/multiple subcircuits/)
+})

package/tests/pill-pad-copper-pour.test.ts

@@ -71,7 +71,7 @@ const circuitJson: AnyCircuitElement[] = [
 const getInputProblem = () =>
   convertCircuitJsonToInputProblem(circuitJson, {
     layer: "top",
-    pour_connectivity_key: "net:GND",
+    subcircuit_connectivity_map_key: "net:GND",
     pad_margin: 0.15,
     trace_margin: 0.15,
   })