@tscircuit/copper-pour-solver 0.0.25 → 0.0.26
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/dist/index.js +169 -323
- package/lib/solvers/CopperPourPipelineSolver.ts +22 -35
- package/lib/solvers/copper-pour/circle-to-polygon.ts +15 -0
- package/lib/solvers/copper-pour/generate-brep.ts +52 -45
- package/lib/solvers/copper-pour/get-board-polygon.ts +19 -11
- package/lib/solvers/copper-pour/process-obstacles.ts +87 -65
- package/package.json +1 -4
- package/tests/__snapshots__/2-layers-bottom.snap.svg +1 -1
- package/tests/__snapshots__/2-layers-top.snap.svg +1 -1
- package/tests/__snapshots__/board-edge-margin-2.snap.svg +1 -1
- package/tests/__snapshots__/board-edge-margin.snap.svg +1 -1
- package/tests/__snapshots__/hole-and-cutouts.snap.svg +1 -1
- package/tests/__snapshots__/larger-trace-margin.snap.svg +1 -1
- package/tests/__snapshots__/multiple-pours.snap.svg +1 -1
- package/tests/__snapshots__/pad-margin.snap.svg +1 -1
- package/tests/__snapshots__/polygon-board-2.snap.svg +1 -1
- package/tests/__snapshots__/polygon-board.snap.svg +1 -1
- package/tests/__snapshots__/smaller-trace-margin.snap.svg +1 -1
- package/tests/__snapshots__/via.snap.svg +1 -1
- package/tests/stm32f746g-disco.test.ts +16 -16
- package/lib/solvers/copper-pour/manifold-geometry-adapter.ts +0 -306
- package/tests/__snapshots__/stm32f746g-disco.test.tsbottom.snap.svg +0 -1
- package/tests/__snapshots__/stm32f746g-disco.test.tstop.snap.svg +0 -1
- package/tests/manifold-copper-pour-geometry.test.ts +0 -194
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296.6829141908728 370.6530116872178 L 292.36074417450993 372.9632596924364 L 288.5723304703363 376.0723304703363 L 285.4632596924364 379.86074417450993 L 283.1530116872178 384.18291419087274 L 281.7303679899193 388.8727419495968 L 281.25 393.75 L 281.7303679899193 398.6272580504032 L 283.1530116872178 403.3170858091272 L 285.46325969243634 407.63925582549007 L 288.5723304703363 411.4276695296637 L 292.36074417450993 414.5367403075636 L 296.68291419087274 416.8469883127822 L 301.3727419495968 418.2696320100807 L 306.25 418.75 L 311.1272580504032 418.2696320100807 L 315.81708580912726 416.8469883127822 L 320.13925582549007 414.53674030756366 L 323.9276695296637 411.4276695296637 L 327.0367403075636 407.63925582549007 L 329.3469883127822 403.31708580912726 L 330.7696320100807 398.6272580504032 L 331.25 393.75 L 330.7696320100807 388.8727419495968 L 329.3469883127822 384.1829141908728 L 327.0367403075636 379.86074417450993 L 323.9276695296637 376.0723304703363 L 320.13925582549007 372.9632596924364 L 316.0805385563561 370.7938301144085 Z" fill="rgb(200, 52, 52)" fill-rule="evenodd" fill-opacity="0.5" data-type="pcb_copper_pour" data-pcb-layer="top"/><path class="pcb-silkscreen pcb-silkscreen-top" d="M 425.5 264 L 351 264 L 351 336 L 425.5 336" fill="none" stroke="#f2eda1" stroke-width="5" stroke-linecap="round" stroke-linejoin="round" data-pcb-component-id="pcb_component_0" data-pcb-silkscreen-path-id="pcb_silkscreen_path_0" data-type="pcb_silkscreen_path" data-pcb-layer="top"/><text x="0" y="0" dx="0" dy="0" fill="#f2eda1" font-family="Arial, sans-serif" font-size="20" text-anchor="middle" dominant-baseline="central" transform="matrix(1,0,0,1,400,239)" class="pcb-silkscreen-text pcb-silkscreen-top" data-pcb-silkscreen-text-id="pcb_component_0" stroke="none" data-type="pcb_silkscreen_text" data-pcb-layer="top">R1</text><g data-type="pcb_via" data-pcb-layer="through"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="306.25" cy="393.75" r="15" data-type="pcb_via" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="306.25" cy="393.75" r="7.5" data-type="pcb_via" data-pcb-layer="drill"/></g></svg>
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@@ -4,23 +4,23 @@ import circuitJson from "./assets/tsci_AnasSarkiz.STM32F746G-DISCO.circuit.json"
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import { runSolverAndRenderToSvg } from "./utils/run-solver-and-render-to-svg"
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test("stm32f746g-disco top layer full board repro", () => {
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expect(() =>
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runSolverAndRenderToSvg(circuitJson as AnyCircuitElement[], {
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layer: "top",
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net_name: "GND",
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pad_margin: 0.2,
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trace_margin: 0.2,
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}),
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).toThrowErrorMatchingInlineSnapshot(`"Cannot complete boolean operation"`)
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})
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test("stm32f746g-disco bottom layer full board repro", () => {
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expect(() =>
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runSolverAndRenderToSvg(circuitJson as AnyCircuitElement[], {
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layer: "bottom",
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net_name: "GND",
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pad_margin: 0.2,
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trace_margin: 0.2,
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}),
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).toThrowErrorMatchingInlineSnapshot(`"Cannot complete boolean operation"`)
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})
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