@tscircuit/checks 0.0.2 → 0.0.4

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
package/dist/index.cjs ADDED
@@ -0,0 +1,291 @@
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+ "use strict";
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+ var __defProp = Object.defineProperty;
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+ var __getOwnPropDesc = Object.getOwnPropertyDescriptor;
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+ var __getOwnPropNames = Object.getOwnPropertyNames;
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+ var __hasOwnProp = Object.prototype.hasOwnProperty;
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+ var __export = (target, all) => {
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+ for (var name in all)
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+ __defProp(target, name, { get: all[name], enumerable: true });
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+ };
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+ var __copyProps = (to, from, except, desc) => {
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+ if (from && typeof from === "object" || typeof from === "function") {
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+ for (let key of __getOwnPropNames(from))
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+ if (!__hasOwnProp.call(to, key) && key !== except)
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+ __defProp(to, key, { get: () => from[key], enumerable: !(desc = __getOwnPropDesc(from, key)) || desc.enumerable });
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+ }
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+ return to;
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+ };
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+ var __toCommonJS = (mod) => __copyProps(__defProp({}, "__esModule", { value: true }), mod);
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+
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+ // index.ts
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+ var checks_exports = {};
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+ __export(checks_exports, {
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+ checkEachPcbPortConnected: () => checkEachPcbPortConnected,
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+ checkEachPcbTraceNonOverlapping: () => checkEachPcbTraceNonOverlapping
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+ });
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+ module.exports = __toCommonJS(checks_exports);
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+
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+ // lib/check-each-pcb-port-connected.ts
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+ function distance(x1, y1, x2, y2) {
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+ return Math.sqrt(Math.pow(x2 - x1, 2) + Math.pow(y2 - y1, 2));
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+ }
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+ function checkEachPcbPortConnected(soup) {
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+ const pcbPorts = soup.filter((item) => item.type === "pcb_port");
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+ const pcbTraces = soup.filter((item) => item.type === "pcb_trace");
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+ const sourceTraces = soup.filter(
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+ (item) => item.type === "source_trace"
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+ );
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+ const errors = [];
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+ pcbTraces.forEach((trace) => {
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+ trace.route.forEach((segment, index) => {
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+ if (segment.route_type === "wire") {
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+ if (!segment.start_pcb_port_id && index === 0) {
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+ const startPort = pcbPorts.find(
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+ (port) => distance(port.x, port.y, segment.x, segment.y) < 1e-3
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+ );
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+ if (startPort) {
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+ segment.start_pcb_port_id = startPort.pcb_port_id;
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+ }
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+ }
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+ if (!segment.end_pcb_port_id && index === trace.route.length - 1) {
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+ const endPort = pcbPorts.find(
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+ (port) => distance(port.x, port.y, segment.x, segment.y) < 1e-3
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+ );
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+ if (endPort) {
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+ segment.end_pcb_port_id = endPort.pcb_port_id;
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+ }
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+ }
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+ }
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+ });
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+ });
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+ for (const port of pcbPorts) {
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+ const connectedTraces = pcbTraces.filter(
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+ (trace) => trace.route.some(
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+ (segment) => segment.route_type === "wire" && (segment.start_pcb_port_id === port.pcb_port_id || segment.end_pcb_port_id === port.pcb_port_id)
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+ )
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+ );
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+ if (connectedTraces.length === 0) {
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+ const sourceTrace = sourceTraces.find(
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+ (trace) => trace.connected_source_port_ids.includes(port.source_port_id)
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+ );
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+ errors.push({
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+ type: "pcb_error",
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+ message: `pcb_trace_error: PCB port ${port.pcb_port_id} is not connected by a PCB trace`,
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+ source_trace_id: sourceTrace ? sourceTrace.source_trace_id : "",
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+ error_type: "pcb_trace_error",
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+ pcb_trace_id: "",
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+ pcb_error_id: "",
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+ // Add appropriate ID generation if necessary
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+ pcb_component_ids: [],
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+ pcb_port_ids: [port.pcb_port_id]
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+ });
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+ }
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+ }
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+ return errors;
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+ }
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+
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+ // lib/net-manager.ts
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+ var NetManager = class {
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+ networks = /* @__PURE__ */ new Set();
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+ setConnected(nodes) {
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+ if (nodes.length < 2) return;
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+ let targetNetwork = null;
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+ for (const network of this.networks) {
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+ for (const node of nodes) {
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+ if (network.has(node)) {
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+ if (targetNetwork === null) {
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+ targetNetwork = network;
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+ } else if (targetNetwork !== network) {
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+ for (const mergeNode of network) {
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+ targetNetwork.add(mergeNode);
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+ }
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+ this.networks.delete(network);
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+ }
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+ break;
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+ }
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+ }
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+ if (targetNetwork !== null && targetNetwork !== network) break;
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+ }
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+ if (targetNetwork === null) {
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+ targetNetwork = new Set(nodes);
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+ this.networks.add(targetNetwork);
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+ } else {
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+ for (const node of nodes) {
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+ targetNetwork.add(node);
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+ }
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+ }
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+ }
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+ isConnected(nodes) {
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+ if (nodes.length < 2) return true;
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+ for (const network of this.networks) {
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+ if (nodes.every((node) => network.has(node))) {
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+ return true;
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+ }
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+ }
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+ return false;
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+ }
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+ };
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+
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+ // lib/check-each-pcb-trace-non-overlapping.ts
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+ function lineIntersects(x1, y1, x2, y2, x3, y3, x4, y4) {
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+ const denom = (y4 - y3) * (x2 - x1) - (x4 - x3) * (y2 - y1);
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+ if (denom === 0) return false;
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+ const ua = ((x4 - x3) * (y1 - y3) - (y4 - y3) * (x1 - x3)) / denom;
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+ const ub = ((x2 - x1) * (y1 - y3) - (y2 - y1) * (x1 - x3)) / denom;
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+ return ua >= 0 && ua <= 1 && ub >= 0 && ub <= 1;
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+ }
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+ function tracesOverlap(trace1, trace2) {
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+ for (let i = 0; i < trace1.route.length - 1; i++) {
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+ for (let j = 0; j < trace2.route.length - 1; j++) {
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+ const seg1 = trace1.route[i];
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+ const seg2 = trace1.route[i + 1];
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+ const seg3 = trace2.route[j];
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+ const seg4 = trace2.route[j + 1];
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+ if (seg1.route_type === "wire" && seg2.route_type === "wire" && seg3.route_type === "wire" && seg4.route_type === "wire" && seg1.layer === seg3.layer && lineIntersects(
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+ seg1.x,
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+ seg1.y,
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+ seg2.x,
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+ seg2.y,
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+ seg3.x,
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+ seg3.y,
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+ seg4.x,
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+ seg4.y
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+ )) {
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+ return true;
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+ }
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+ }
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+ }
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+ return false;
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+ }
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+ function traceOverlapsWithPad(trace, pad) {
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+ for (let i = 0; i < trace.route.length - 1; i++) {
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+ const seg1 = trace.route[i];
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+ const seg2 = trace.route[i + 1];
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+ if (seg1.route_type === "wire" && seg2.route_type === "wire" && seg1.layer === pad.layer && pad.shape === "rect") {
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+ const padLeft = pad.x - pad.width / 2;
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+ const padRight = pad.x + pad.width / 2;
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+ const padTop = pad.y - pad.height / 2;
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+ const padBottom = pad.y + pad.height / 2;
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+ if (lineIntersects(
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+ seg1.x,
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+ seg1.y,
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+ seg2.x,
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+ seg2.y,
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+ padLeft,
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+ padTop,
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+ padRight,
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+ padTop
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+ ) || lineIntersects(
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+ seg1.x,
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+ seg1.y,
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+ seg2.x,
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+ seg2.y,
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+ padRight,
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+ padTop,
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+ padRight,
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+ padBottom
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+ ) || lineIntersects(
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+ seg1.x,
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+ seg1.y,
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+ seg2.x,
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+ seg2.y,
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+ padRight,
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+ padBottom,
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+ padLeft,
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+ padBottom
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+ ) || lineIntersects(
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+ seg1.x,
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+ seg1.y,
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+ seg2.x,
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+ seg2.y,
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+ padLeft,
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+ padBottom,
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+ padLeft,
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+ padTop
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+ )) {
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+ return true;
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+ }
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+ }
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+ }
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+ return false;
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+ }
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+ function getPortIdsConnectedToTrace(trace) {
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+ const connectedPorts = /* @__PURE__ */ new Set();
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+ for (const segment of trace.route) {
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+ if (segment.route_type === "wire") {
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+ if (segment.start_pcb_port_id)
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+ connectedPorts.add(segment.start_pcb_port_id);
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+ if (segment.end_pcb_port_id) connectedPorts.add(segment.end_pcb_port_id);
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+ }
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+ }
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+ return Array.from(connectedPorts);
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+ }
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+ function getPortIdsConnectedToTraces(...traces) {
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+ const connectedPorts = /* @__PURE__ */ new Set();
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+ for (const trace of traces) {
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+ getPortIdsConnectedToTrace(trace).forEach(
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+ (portId) => connectedPorts.add(portId)
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+ );
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+ }
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+ return Array.from(connectedPorts);
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+ }
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+ function checkEachPcbTraceNonOverlapping(soup) {
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+ const pcbTraces = soup.filter(
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+ (item) => item.type === "pcb_trace"
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+ );
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+ const pcbSMTPads = soup.filter(
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+ (item) => item.type === "pcb_smtpad"
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+ );
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+ const errors = [];
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+ const netManager = new NetManager();
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+ pcbTraces.forEach(
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+ (trace) => netManager.setConnected(getPortIdsConnectedToTrace(trace))
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+ );
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+ for (let i = 0; i < pcbTraces.length; i++) {
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+ for (let j = i + 1; j < pcbTraces.length; j++) {
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+ if (netManager.isConnected(
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+ getPortIdsConnectedToTraces(pcbTraces[i], pcbTraces[j])
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+ )) {
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+ continue;
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+ }
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+ if (tracesOverlap(pcbTraces[i], pcbTraces[j])) {
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+ errors.push({
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+ type: "pcb_error",
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+ error_type: "pcb_trace_error",
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+ message: `PCB trace ${pcbTraces[i].pcb_trace_id} overlaps with ${pcbTraces[j].pcb_trace_id}`,
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+ pcb_trace_id: pcbTraces[i].pcb_trace_id,
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+ source_trace_id: "",
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+ pcb_error_id: `overlap_${pcbTraces[i].pcb_trace_id}_${pcbTraces[j].pcb_trace_id}`,
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+ pcb_component_ids: [],
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+ pcb_port_ids: getPortIdsConnectedToTraces(pcbTraces[i], pcbTraces[j])
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+ });
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+ }
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+ }
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+ for (const pad of pcbSMTPads) {
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+ if (pad.pcb_port_id && netManager.isConnected(
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+ getPortIdsConnectedToTrace(pcbTraces[i]).concat([pad.pcb_port_id])
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+ )) {
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+ continue;
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+ }
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+ if (traceOverlapsWithPad(pcbTraces[i], pad)) {
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+ errors.push({
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+ type: "pcb_error",
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+ error_type: "pcb_trace_error",
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+ message: `PCB trace ${pcbTraces[i].pcb_trace_id} overlaps with pcb_smtpad ${pad.pcb_smtpad_id}`,
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+ pcb_trace_id: pcbTraces[i].pcb_trace_id,
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+ source_trace_id: "",
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+ pcb_error_id: `overlap_${pcbTraces[i].pcb_trace_id}_${pad.pcb_smtpad_id}`,
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+ pcb_component_ids: [],
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+ pcb_port_ids: getPortIdsConnectedToTrace(pcbTraces[i])
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+ });
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+ }
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+ }
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+ }
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+ return errors;
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+ }
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+ // Annotate the CommonJS export names for ESM import in node:
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+ 0 && (module.exports = {
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+ checkEachPcbPortConnected,
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+ checkEachPcbTraceNonOverlapping
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+ });
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+ //# sourceMappingURL=index.cjs.map
@@ -0,0 +1 @@
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+ {"version":3,"sources":["../index.ts","../lib/check-each-pcb-port-connected.ts","../lib/net-manager.ts","../lib/check-each-pcb-trace-non-overlapping.ts"],"sourcesContent":["export { checkEachPcbPortConnected } from \"./lib/check-each-pcb-port-connected\"\nexport { checkEachPcbTraceNonOverlapping } from \"./lib/check-each-pcb-trace-non-overlapping\"\n","import type {\n PCBPort,\n PCBTrace,\n SourceTrace,\n AnySoupElement,\n PCBTraceError,\n} from \"@tscircuit/soup\"\n\nfunction distance(x1: number, y1: number, x2: number, y2: number): number {\n return Math.sqrt(Math.pow(x2 - x1, 2) + Math.pow(y2 - y1, 2))\n}\n\nfunction checkEachPcbPortConnected(soup: AnySoupElement[]): PCBTraceError[] {\n const pcbPorts: PCBPort[] = soup.filter((item) => item.type === \"pcb_port\")\n const pcbTraces: PCBTrace[] = soup.filter((item) => item.type === \"pcb_trace\")\n const sourceTraces: SourceTrace[] = soup.filter(\n (item) => item.type === \"source_trace\",\n )\n const errors: PCBTraceError[] = []\n\n // Add start_pcb_port_id and end_pcb_port_id if not present\n pcbTraces.forEach((trace) => {\n trace.route.forEach((segment, index) => {\n if (segment.route_type === \"wire\") {\n if (!segment.start_pcb_port_id && index === 0) {\n const startPort = pcbPorts.find(\n (port) => distance(port.x, port.y, segment.x, segment.y) < 0.001,\n )\n if (startPort) {\n segment.start_pcb_port_id = startPort.pcb_port_id\n }\n }\n if (!segment.end_pcb_port_id && index === trace.route.length - 1) {\n const endPort = pcbPorts.find(\n (port) => distance(port.x, port.y, segment.x, segment.y) < 0.001,\n )\n if (endPort) {\n segment.end_pcb_port_id = endPort.pcb_port_id\n }\n }\n }\n })\n })\n\n for (const port of pcbPorts) {\n const connectedTraces = pcbTraces.filter((trace) =>\n trace.route.some(\n (segment) =>\n segment.route_type === \"wire\" &&\n (segment.start_pcb_port_id === port.pcb_port_id ||\n segment.end_pcb_port_id === port.pcb_port_id),\n ),\n )\n\n if (connectedTraces.length === 0) {\n const sourceTrace = sourceTraces.find((trace) =>\n trace.connected_source_port_ids.includes(port.source_port_id),\n )\n\n errors.push({\n type: \"pcb_error\",\n message: `pcb_trace_error: PCB port ${port.pcb_port_id} is not connected by a PCB trace`,\n source_trace_id: sourceTrace ? sourceTrace.source_trace_id : \"\",\n error_type: \"pcb_trace_error\",\n pcb_trace_id: \"\",\n pcb_error_id: \"\", // Add appropriate ID generation if necessary\n pcb_component_ids: [],\n pcb_port_ids: [port.pcb_port_id],\n })\n }\n }\n\n return errors\n}\n\nexport { checkEachPcbPortConnected }\n","export class NetManager {\n private networks: Set<Set<string>> = new Set()\n\n setConnected(nodes: string[]): void {\n if (nodes.length < 2) return\n\n let targetNetwork: Set<string> | null = null\n\n // Check if any of the nodes are already in a network\n for (const network of this.networks) {\n for (const node of nodes) {\n if (network.has(node)) {\n if (targetNetwork === null) {\n targetNetwork = network\n } else if (targetNetwork !== network) {\n // Merge networks\n for (const mergeNode of network) {\n targetNetwork.add(mergeNode)\n }\n this.networks.delete(network)\n }\n break\n }\n }\n if (targetNetwork !== null && targetNetwork !== network) break\n }\n\n // If no existing network found, create a new one\n if (targetNetwork === null) {\n targetNetwork = new Set(nodes)\n this.networks.add(targetNetwork)\n } else {\n // Add all nodes to the target network\n for (const node of nodes) {\n targetNetwork.add(node)\n }\n }\n }\n\n isConnected(nodes: string[]): boolean {\n if (nodes.length < 2) return true\n\n for (const network of this.networks) {\n if (nodes.every((node) => network.has(node))) {\n return true\n }\n }\n\n return false\n }\n}\n","import type {\n PCBTrace,\n PCBSMTPad,\n AnySoupElement,\n PCBTraceError,\n} from \"@tscircuit/soup\"\nimport { NetManager } from \"./net-manager\"\n\n/**\n * Checks if lines given by (x1, y1) and (x2, y2) intersect with line\n * given by (x3, y3) and (x4, y4)\n */\nfunction lineIntersects(\n x1: number,\n y1: number,\n x2: number,\n y2: number,\n x3: number,\n y3: number,\n x4: number,\n y4: number,\n): boolean {\n const denom = (y4 - y3) * (x2 - x1) - (x4 - x3) * (y2 - y1)\n if (denom === 0) return false // parallel lines\n\n const ua = ((x4 - x3) * (y1 - y3) - (y4 - y3) * (x1 - x3)) / denom\n const ub = ((x2 - x1) * (y1 - y3) - (y2 - y1) * (x1 - x3)) / denom\n\n return ua >= 0 && ua <= 1 && ub >= 0 && ub <= 1\n}\n\nfunction tracesOverlap(trace1: PCBTrace, trace2: PCBTrace): boolean {\n for (let i = 0; i < trace1.route.length - 1; i++) {\n for (let j = 0; j < trace2.route.length - 1; j++) {\n const seg1 = trace1.route[i]\n const seg2 = trace1.route[i + 1]\n const seg3 = trace2.route[j]\n const seg4 = trace2.route[j + 1]\n\n if (\n seg1.route_type === \"wire\" &&\n seg2.route_type === \"wire\" &&\n seg3.route_type === \"wire\" &&\n seg4.route_type === \"wire\" &&\n seg1.layer === seg3.layer &&\n lineIntersects(\n seg1.x,\n seg1.y,\n seg2.x,\n seg2.y,\n seg3.x,\n seg3.y,\n seg4.x,\n seg4.y,\n )\n ) {\n return true\n }\n }\n }\n return false\n}\n\nfunction traceOverlapsWithPad(trace: PCBTrace, pad: PCBSMTPad): boolean {\n for (let i = 0; i < trace.route.length - 1; i++) {\n const seg1 = trace.route[i]\n const seg2 = trace.route[i + 1]\n\n if (\n seg1.route_type === \"wire\" &&\n seg2.route_type === \"wire\" &&\n seg1.layer === pad.layer &&\n pad.shape === \"rect\"\n ) {\n const padLeft = pad.x - pad.width / 2\n const padRight = pad.x + pad.width / 2\n const padTop = pad.y - pad.height / 2\n const padBottom = pad.y + pad.height / 2\n\n if (\n lineIntersects(\n seg1.x,\n seg1.y,\n seg2.x,\n seg2.y,\n padLeft,\n padTop,\n padRight,\n padTop,\n ) ||\n lineIntersects(\n seg1.x,\n seg1.y,\n seg2.x,\n seg2.y,\n padRight,\n padTop,\n padRight,\n padBottom,\n ) ||\n lineIntersects(\n seg1.x,\n seg1.y,\n seg2.x,\n seg2.y,\n padRight,\n padBottom,\n padLeft,\n padBottom,\n ) ||\n lineIntersects(\n seg1.x,\n seg1.y,\n seg2.x,\n seg2.y,\n padLeft,\n padBottom,\n padLeft,\n padTop,\n )\n ) {\n return true\n }\n }\n }\n return false\n}\n\nfunction getPortIdsConnectedToTrace(trace: PCBTrace) {\n const connectedPorts = new Set<string>()\n for (const segment of trace.route) {\n if (segment.route_type === \"wire\") {\n if (segment.start_pcb_port_id)\n connectedPorts.add(segment.start_pcb_port_id)\n if (segment.end_pcb_port_id) connectedPorts.add(segment.end_pcb_port_id)\n }\n }\n return Array.from(connectedPorts)\n}\n\nfunction getPortIdsConnectedToTraces(...traces: PCBTrace[]) {\n const connectedPorts = new Set<string>()\n for (const trace of traces) {\n getPortIdsConnectedToTrace(trace).forEach((portId) =>\n connectedPorts.add(portId),\n )\n }\n return Array.from(connectedPorts)\n}\n\nfunction checkEachPcbTraceNonOverlapping(\n soup: AnySoupElement[],\n): PCBTraceError[] {\n const pcbTraces: PCBTrace[] = soup.filter(\n (item): item is PCBTrace => item.type === \"pcb_trace\",\n )\n const pcbSMTPads: PCBSMTPad[] = soup.filter(\n (item): item is PCBSMTPad => item.type === \"pcb_smtpad\",\n )\n const errors: PCBTraceError[] = []\n const netManager = new NetManager()\n\n // TODO use source port ids instead of port ids, parse source ports for connections\n pcbTraces.forEach((trace) =>\n netManager.setConnected(getPortIdsConnectedToTrace(trace)),\n )\n\n for (let i = 0; i < pcbTraces.length; i++) {\n for (let j = i + 1; j < pcbTraces.length; j++) {\n if (\n netManager.isConnected(\n getPortIdsConnectedToTraces(pcbTraces[i], pcbTraces[j]),\n )\n ) {\n continue\n }\n if (tracesOverlap(pcbTraces[i], pcbTraces[j])) {\n errors.push({\n type: \"pcb_error\",\n error_type: \"pcb_trace_error\",\n message: `PCB trace ${pcbTraces[i].pcb_trace_id} overlaps with ${pcbTraces[j].pcb_trace_id}`,\n pcb_trace_id: pcbTraces[i].pcb_trace_id,\n source_trace_id: \"\",\n pcb_error_id: `overlap_${pcbTraces[i].pcb_trace_id}_${pcbTraces[j].pcb_trace_id}`,\n pcb_component_ids: [],\n pcb_port_ids: getPortIdsConnectedToTraces(pcbTraces[i], pcbTraces[j]),\n })\n }\n }\n\n for (const pad of pcbSMTPads) {\n if (\n pad.pcb_port_id &&\n netManager.isConnected(\n getPortIdsConnectedToTrace(pcbTraces[i]).concat([pad.pcb_port_id]),\n )\n ) {\n continue\n }\n if (traceOverlapsWithPad(pcbTraces[i], pad)) {\n errors.push({\n type: \"pcb_error\",\n error_type: \"pcb_trace_error\",\n message: `PCB trace ${pcbTraces[i].pcb_trace_id} overlaps with pcb_smtpad ${pad.pcb_smtpad_id}`,\n pcb_trace_id: pcbTraces[i].pcb_trace_id,\n source_trace_id: \"\",\n pcb_error_id: `overlap_${pcbTraces[i].pcb_trace_id}_${pad.pcb_smtpad_id}`,\n pcb_component_ids: [],\n pcb_port_ids: getPortIdsConnectedToTrace(pcbTraces[i]),\n })\n }\n }\n }\n\n return errors\n}\n\nexport { checkEachPcbTraceNonOverlapping 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@@ -0,0 +1,7 @@
1
+ import { AnySoupElement, PCBTraceError } from '@tscircuit/soup';
2
+
3
+ declare function checkEachPcbPortConnected(soup: AnySoupElement[]): PCBTraceError[];
4
+
5
+ declare function checkEachPcbTraceNonOverlapping(soup: AnySoupElement[]): PCBTraceError[];
6
+
7
+ export { checkEachPcbPortConnected, checkEachPcbTraceNonOverlapping };
package/package.json CHANGED
@@ -3,7 +3,7 @@
3
3
  "module": "index.ts",
4
4
  "type": "module",
5
5
  "main": "./dist/index.cjs",
6
- "version": "0.0.2",
6
+ "version": "0.0.4",
7
7
  "files": [
8
8
  "dist"
9
9
  ],
@@ -18,7 +18,7 @@
18
18
  "@tscircuit/soup": "^0.0.40",
19
19
  "@tscircuit/soup-util": "^0.0.13",
20
20
  "@types/bun": "latest",
21
- "tsup": "^8.2.1"
21
+ "tsup": "^8.2.3"
22
22
  },
23
23
  "peerDependencies": {
24
24
  "typescript": "^5.5.3"