@tscircuit/checks 0.0.177 → 0.0.179

package/README.md

@@ -15,6 +15,7 @@ and output an array of arrays for any issues found.
 | [`checkNoPowerPinDefined`](./lib/check-no-power-pin-defined.ts) | Returns `source_no_power_pin_defined_warning` when a chip has no pin with `requires_power=true`. |
 | [`checkNoGroundPinDefined`](./lib/check-no-ground-pin-defined.ts) | Returns `source_no_ground_pin_defined_warning` when a chip has no pin with `requires_ground=true`. |
 | [`checkSchematicComponentExcessiveVerticalPadding`](./lib/check-schematic-component-excessive-vertical-padding.ts) | Returns a `schematic_component_styling_warning` with `styling_issue_type: "excessive_top_padding"` or `"excessive_bottom_padding"` when a box-style component has more than three pin spacings of empty space above or below its left/right pins. |
+| [`checkSchematicComponentMissingReferenceDesignatorText`](./lib/check-schematic-component-missing-reference-designator-text.ts) | Returns a `schematic_component_styling_warning` with `styling_issue_type: "missing_reference_designator_text"` when a schematic component has no attached text matching its reference designator or display-name override. |
 | [`checkSchematicComponentPortsOutsideBody`](./lib/check-schematic-component-ports-outside-body.ts) | Returns a `schematic_component_styling_warning` with `styling_issue_type: "ports_outside_body"` when pins fall beyond the body edge they enter, with an actionable minimum `schHeight` or `schWidth`. |
 | [`checkDifferentNetViaSpacing`](./lib/check-different-net-via-spacing.ts) | Returns `pcb_via_clearance_error` if vias on different nets are too close together. |
 | [`checkEachPcbPortConnectedToPcbTraces`](./lib/check-each-pcb-port-connected-to-pcb-trace.ts) | Returns `pcb_trace_error` if any `source_port` is not connected to its corresponding PCB traces. |
@@ -39,7 +40,7 @@ and output an array of arrays for any issues found.
 | [`runAllPlacementChecks`](./lib/run-all-checks.ts) | Runs placement checks (`checkCopperToBoardEdgeClearance`, `checkPcbComponentsOutOfBoard`, `checkPcbCopperOverKeepout`, `checkPcbComponentOverlap`, `checkPadPadClearance`, `checkCourtyardOverlap`, `checkConnectorAccessibleOrientation`, and `checkTestPointAccessibility`). |
 | [`runAllNetlistChecks`](./lib/run-all-checks.ts) | Runs netlist connectivity checks (currently `checkPinMustBeConnected`). |
 | [`runAllPinSpecificationChecks`](./lib/run-all-checks.ts) | Runs pin specification checks (e.g. `checkAllPinsInComponentAreUnderspecified`, `checkNoPowerPinDefined`, and `checkNoGroundPinDefined`). |
-| [`runAllSchematicChecks`](./lib/run-all-checks.ts) | Runs schematic-layout checks (currently `checkSchematicComponentExcessiveVerticalPadding`). |
+| [`runAllSchematicChecks`](./lib/run-all-checks.ts) | Runs schematic-layout checks (`checkSchematicComponentExcessiveVerticalPadding`, `checkSchematicComponentMissingReferenceDesignatorText`, and `checkSchematicComponentPortsOutsideBody`). |
 | [`runAllRoutingChecks`](./lib/run-all-checks.ts) | Runs all routing checks currently enabled (`checkEachPcbPortConnectedToPcbTraces`, `checkSourceTracesHavePcbTraces`, `checkEachPcbTraceNonOverlapping`, `checkPadTraceClearance`, `checkViaTraceClearance`, same/different net via spacing, and `checkPcbTracesOutOfBoard`). Trace-obstacle pairs are classified before aggregation, so each pair produces one overlap or clearance diagnostic, never both. |
 | [`runAllChecks`](./lib/run-all-checks.ts) | Runs placement, schematic, netlist, pin specification, and routing checks and returns a combined list of issues. |
 

package/dist/index.d.ts

@@ -168,6 +168,12 @@ declare function checkNoGroundPinDefined(circuitJson: AnyCircuitElement[]): Sour
  */
 declare function checkSchematicComponentExcessiveVerticalPadding(circuitJson: AnyCircuitElement[]): SchematicComponentStylingWarning[];
 
+/**
+ * Warns when a schematic component does not have attached text displaying its
+ * reference designator (or the component's display-name override).
+ */
+declare function checkSchematicComponentMissingReferenceDesignatorText(circuitJson: AnyCircuitElement[]): SchematicComponentStylingWarning[];
+
 /**
  * Warns when a box-style component's pins are positioned beyond the body edge
  * they enter. Left/right pins are checked against the body's vertical span,
@@ -207,4 +213,4 @@ declare function checkConnectorAccessibleOrientation(circuitJson: AnyCircuitElem
  */
 declare function checkTestPointAccessibility(circuitJson: AnyCircuitElement[]): PcbPlacementError[];
 
-export { NetManager, checkAllPinsInComponentAreUnderspecified, checkConnectorAccessibleOrientation, checkCopperToBoardEdgeClearance, checkDifferentNetViaSpacing, checkEachPcbPortConnectedToPcbTraces, checkEachPcbTraceNonOverlapping, checkNoGroundPinDefined, checkNoPowerPinDefined, checkPadPadClearance, checkPadTraceClearance, checkPcbComponentOverCutout, checkPcbComponentOverlap, checkPcbComponentsMissingCourtyard, checkPcbComponentsOutOfBoard, checkPcbCopperOverKeepout, checkPcbTraceLengths, checkPcbTraceViaCounts, checkPcbTracesOutOfBoard, checkPinMustBeConnected, checkSameNetViaSpacing, checkSchematicComponentExcessiveVerticalPadding, checkSchematicComponentPortsOutsideBody, checkSourceTracesHavePcbTraces, checkSourceTracesMatchPcbTraceThickness, checkTestPointAccessibility, checkTracesAreContiguous, checkViaPadClearance, checkViaTraceClearance, checkViasInPads, checkViasOffBoard, dedupePcbDrcErrors, runAllChecks, runAllNetlistChecks, runAllPinSpecificationChecks, runAllPlacementChecks, runAllRoutingChecks, runAllSchematicChecks };
+export { NetManager, checkAllPinsInComponentAreUnderspecified, checkConnectorAccessibleOrientation, checkCopperToBoardEdgeClearance, checkDifferentNetViaSpacing, checkEachPcbPortConnectedToPcbTraces, checkEachPcbTraceNonOverlapping, checkNoGroundPinDefined, checkNoPowerPinDefined, checkPadPadClearance, checkPadTraceClearance, checkPcbComponentOverCutout, checkPcbComponentOverlap, checkPcbComponentsMissingCourtyard, checkPcbComponentsOutOfBoard, checkPcbCopperOverKeepout, checkPcbTraceLengths, checkPcbTraceViaCounts, checkPcbTracesOutOfBoard, checkPinMustBeConnected, checkSameNetViaSpacing, checkSchematicComponentExcessiveVerticalPadding, checkSchematicComponentMissingReferenceDesignatorText, checkSchematicComponentPortsOutsideBody, checkSourceTracesHavePcbTraces, checkSourceTracesMatchPcbTraceThickness, checkTestPointAccessibility, checkTracesAreContiguous, checkViaPadClearance, checkViaTraceClearance, checkViasInPads, checkViasOffBoard, dedupePcbDrcErrors, runAllChecks, runAllNetlistChecks, runAllPinSpecificationChecks, runAllPlacementChecks, runAllRoutingChecks, runAllSchematicChecks };

package/dist/index.js

@@ -3383,6 +3383,19 @@ var getPcbTraceLength = (pcbTrace) => {
   }
   return traceLength;
 };
+var getReferencedPcbPortIds = (pcbTrace) => {
+  const pcbPortIds = /* @__PURE__ */ new Set();
+  for (const routePoint of pcbTrace.route) {
+    if (routePoint.route_type !== "wire") continue;
+    if (routePoint.start_pcb_port_id) {
+      pcbPortIds.add(routePoint.start_pcb_port_id);
+    }
+    if (routePoint.end_pcb_port_id) {
+      pcbPortIds.add(routePoint.end_pcb_port_id);
+    }
+  }
+  return pcbPortIds;
+};
 var checkPcbTraceLengths = (circuitJson) => {
   const sourceTraces = circuitJson.filter(
     (element) => element.type === "source_trace"
@@ -3390,12 +3403,53 @@ var checkPcbTraceLengths = (circuitJson) => {
   const pcbTraces = circuitJson.filter(
     (element) => element.type === "pcb_trace"
   );
+  const pcbPorts = circuitJson.filter(
+    (element) => element.type === "pcb_port"
+  );
   const sourceTracesById = new Map(
     sourceTraces.map((sourceTrace) => [
       sourceTrace.source_trace_id,
       sourceTrace
     ])
   );
+  const pcbPortIdsBySourcePortId = /* @__PURE__ */ new Map();
+  for (const pcbPort of pcbPorts) {
+    if (!pcbPort.source_port_id) continue;
+    const pcbPortIds = pcbPortIdsBySourcePortId.get(pcbPort.source_port_id) ?? /* @__PURE__ */ new Set();
+    pcbPortIds.add(pcbPort.pcb_port_id);
+    pcbPortIdsBySourcePortId.set(pcbPort.source_port_id, pcbPortIds);
+  }
+  const pcbTracesBySourceTraceId = /* @__PURE__ */ new Map();
+  for (const pcbTrace of pcbTraces) {
+    if (!pcbTrace.source_trace_id) continue;
+    const matchingPcbTraces = pcbTracesBySourceTraceId.get(pcbTrace.source_trace_id) ?? [];
+    matchingPcbTraces.push(pcbTrace);
+    pcbTracesBySourceTraceId.set(pcbTrace.source_trace_id, matchingPcbTraces);
+  }
+  const exactEndpointPcbTraceIdsBySourceTraceId = /* @__PURE__ */ new Map();
+  for (const sourceTrace of sourceTraces) {
+    if (sourceTrace.connected_source_port_ids.length !== 2) continue;
+    const endpointPcbPortIds = sourceTrace.connected_source_port_ids.map(
+      (sourcePortId) => pcbPortIdsBySourcePortId.get(sourcePortId)
+    );
+    if (endpointPcbPortIds.some((pcbPortIds) => !pcbPortIds?.size)) continue;
+    const exactEndpointPcbTraceIds = new Set(
+      (pcbTracesBySourceTraceId.get(sourceTrace.source_trace_id) ?? []).filter((pcbTrace) => {
+        const referencedPcbPortIds = getReferencedPcbPortIds(pcbTrace);
+        return endpointPcbPortIds.every(
+          (pcbPortIds) => [...pcbPortIds].some(
+            (pcbPortId) => referencedPcbPortIds.has(pcbPortId)
+          )
+        );
+      }).map((pcbTrace) => pcbTrace.pcb_trace_id)
+    );
+    if (exactEndpointPcbTraceIds.size > 0) {
+      exactEndpointPcbTraceIdsBySourceTraceId.set(
+        sourceTrace.source_trace_id,
+        exactEndpointPcbTraceIds
+      );
+    }
+  }
   const warnings = [];
   for (const pcbTrace of pcbTraces) {
     if (!pcbTrace.source_trace_id) continue;
@@ -3403,6 +3457,10 @@ var checkPcbTraceLengths = (circuitJson) => {
     if (!sourceTrace) continue;
     const maximumTraceLength = sourceTrace.max_length;
     if (typeof maximumTraceLength !== "number") continue;
+    const exactEndpointPcbTraceIds = exactEndpointPcbTraceIdsBySourceTraceId.get(sourceTrace.source_trace_id);
+    if (exactEndpointPcbTraceIds && !exactEndpointPcbTraceIds.has(pcbTrace.pcb_trace_id)) {
+      continue;
+    }
     const actualTraceLength = getPcbTraceLength(pcbTrace);
     if (actualTraceLength <= maximumTraceLength) continue;
     warnings.push({
@@ -4062,6 +4120,85 @@ function checkSchematicComponentExcessiveVerticalPadding(circuitJson) {
   return warnings;
 }
 
+// lib/check-schematic-component-missing-reference-designator-text.ts
+var isFallbackReferenceDesignator = (name) => /^unnamed_[a-z0-9_-]+\d+$/i.test(name);
+var isTextWithinComponentBounds = (schematicText, schematicComponent) => {
+  const { center, size } = schematicComponent;
+  const tolerance = 1e-9;
+  return schematicText.position.x >= center.x - size.width / 2 - tolerance && schematicText.position.x <= center.x + size.width / 2 + tolerance && schematicText.position.y >= center.y - size.height / 2 - tolerance && schematicText.position.y <= center.y + size.height / 2 + tolerance;
+};
+function checkSchematicComponentMissingReferenceDesignatorText(circuitJson) {
+  const schematicComponents = circuitJson.filter(
+    (element) => element.type === "schematic_component"
+  );
+  const sourceComponents = circuitJson.filter(
+    (element) => element.type === "source_component"
+  );
+  const schematicTexts = circuitJson.filter(
+    (element) => element.type === "schematic_text"
+  );
+  const sourceComponentById = new Map(
+    sourceComponents.map((component) => [
+      component.source_component_id,
+      component
+    ])
+  );
+  const textBySchematicComponentId = /* @__PURE__ */ new Map();
+  const customSymbolTexts = [];
+  for (const schematicText of schematicTexts) {
+    if (!schematicText.schematic_component_id) {
+      if (schematicText.schematic_symbol_id) {
+        customSymbolTexts.push(schematicText);
+      }
+      continue;
+    }
+    const componentTexts = textBySchematicComponentId.get(schematicText.schematic_component_id) ?? /* @__PURE__ */ new Set();
+    componentTexts.add(schematicText.text.trim());
+    textBySchematicComponentId.set(
+      schematicText.schematic_component_id,
+      componentTexts
+    );
+  }
+  const warnings = [];
+  for (const schematicComponent of schematicComponents) {
+    if (!schematicComponent.source_component_id) continue;
+    const sourceComponent = sourceComponentById.get(
+      schematicComponent.source_component_id
+    );
+    if (!sourceComponent) continue;
+    const referenceDesignators = new Set(
+      [sourceComponent.name, sourceComponent.display_name].map((name) => name?.trim()).filter((name) => Boolean(name))
+    );
+    const nonFallbackReferenceDesignator = [...referenceDesignators].find(
+      (referenceDesignator) => !isFallbackReferenceDesignator(referenceDesignator)
+    );
+    const componentTexts = textBySchematicComponentId.get(
+      schematicComponent.schematic_component_id
+    );
+    const hasReferenceDesignatorText = [...referenceDesignators].some(
+      (referenceDesignator) => componentTexts?.has(referenceDesignator)
+    ) || customSymbolTexts.some(
+      (schematicText) => referenceDesignators.has(schematicText.text.trim()) && isTextWithinComponentBounds(schematicText, schematicComponent)
+    );
+    if (nonFallbackReferenceDesignator && hasReferenceDesignatorText) {
+      continue;
+    }
+    const readableComponentName = nonFallbackReferenceDesignator ?? "Schematic component";
+    warnings.push({
+      type: "schematic_component_styling_warning",
+      schematic_component_styling_warning_id: `schematic_component_styling_warning_${schematicComponent.schematic_component_id}_missing_reference_designator_text`,
+      warning_type: "schematic_component_styling_warning",
+      message: `${readableComponentName} is missing schematic reference designator text. For a custom symbol, add name="{REFDES}" inside the symbol.`,
+      schematic_component_id: schematicComponent.schematic_component_id,
+      styling_issue_type: "missing_reference_designator_text",
+      source_component_id: schematicComponent.source_component_id,
+      schematic_sheet_id: schematicComponent.schematic_sheet_id,
+      subcircuit_id: schematicComponent.subcircuit_id
+    });
+  }
+  return warnings;
+}
+
 // lib/check-schematic-component-ports-outside-body.ts
 var FLOATING_POINT_TOLERANCE2 = 1e-9;
 var getPortLabel = (port) => port.display_pin_label ?? `pin ${port.pin_number}`;
@@ -4451,6 +4588,7 @@ async function runAllNetlistChecks(circuitJson) {
 async function runAllSchematicChecks(circuitJson) {
   return [
     ...checkSchematicComponentExcessiveVerticalPadding(circuitJson),
+    ...checkSchematicComponentMissingReferenceDesignatorText(circuitJson),
     ...checkSchematicComponentPortsOutsideBody(circuitJson)
   ];
 }
@@ -4509,6 +4647,7 @@ export {
   checkPinMustBeConnected,
   checkSameNetViaSpacing,
   checkSchematicComponentExcessiveVerticalPadding,
+  checkSchematicComponentMissingReferenceDesignatorText,
   checkSchematicComponentPortsOutsideBody,
   checkSourceTracesHavePcbTraces,
   checkSourceTracesMatchPcbTraceThickness,