@tachikomagundam/abathur 0.2.6 → 0.2.8

package/graders/pcb-agent/seed/tools/board_author_pcb.py

@@ -0,0 +1,237 @@
+#!/usr/bin/env python3
+"""r17 deterministic PCB author: netlist.json + spec footprints -> placed .kicad_pcb.
+RM-56 doctrine: no bytes through a model. Embeds real .kicad_mod libs from the
+KiCad AppDir, injects (net N "NAME") per pad (name-match, else positional match
+with WARN), shelf placement by footprint bbox + clearance, Edge.Cuts rect.
+DRC gate (board_gate_pcb.py) evaluates placement-class errors; unconnected_items
+are expected pre-routing and reported separately."""
+import json, re, os, sys
+from collections import defaultdict
+
+ALIASES = {}
+_ali = os.path.join(os.path.dirname(os.path.abspath(__file__)), "board_author_aliases.json")
+if os.path.exists(_ali):
+    ALIASES = {tuple(k.split("|")): v for k, v in json.load(open(_ali)).items()}
+
+FP_ROOT = "/home/lab/.local/AppDir/share/kicad/footprints"
+PLACE_MARGIN = 3.0   # mm between footprint bboxes (courtyard-ish)
+GRID = 0.1
+
+
+def snap(v):
+    return round(v / GRID) * GRID
+
+
+def forms(s):
+    """top-level s-expr blocks inside a ( ... ) wrapper string."""
+    out = []
+    i = 0
+    n = len(s)
+    while i < n:
+        if s[i] == "(":
+            depth = 0
+            j = i
+            instr = False
+            while j < n:
+                ch = s[j]
+                if ch == '"' and (j == 0 or s[j - 1] != "\\"):
+                    instr = not instr
+                elif not instr:
+                    if ch == "(":
+                        depth += 1
+                    elif ch == ")":
+                        depth -= 1
+                        if depth == 0:
+                            break
+                j += 1
+            out.append(s[i:j + 1])
+            i = j + 1
+        else:
+            i += 1
+    return out
+
+
+def sub_block(s, token):
+    """return (block, start, end) of first block starting with token, else None"""
+    for b in forms(s):
+        if b.startswith(f"({token}"):
+            return b
+    return None
+
+
+def bbox_of(km):
+    """rough extent from pads + courtyard graphic lines/rects."""
+    xs, ys = [], []
+    for m in re.finditer(r'\(pad[^()]*?\(at ([-\d.]+)(?: ([-\d.]+))?\)(?:\s*\(size ([-\d.]+) ([-\d.]+))?', km):
+        x, y = float(m.group(1)), float(m.group(2) or 0)
+        w, h = (float(m.group(3)), float(m.group(4))) if m.group(3) else (1.0, 1.0)
+        xs += [x - w / 2, x + w / 2]
+        ys += [y - h / 2, y + h / 2]
+    for m in re.finditer(r'\((?:xy|start|end|at) ([-\d.]+) ([-\d.]+)', km):
+        xs.append(float(m.group(1)))
+        ys.append(float(m.group(2)))
+    if not xs:
+        return -1, -1, 2, 2
+    pad = 0.5
+    return min(xs) - pad, min(ys) - pad, max(xs) + pad, max(ys) + pad
+
+
+def resolve_footprint(spec_fp):
+    lib, name = spec_fp.split(":", 1)
+    p = os.path.join(FP_ROOT, f"{lib}.pretty", f"{name}.kicad_mod")
+    return p if os.path.exists(p) else None
+
+
+def assign_nets(netlist):
+    nets = sorted({n for c in netlist["components"] for n in c["pins"].values()})
+    code = {n: i + 1 for i, n in enumerate(nets)}
+    return nets, code
+
+
+def author(netlist_path, out_path, rot_by_ref=None):
+    d = json.load(open(netlist_path))
+    comps = d["components"]
+    nets, ncode = assign_nets(d)
+    uuidn = [0]
+
+    def U():
+        uuidn[0] += 1
+        x = f"{uuidn[0]:032x}"
+        return f"{x[:8]}-{x[8:12]}-{x[12:16]}-{x[16:20]}-{x[20:32]}"
+
+    # ---- layout pass: shelf by bbox heights
+    items = []
+    warn = []
+    for c in sorted(comps, key=lambda c: (c["ref"][0], int(re.sub(r"\D", "", c["ref"]) or 0))):
+        fpp = resolve_footprint(c["footprint"])
+        if not fpp:
+            warn.append(f"NO-FOOTPRINT {c['ref']} {c['footprint']}")
+            continue
+        km = open(fpp).read()
+        x0, y0, x1, y1 = bbox_of(km)
+        items.append([c, km, snap(x1 - x0) + PLACE_MARGIN, snap(y1 - y0) + PLACE_MARGIN, (x0, y0)])
+    COL_W = 120.0
+    cx, cy, rowh = 10.0, 10.0, 0.0
+    placed = []
+    for it in items:
+        if cx + it[2] > COL_W:
+            cx = 10.0
+            cy += rowh
+            rowh = 0.0
+        placed.append((it, snap(cx), snap(cy)))
+        cx += it[2]
+        rowh = max(rowh, it[3])
+    board_w, board_h = snap(COL_W + 20), snap(cy + rowh + 20)
+
+    # ---- emit
+    L = ['(kicad_pcb (version 20260206) (generator "board_author_pcb") (generator_version "10.0")',
+         '  (general (thickness 1.6) (legacy_teardrops no))',
+         '  (paper "A3")',
+         '  (layers (0 "F.Cu" signal) (31 "B.Cu" signal) (32 "B.Adhes" user "B.Adhesive") '
+         '(33 "F.Adhes" user "F.Adhesive") (34 "B.Paste" user) (35 "F.Paste" user) '
+         '(36 "B.SilkS" user "B.Silkscreen") (37 "F.SilkS" user "F.Silkscreen") '
+         '(38 "B.Mask" user) (39 "F.Mask" user) (40 "Dwgs.User" user "User.Drawings") '
+         '(44 "Edge.Cuts" user) (45 "Margin" user "BoardOutline") (46 "B.CrtYd" user "B.Courtyard") '
+         '(47 "F.CrtYd" user "F.Courtyard") (48 "B.Fab" user) (49 "F.Fab" user) (50 "User.1" user))',
+         '  (setup (pad_to_mask_clearance 0))',
+         '  (net_class "Default" "" (clearance 0.2) (trace_width 0.25) (via_dia 0.6) (via_drill 0.3) (uvia_dia 0.3) (uvia_drill 0.1)'
+         + " " + "".join(f'(add_net "{esc(n)}")' for n in sorted(nets)) + ')']
+    L.append('  (net 0 "")')
+    for n in nets:
+        L.append(f'  (net {ncode[n]} "{n.replace(chr(92), chr(92)*2).replace(chr(34), chr(92)+chr(34))}")')
+    # Edge.Cuts rectangle
+    pts = [(5, 5), (board_w, 5), (board_w, board_h - 5), (5, board_h - 5), (5, 5)]
+    for i in range(4):
+        L.append(f'  (gr_line (start {pts[i][0]} {pts[i][1]}) (end {pts[i+1][0]} {pts[i+1][1]})'
+                 f' (stroke (width 0.1) (type solid)) (layer "Edge.Cuts") (uuid "{U()}"))')
+    for (it, px, py) in placed:
+        c, km, _, _, (x0, y0) = it
+        ref = c["ref"]
+        pins = c["pins"]
+        # pad name -> net number string; match footprint pad names
+        fp_padnames = re.findall(r'\(pad "([^"]*)"', km)  # file order; '' = np/mount hole
+        named = [n for n in fp_padnames if n]
+        mapping = {}
+        alias = ALIASES.get((ref, c["footprint"]))
+        if alias:
+            mapping = dict(alias)
+        elif set(pins) <= set(named):
+            pass  # identity match on covered pins; extra pads (shell/np) stay net 0
+        elif len(named) == len(pins):
+            order_pins = sorted(pins, key=lambda pin: int(pin) if pin.isdigit() else 0)
+            for fpn, spp in zip(named, order_pins):
+                mapping.setdefault(fpn, spp)
+            warn.append(f"POSITIONAL-MAP {ref} {c['footprint']}: {len(named)} pads zipped to spec pins — NO authority table, verify datasheet")
+        else:
+            warn.append(f"NO-AUTHORITY-MAP {ref} {c['footprint']}: pads {sorted(set(named))[:8]} vs spec pins {sorted(pins)[:8]} -> design-data GAP, net 0 (refusing to guess)")
+        # origin so that bbox min lands at px,py
+        ox, oy = snap(px - x0), snap(py - y0)
+        head = f'  (footprint "{esc(c["footprint"])}" (layer "F.Cu") (uuid "{U()}") (at {ox} {oy})'
+        head += (f' (property "Reference" "{esc(ref)}" (at 0 -1 0) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15))))'
+                 f' (property "Value" "{esc(c.get("mpn", ref))}" (at 0 1 0) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15))))')
+        body = km[km.index("(attr"):] if "(attr" in km else km[km.rindex(")"):]
+        # inject nets into pad blocks
+        out_km = []
+        pos = 0
+        for pb in forms(body):
+            m = re.match(r'\(pad "([^"]+)"', pb)
+            s, e = body.find(pb, pos), body.find(pb, pos) + len(pb)
+            if m:
+                padname = m.group(1)
+                pin = None if padname == "" else mapping.get(padname, padname if padname in pins else None)
+                if pin is not None:
+                    net = pins[pin]
+                    ins = f' (net {ncode[net]} "{esc(net)}")'
+                    pb = pb[:-1] + ins + ")"
+                pos = e
+            out_km.append((s, pb))
+        rebuilt = body
+        for s, pb in reversed(out_km):
+            e = s + None if False else s
+        # simpler: replace each original pad block string once
+        # (do textual replacement with count=1 on the ORIGINAL blocks)
+        for orig_pb in [b for b in forms(body) if b.startswith('(pad ')]:
+            new_pb = next(p for (s, p) in out_km if s == body.find(orig_pb))
+            rebuilt = rebuilt.replace(orig_pb, new_pb, 1)
+        rebuilt = rebuilt[:rebuilt.rindex(")")]  # strip trailing close of fp file
+        L.append(head + "\n" + rebuilt + "\n  )")
+    L.append(')\n')
+    open(out_path, "w").write("\n".join(x for x in L if x) + "\n")
+    pro = out_path[:-len(".kicad_pcb")] + ".kicad_pro"
+    import json as _j
+    _j.dump({
+        "board": {"design_settings": {
+            "defaults": {"board_outline_line_width": 0.1, "copper_line_width": 0.2,
+                         "solder_mask_clearance": 0.0, "solder_mask_min_width": 0.0,
+                         "allow_soldermask_bridges_in_footprints": True},
+            "drc_exclusions": [],
+            "rules": {"min_hole_to_hole": 0.15, "min_through_hole_diameter": 0.15,
+                      "min_clearance": 0.2, "min_connection": 0.0,
+                      "min_copper_edge_clearance": 0.1, "min_hole_clearance": 0.15,
+                      "min_silk_clearance": 0.0, "min_text_height": 0.8,
+                      "min_text_thickness": 0.12, "min_track_width": 0.15,
+                      "min_via_annular_width": 0.1, "min_via_diameter": 0.45,
+                      "solder_mask_to_copper_clearance": 0.0, "use_height_for_length_calcs": True}}},
+        "libraries": {"fp_files": []},
+        "meta": {"filename": pro.split("/")[-1], "version": 3},
+        "net_settings": {"classes": [{"name": "Default", "clearance": 0.2,
+            "trace_width": 0.25, "via_dia": 0.6, "via_drill": 0.2, "uvia_dia": 0.3,
+            "uvia_drill": 0.1, "allow_soldermask_bridges_in_footprints": True}],
+            "meta": {"version": 3}},
+        "pcbnew": {"last_paths": {}},
+        "sheets": [], "text_variables": {}},
+        open(pro, "w"), indent=1)
+    return nets, warn, board_w, board_h
+
+
+def esc(s):
+    return str(s).replace("\\", "\\\\").replace('"', '\\"')
+
+
+if __name__ == "__main__":
+    nl = sys.argv[1]
+    out = sys.argv[2]
+    nets, warn, w, h = author(nl, out)
+    print(f"authored {out}: nets={len(nets)} board={w}x{h}mm")
+    for x in warn:
+        print("WARN", x)

package/graders/pcb-agent/seed/tools/board_author_sch.py

@@ -0,0 +1,118 @@
+#!/usr/bin/env python3
+"""r17 deterministic schematic author (RM-56: netlist bytes NEVER through a model).
+Topology: NO wires. Every pin gets one global label anchored EXACTLY on the pin
+end, rotation 180 (text left, away from body). Anchor == pin end by construction;
+no dangling labels (r13 D1 defect class), no collinear merges. Grid 0.635 mm.
+Usage: board_author_sch.py netlist.json -o out.kicad_sch"""
+import json, re, argparse
+from collections import defaultdict
+
+G = 0.635
+COLPITCH = 99.06   # column pitch (41-pin U1 fans 52mm left of anchor col)
+ROWPITCH = 76.2    # row pitch; keep > 2.54 * maxpins/2 stack of neighbours
+PINPITCH = 2.54    # pin vertical spacing (label height 1.27 leaves 1.27 gap)
+
+
+def snap(v):
+    return round(v / G) * G
+
+
+def esc(s):
+    return str(s).replace("\\", "\\\\").replace('"', '\\"')
+
+
+class Uuid:
+    def __init__(self):
+        self.n = 0
+
+    def __call__(self):
+        self.n += 1
+        x = f"{self.n:032x}"
+        return f"{x[:8]}-{x[8:12]}-{x[12:16]}-{x[16:20]}-{x[20:32]}"
+
+
+def pin_order(pins):
+    return sorted(pins, key=lambda p: int(p) if p.isdigit() else 0)
+
+
+def build(netlist_path, out_path):
+    d = json.load(open(netlist_path))
+    comps = d["components"]
+    u = Uuid()
+    order = sorted(comps, key=lambda c: (c["ref"][0], int(re.sub(r"\D", "", c["ref"]) or 0)))
+    pos = {}
+    for slot, c in enumerate(order):
+        row, col = divmod(slot, 4)
+        pos[c["ref"]] = (snap(60 + col * COLPITCH), snap(60 + row * ROWPITCH))
+    # symbol defs: single-sided fan-left, PINPITCH spacing
+    prefix_pins = {}
+    pinset = {}
+    for c in order:
+        ref = c["ref"]
+        ps = pin_order(c["pins"])
+        key = "SR_" + re.sub(r"\d+$", "", ref)
+        if key in prefix_pins and prefix_pins[key] != ps:
+            key = "SR_" + ref
+        prefix_pins.setdefault(key, ps)
+        c["_key"] = key
+        sx, sy = pos[ref]
+        n = len(ps)
+        # world y-down vs lib-symbol-local y-UP: the def emits oy=+off (up) per
+        # pin slot i; the label anchor in SHEET coords must therefore SUBTRACT.
+        pinset[ref] = [(p, snap(sx - 5.08), snap(sy - ((n - 1) / 2 - i) * PINPITCH))
+                       for i, p in enumerate(ps)]
+    labels = []
+    for c in order:
+        for pnum, net in c["pins"].items():
+            px, py = next((ax, ay) for (pp, ax, ay) in pinset[c["ref"]] if pp == pnum)
+            labels.append((net, px, py))
+    L = ['(kicad_sch (version 20250114) (generator "board_author_sch") (generator_version "10.0.5")',
+         f'  (uuid "{u()}")', '  (paper "A3")', '  (lib_symbols']
+    for key, ps in sorted(prefix_pins.items()):
+        n = len(ps)
+        L.append(f'    (symbol "solar_ray:{esc(key)}"')
+        L.append('      (pin_numbers (hide yes))')
+        L.append('      (pin_names (offset 1.016))')
+        L.append('      (exclude_from_sim no) (in_bom yes) (on_board yes)')
+        L.append('      (property "Reference" "U" (at 0 0 0) (effects (font (size 1.27 1.27))))')
+        L.append('      (property "Value" "V" (at 0 0 0) (effects (font (size 1.27 1.27))))')
+        L.append('      (property "Footprint" "" (at 0 0 0) (effects (font (size 1.27 1.27)) (hide yes)))')
+        L.append('      (property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) (hide yes)))')
+        L.append(f'      (symbol "{esc(key)}_1_1"')
+        for i, p in enumerate(ps):
+            oy = snap(((n - 1) / 2 - i) * PINPITCH)
+            L.append(f'        (pin passive line (at {-5.08} {oy} 0) (length 5.08)'
+                     f' (name "~" (effects (font (size 1.016 1.016))))'
+                     f' (number "{esc(p)}" (effects (font (size 1.016 1.016)))))')
+        L.append('      )')
+        L.append('      (embedded_fonts no)')
+        L.append('    )')
+    L.append('  )')
+    for c in order:
+        ref = c["ref"]
+        sx, sy = pos[ref]
+        L.append(f'    (symbol (lib_id "solar_ray:{esc(c["_key"])}") (at {sx} {sy} 0) (unit 1)')
+        L.append('      (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced no)')
+        L.append(f'      (uuid "{u()}")')
+        for k, v, xo in (("Reference", ref, -2.54), ("Value", c.get("mpn", ref), 2.54),
+                         ("Footprint", c.get("footprint", ""), 0.0), ("Datasheet", "", 0.0)):
+            L.append(f'      (property "{k}" "{esc(v)}" (at {snap(sx+xo)} {snap(sy+5.08)} 0)'
+                     f' (effects (font (size 1.27 1.27)) (hide yes)))')
+        for (p, _, _) in pinset[ref]:
+            L.append(f'      (pin "{esc(p)}" (uuid "{u()}"))')
+        L.append('    )')
+    for net, x, y in labels:
+        L.append(f'    (global_label "{esc(net)}" (shape passive) (at {x} {y} 180)'
+                 f' (effects (font (size 1.27 1.27)) (justify left)) (uuid "{u()}"))')
+    L += ['  (sheet_instances', '    (path "/" (page "1"))', '  )', '  (embedded_fonts no)', ')']
+    open(out_path, "w").write("\n".join(L) + "\n")
+    return len(order), len(labels)
+
+
+if __name__ == "__main__":
+    ap = argparse.ArgumentParser()
+    ap.add_argument("netlist")
+    ap.add_argument("-o", "--out", required=True)
+    a = ap.parse_args()
+    s, l = build(a.netlist, a.out)
+    print(f"emitted {a.out}: symbols={s} labels={l}")

package/graders/pcb-agent/seed/tools/board_finalize.sh

@@ -0,0 +1,23 @@
+#!/bin/bash
+# r17 finalization pipeline: routed board -> pour -> native refill -> DRC gate -> fab exports
+set -e
+IN="${1:?routed kicad_pcb}"
+OUT="${2:?output board pcb}"
+RUN="${3:-evolution-round-17}"
+cd /home/lab/workspace/pcb-control
+python3 tools/board_zone_pour.py "$IN" "$OUT"
+cp /tmp/sr-c4.kicad_pro "$(dirname "$OUT")/$(basename "$OUT" .kicad_pcb).kicad_pro"
+D=/home/lab/workspace/pcb-control/reports/recovery/$RUN
+kicad-cli pcb drc "$OUT" --refill-zones --save-board --format json --severity-error --output "$D/$(basename "$OUT").drc-refill.json" >/dev/null 2>&1
+kicad-cli pcb drc "$OUT" --format json --severity-error --output "$D/$(basename "$OUT").drc-final.json" >/dev/null 2>&1
+python3 - "$D/$(basename "$OUT").drc-final.json" <<'EOF'
+import json, sys, collections
+d = json.load(open(sys.argv[1]))
+v = d.get('violations', []); u = d.get('unconnected_items', [])
+print(f"GATE: errors={len(v)} {dict(collections.Counter(x.get('type','?') for x in v))} unconnected={len(u)}")
+EOF
+mkdir -p "$D/fab-out"
+kicad-cli pcb export gerbers "$OUT" -o "$D/fab-out/gerbers.zip" >/dev/null
+kicad-cli pcb export drill "$OUT" -o "$D/fab-out/" >/dev/null
+kicad-cli pcb export pos "$OUT" -o "$D/fab-out/pos.pos" --units mm >/dev/null
+echo "fab exports -> $D/fab-out/"; ls "$D/fab-out/" | head

package/graders/pcb-agent/seed/tools/board_gate.py

@@ -0,0 +1,69 @@
+#!/usr/bin/env python3
+"""r17 board gate: ERC-clean + netlist-exact roundtrip for an authored sheet.
+Exit 0 only when: ERC 0 errors, 0 unconnected, and EVERY spec net appears in the
+export with EXACTLY its spec membership (and no extra nets). Closes the r13 D1
+defect class deterministically (no model in the byte path)."""
+import json, re, subprocess, sys, tempfile, os
+from collections import defaultdict
+
+def main(sch, netlist_json):
+    spec = json.load(open(netlist_json))
+    got = defaultdict(set)
+    for c in spec["components"]:
+        for p, net in c["pins"].items():
+            got[net].add(f"{c['ref']}.{p}")
+    with tempfile.TemporaryDirectory() as td:
+        erc = os.path.join(td, "erc.json"); net = os.path.join(td, "netlist.net")
+        r1 = subprocess.run(["kicad-cli", "sch", "erc", sch, "--format", "json",
+                             "--severity-error", "--output", erc], capture_output=True, text=True)
+        r2 = subprocess.run(["kicad-cli", "sch", "export", "netlist", sch, "-o", net],
+                            capture_output=True, text=True)
+        if r1.returncode or not os.path.exists(erc):
+            print(f"FAIL ERC_RUN rc={r1.returncode} {r1.stderr[:200]}"); return 1
+        if r2.returncode or not os.path.exists(net):
+            print(f"FAIL EXPORT rc={r2.returncode} {r2.stderr[:200]}"); return 1
+        d = json.load(open(erc))
+        sh = d["sheets"][0].get("erc", {})
+        v, u = sh.get("violations", []), sh.get("unconnected", [])
+        if v or u:
+            print(f"FAIL ERC violations={len(v)} unconnected={len(u)}")
+            for x in v[:6]: print("  ", json.dumps(x)[:180])
+            return 1
+        txt = open(net).read()
+        # parenthesis-balanced extraction of each (net ...) block (regex cannot
+        # nest; truncation risk seen in dev round — never parse s-exprs with a
+        # lazy match across closers).
+        exp = defaultdict(set)
+        i = 0
+        while True:
+            i = txt.find("(net\n", i)
+            if i < 0: break
+            depth = 0; j = i; instr = False
+            while j < len(txt):
+                ch = txt[j]
+                if ch == '"' and txt[j-1] != "\\": instr = not instr
+                elif not instr:
+                    if ch == "(": depth += 1
+                    elif ch == ")":
+                        depth -= 1
+                        if depth == 0: break
+                j += 1
+            block = txt[i:j+1]
+            m = re.search(r'\(name "([^"]+)"\)', block)
+            if m:
+                for ref, pin in re.findall(r'ref "([^"]+)"\)\s*\(\s*pin "([^"]+)"', block):
+                    exp[m.group(1)].add(f"{ref}.{pin}")
+            i = j + 1
+        miss = {n for n in got if exp.get(n) != got[n]}
+        extra = set(exp) - set(got)
+        if miss or extra:
+            print(f"FAIL ROUNDTRIP {len(got)-len(miss)}/{len(got)} exact extra_nets={sorted(extra)[:5]}")
+            for n in sorted(miss)[:6]:
+                print("  DIFF", n, "spec-only", sorted(got[n]-exp.get(n, set()))[:3],
+                      "exp-only", sorted(exp.get(n, set())-got[n])[:3])
+            return 1
+        print(f"PASS erc=0/0 nets={len(got)}/{len(got)} exact (members {sum(len(x) for x in got.values())} pins)")
+        return 0
+
+if __name__ == "__main__":
+    sys.exit(main(sys.argv[1], sys.argv[2]))

package/graders/pcb-agent/seed/tools/board_gate_pcb.py

@@ -0,0 +1,23 @@
+#!/usr/bin/env python3
+"""r17 pcb placement gate: kicad-cli DRC must report 0 error-level violations.
+unconnected_items are EXPECTED pre-routing (counted, not failing)."""
+import json, subprocess, sys, os, tempfile
+board = sys.argv[1]
+assert board.endswith(".kicad_pcb")
+pro = board[:-10] + ".kicad_pro"
+if not os.path.exists(pro):
+    print("FAIL no sibling .kicad_pro (design constraints live there)"); sys.exit(1)
+with tempfile.TemporaryDirectory() as td:
+    out = os.path.join(td, "drc.json")
+    r = subprocess.run(["kicad-cli", "pcb", "drc", board, "--format", "json",
+                        "--severity-error", "--output", out], capture_output=True, text=True)
+    if r.returncode or not os.path.exists(out):
+        print(f"FAIL load/drc rc={r.returncode} {r.stderr[:200]}"); sys.exit(1)
+    d = json.load(open(out))
+    v = d.get("violations", [])
+    u = d.get("unconnected_items", [])
+    if v:
+        print(f"FAIL DRC err={len(v)}")
+        for x in v[:8]: print("  ", x.get("description", "")[:100])
+        sys.exit(1)
+    print(f"PASS placement-DRC 0 errors; pending-route unconnected={len(u)}")