@silinx/nextpnr-himbaechel-xc7 0.1.1 → 0.1.2

package/CHANGELOG.md

@@ -4,6 +4,24 @@ Each version is the fork's tag `xc7-v<version>`, its GitHub release (the package
 package. A version's changes are written here before it is tagged. Before 1.0.0 a minor version may change the interface
 the [README](README.md) describes.
 
+## 0.1.2
+
+The LUT pairs (pmnmalo/Silinx#3495) and the JTAG's user access for Silinx's logic analyzer (pmnmalo/Silinx#3767): a
+BSCAN placed on the site of its JTAG chain, a block RAM written on its clock's falling edge timed on that edge.
+
+- Two LUTs of at most five inputs in all, sharing at least one, packed in one site's 6LUT and 5LUT, as Vivado combines
+  them (pmnmalo/Silinx#3495): on Silinx's examples 7-16 % fewer LUTs as Vivado counts them (vga 119 to 106, Vivado's
+  105). The tests' LUTs as Vivado counts them now at most 5 % over Vivado's (15 % before).
+- A cell's BEL attribute that is not an I/O buffer's left to the placer (`pack_io.cc`), which honours it: a BSCAN on the
+  site of its JTAG chain, as Vivado's DRC asks (PDRC-2: the chain n on BSCAN_X0Y<n - 1>), for Silinx's logic analyzer
+  (pmnmalo/Silinx#3767). Before, any cell with a BEL attribute stopped the packer ("Unexpected IOBUF BEL").
+- A clock pin its cell inverts (`IS_<pin>_INVERTED`, an INV that `pack_inverters` folded in: a block RAM written on its
+  clock's falling edge) timed on that edge (`getPortClockingInfo`): before, on the rising one, so a flip-flop on the same
+  clock beside it gave a false hold violation (pmnmalo/Silinx#3767).
+- Tests: `tests/bscan.json.gz` (Silinx's blinky with its capture core on the Basys 3, its BSCAN on BSCAN_X0Y0, its block
+  RAM on the falling edge) placed on its site, routed, no warning (`ci/build-and-test.sh`); blinky, vga and micro80 as
+  before.
+
 ## 0.1.1
 
 The same nextpnr and chip databases as 0.1.0, published again: npm kept 0.1.0 staged when its first, manual publication was not completed, and refuses that version number.

package/gen/bundle.js

@@ -744,7 +744,7 @@ var filesystem = async (fetch3) => {
     "share": await new Blob(chunks).arrayBuffer().then(unpackTarFilesystem)
   };
 };
-var totalSize = 2427302;
+var totalSize = 2432875;
 
 // gen/nextpnr-himbaechel-xilinx.js
 function instantiate(getCoreModule, imports, instantiateCore = WebAssembly.instantiate) {
@@ -10661,7 +10661,7 @@ var runNextpnrHimbaechelXilinx = nextpnrHimbaechelXilinx.run.bind(nextpnrHimbaec
 var commands = {
   "nextpnr-himbaechel-xilinx": runNextpnrHimbaechelXilinx
 };
-var version = "0.1.1";
+var version = "0.1.2";
 var devices = ["xc7a50t", "xc7a100t"];
 var fabricOf = { xc7a35t: "xc7a50t" };
 function deviceOf(part) {

package/package.json

@@ -1,6 +1,6 @@
 {
   "name": "@silinx/nextpnr-himbaechel-xc7",
-  "version": "0.1.1",
+  "version": "0.1.2",
   "description": "nextpnr-himbaechel with the Xilinx 7-series (xilinx, on Project X-Ray's database), in WebAssembly, for Silinx ISE",
   "license": "ISC",
   "homepage": "https://github.com/pmnmalo/nextpnr-spartan",