@salang/sa 0.1.2 → 0.1.4

package/sa_std/sync/atomic.sal

@@ -0,0 +1,45 @@
+#def AtomicBool_SIZE = 1
+#def AtomicBool_value = +0
+
+#def AtomicU8_SIZE = 1
+#def AtomicU8_value = +0
+
+#def AtomicI8_SIZE = 1
+#def AtomicI8_value = +0
+
+#def AtomicU16_SIZE = 2
+#def AtomicU16_value = +0
+
+#def AtomicI16_SIZE = 2
+#def AtomicI16_value = +0
+
+#def AtomicU32_SIZE = 4
+#def AtomicU32_value = +0
+
+#def AtomicI32_SIZE = 4
+#def AtomicI32_value = +0
+
+#def AtomicU64_SIZE = 8
+#def AtomicU64_value = +0
+
+#def AtomicI64_SIZE = 8
+#def AtomicI64_value = +0
+
+#def AtomicUsize_SIZE = 8
+#def AtomicUsize_value = +0
+
+#def AtomicIsize_SIZE = 8
+#def AtomicIsize_value = +0
+
+#def AtomicPtr_SIZE = 8
+#def AtomicPtr_value = +0
+
+#def AtomicOrdering_SIZE = 1
+#def AtomicOrdering_ALIGN = 1
+#def AtomicOrdering_value = +0
+
+#def ATOMIC_ORDERING_RELAXED = 0
+#def ATOMIC_ORDERING_RELEASE = 1
+#def ATOMIC_ORDERING_ACQUIRE = 2
+#def ATOMIC_ORDERING_ACQ_REL = 3
+#def ATOMIC_ORDERING_SEQ_CST = 4

package/sa_std/sync/barrier.sa

@@ -0,0 +1,105 @@
+// Concrete Barrier subset: wait until N waiters arrive, then release.
+// Spin/backoff based (no OS futex). Leader = last waiter to arrive.
+// Scope: single-generation spin barrier for concrete N; not full Rust generation object.
+@import "barrier.sal"
+@import "../time.sai"
+
+@__barrier_wait_spin(barrier: ptr) -> u64:
+L_ENTRY:
+    n = load barrier+Barrier_n as u64
+    prev = atomic_rmw_add barrier+Barrier_count, 1 as u64 seq_cst
+    arrived = add prev, 1
+    is_leader = eq arrived, n
+    br is_leader -> L_LEADER, L_FOLLOWER
+
+L_LEADER:
+    atomic_store barrier+Barrier_count, 0 as u64 seq_cst
+    !barrier
+    !arrived
+    !prev
+    !n
+    return 1
+
+L_FOLLOWER:
+    backoff_slot = stack_alloc 8
+    store backoff_slot+0, 1 as u64
+    arrived_slot = stack_alloc 8
+    store arrived_slot+0, arrived as u64
+    !arrived
+    !prev
+    !n
+    jmp L_SPIN
+
+L_SPIN:
+    cur = atomic_load barrier+Barrier_count as u64 acquire
+    // Leader reset count to 0, or a new generation started below our marker.
+    done = eq cur, 0
+    br done -> L_FOLLOWER_DONE, L_CHECK_GEN
+
+L_CHECK_GEN:
+    arrived_v = load arrived_slot+0 as u64
+    still_waiting = uge cur, arrived_v
+    !arrived_v
+    br still_waiting -> L_BACKOFF, L_FOLLOWER_DONE
+
+L_BACKOFF:
+    backoff_ns = load backoff_slot+0 as u64
+    call @sa_time_sleep_ns(backoff_ns)
+    at_limit = uge backoff_ns, 1024
+    br at_limit -> L_KEEP, L_GROW
+
+L_GROW:
+    next_backoff = shl backoff_ns, 1
+    store backoff_slot+0, next_backoff as u64
+    !next_backoff
+    !at_limit
+    !backoff_ns
+    !still_waiting
+    !done
+    !cur
+    jmp L_SPIN
+
+L_KEEP:
+    !at_limit
+    !backoff_ns
+    !still_waiting
+    !done
+    !cur
+    jmp L_SPIN
+
+L_FOLLOWER_DONE:
+    !barrier
+    return 0
+
+[MACRO] BARRIER_NEW %out_barrier, %n
+    %out_barrier = alloc Barrier_SIZE
+    __barrier_n_zero_%out_barrier = eq %n, 0
+    __barrier_n_norm_%out_barrier = add %n, __barrier_n_zero_%out_barrier
+    store %out_barrier+Barrier_n, __barrier_n_norm_%out_barrier as u64
+    store %out_barrier+Barrier_count, 0 as u64
+    !__barrier_n_norm_%out_barrier
+    !__barrier_n_zero_%out_barrier
+[END_MACRO]
+
+[MACRO] BARRIER_WAIT %out_is_leader, %barrier_reg
+    %out_is_leader = call @__barrier_wait_spin(%barrier_reg)
+[END_MACRO]
+
+[MACRO] BARRIER_N %out_n, %barrier_reg
+    %out_n = load %barrier_reg+Barrier_n as u64
+[END_MACRO]
+
+[MACRO] BARRIER_DEFAULT %out_barrier
+    EXPAND BARRIER_NEW %out_barrier, 2
+[END_MACRO]
+
+[MACRO] BARRIER_WAIT_RESULT %out_result, %barrier_reg
+    %out_result = alloc BarrierWaitResult_SIZE
+    __bw_leader_%out_result = call @__barrier_wait_spin(%barrier_reg)
+    store %out_result+BarrierWaitResult_is_leader, __bw_leader_%out_result as u64
+    !__bw_leader_%out_result
+[END_MACRO]
+
+[MACRO] BARRIER_WAIT_RESULT_IS_LEADER %out_bool, %result_reg
+    %out_bool = load %result_reg+BarrierWaitResult_is_leader as u64
+[END_MACRO]

package/sa_std/sync/barrier.sal

@@ -0,0 +1,7 @@
+// Concrete Barrier facade for N waiters (single-generation spin barrier).
+#def Barrier_SIZE = 16
+#def Barrier_n = +0
+#def Barrier_count = +8
+
+#def BarrierWaitResult_SIZE = 8
+#def BarrierWaitResult_is_leader = +0

package/sa_std/sync/condvar.sa

@@ -0,0 +1,240 @@
+// Concrete Condvar subset: notify_one/notify_all + wait with Mutex.
+// Spin/backoff based. Single-thread wait_while(false) is non-blocking.
+@import "condvar.sal"
+@import "mutex.sal"
+@import "mutex.sa"
+@import "../time.sa"
+@import "../time.sai"
+
+@__condvar_dec_waiter(cond: ptr) -> u64:
+L_ENTRY:
+    waiters = atomic_load cond+Condvar_waiters as u64 acquire
+    has_waiter = ne waiters, 0
+    br has_waiter -> L_CLAIM, L_EMPTY
+L_CLAIM:
+    next_waiters = sub waiters, 1
+    old_waiters, released = cmpxchg cond+Condvar_waiters, waiters, next_waiters as u64 seq_cst seq_cst
+    br released -> L_DONE, L_RETRY
+L_RETRY:
+    !old_waiters
+    !next_waiters
+    !released
+    !has_waiter
+    !waiters
+    jmp L_ENTRY
+L_EMPTY:
+    !has_waiter
+    !waiters
+    return 0
+L_DONE:
+    !old_waiters
+    !next_waiters
+    !released
+    !has_waiter
+    !waiters
+    return 1
+@__condvar_wait_spin(cond: ptr, mutex: ptr) -> void:
+L_ENTRY:
+    old_waiters = atomic_rmw_add cond+Condvar_waiters, 1 as u64 seq_cst
+    !old_waiters
+    atomic_store mutex+Mutex_lock, 0 as u64 release
+    backoff_slot = stack_alloc 8
+    store backoff_slot+0, 1 as u64
+    jmp L_SPIN
+
+L_SPIN:
+    note = atomic_load cond+Condvar_notify as u64 acquire
+    has_note = ne note, 0
+    br has_note -> L_NOTIFIED, L_BACKOFF
+
+L_BACKOFF:
+    backoff_ns = load backoff_slot+0 as u64
+    call @sa_time_sleep_ns(backoff_ns)
+    at_limit = uge backoff_ns, 1024
+    br at_limit -> L_KEEP, L_GROW
+
+L_GROW:
+    next_backoff = shl backoff_ns, 1
+    store backoff_slot+0, next_backoff as u64
+    !next_backoff
+    !at_limit
+    !backoff_ns
+    !has_note
+    !note
+    jmp L_SPIN
+
+L_KEEP:
+    !at_limit
+    !backoff_ns
+    !has_note
+    !note
+    jmp L_SPIN
+
+L_NOTIFIED:
+    prev = atomic_rmw_xchg cond+Condvar_notify, 0 as u64 seq_cst
+    old_w = call @__condvar_dec_waiter(cond)
+    !old_w
+    was_all = ugt prev, 1
+    br was_all -> L_REARM_ALL, L_RELOCK
+
+L_REARM_ALL:
+    atomic_store cond+Condvar_notify, 2 as u64 release
+    jmp L_RELOCK
+
+L_RELOCK:
+    call @__mutex_lock_spin(mutex)
+    !was_all
+    !prev
+    !has_note
+    !note
+    return
+
+[MACRO] CONDVAR_NEW %out_cond
+    %out_cond = alloc Condvar_SIZE
+    store %out_cond+Condvar_waiters, 0 as u64
+    store %out_cond+Condvar_notify, 0 as u64
+[END_MACRO]
+
+[MACRO] CONDVAR_DEFAULT %out_cond
+    EXPAND CONDVAR_NEW %out_cond
+[END_MACRO]
+
+[MACRO] CONDVAR_NOTIFY_ONE %cond_reg
+    atomic_store %cond_reg+Condvar_notify, 1 as u64 release
+[END_MACRO]
+
+[MACRO] CONDVAR_NOTIFY_ALL %cond_reg
+    atomic_store %cond_reg+Condvar_notify, 2 as u64 release
+[END_MACRO]
+
+[MACRO] CONDVAR_WAIT %cond_reg, %mutex_reg
+    call @__condvar_wait_spin(%cond_reg, %mutex_reg)
+[END_MACRO]
+
+[MACRO] CONDVAR_WAIT_WHILE %cond_reg, %mutex_reg, %pred_fn
+    jmp L_COND_WW_HEAD_%cond_reg
+L_COND_WW_HEAD_%cond_reg:
+    __cond_ww_keep_%cond_reg = call %pred_fn(%mutex_reg)
+    __cond_ww_done_%cond_reg = eq __cond_ww_keep_%cond_reg, 0
+    br __cond_ww_done_%cond_reg -> L_COND_WW_DONE_%cond_reg, L_COND_WW_BODY_%cond_reg
+L_COND_WW_BODY_%cond_reg:
+    call @__condvar_wait_spin(%cond_reg, %mutex_reg)
+    !__cond_ww_done_%cond_reg
+    !__cond_ww_keep_%cond_reg
+    jmp L_COND_WW_HEAD_%cond_reg
+L_COND_WW_DONE_%cond_reg:
+    !__cond_ww_done_%cond_reg
+    !__cond_ww_keep_%cond_reg
+[END_MACRO]
+
+[MACRO] CONDVAR_WAITERS %out_count, %cond_reg
+    %out_count = atomic_load %cond_reg+Condvar_waiters as u64 acquire
+[END_MACRO]
+
+// Timed wait: returns 1 if notified, 0 if timeout. Spins with sleep until deadline.
+@__condvar_wait_timeout_ns(cond: ptr, mutex: ptr, timeout_ns: u64) -> u64:
+L_ENTRY:
+    start = call @sa_time_instant_ns()
+    old_waiters = atomic_rmw_add cond+Condvar_waiters, 1 as u64 seq_cst
+    !old_waiters
+    atomic_store mutex+Mutex_lock, 0 as u64 release
+    backoff_slot = stack_alloc 8
+    store backoff_slot+0, 1 as u64
+    jmp L_TO_SPIN
+
+L_TO_SPIN:
+    note = atomic_load cond+Condvar_notify as u64 acquire
+    has_note = ne note, 0
+    br has_note -> L_TO_NOTIFIED, L_TO_CHECK
+
+L_TO_CHECK:
+    now = call @sa_time_instant_ns()
+    elapsed = sub now, start
+    timed_out = uge elapsed, timeout_ns
+    !now
+    !elapsed
+    br timed_out -> L_TO_TIMEOUT, L_TO_BACKOFF
+
+L_TO_BACKOFF:
+    backoff_ns = load backoff_slot+0 as u64
+    call @sa_time_sleep_ns(backoff_ns)
+    at_limit = uge backoff_ns, 1024
+    br at_limit -> L_TO_KEEP, L_TO_GROW
+
+L_TO_GROW:
+    next_backoff = shl backoff_ns, 1
+    store backoff_slot+0, next_backoff as u64
+    !next_backoff
+    !at_limit
+    !backoff_ns
+    !timed_out
+    !has_note
+    !note
+    jmp L_TO_SPIN
+
+L_TO_KEEP:
+    !at_limit
+    !backoff_ns
+    !timed_out
+    !has_note
+    !note
+    jmp L_TO_SPIN
+
+L_TO_TIMEOUT:
+    old_w = call @__condvar_dec_waiter(cond)
+    !old_w
+    call @__mutex_lock_spin(mutex)
+    !timed_out
+    !has_note
+    !note
+    !start
+    !timeout_ns
+    !cond
+    !mutex
+    return 0
+
+L_TO_NOTIFIED:
+    prev = atomic_rmw_xchg cond+Condvar_notify, 0 as u64 seq_cst
+    old_w2 = call @__condvar_dec_waiter(cond)
+    !old_w2
+    was_all = ugt prev, 1
+    br was_all -> L_TO_REARM, L_TO_RELOCK
+
+L_TO_REARM:
+    atomic_store cond+Condvar_notify, 2 as u64 release
+    jmp L_TO_RELOCK
+
+L_TO_RELOCK:
+    call @__mutex_lock_spin(mutex)
+    !was_all
+    !prev
+    !has_note
+    !note
+    !start
+    !timeout_ns
+    !cond
+    !mutex
+    return 1
+
+[MACRO] CONDVAR_WAIT_TIMEOUT_NS %out_notified, %cond_reg, %mutex_reg, %timeout_ns
+    %out_notified = call @__condvar_wait_timeout_ns(%cond_reg, %mutex_reg, %timeout_ns)
+[END_MACRO]
+
+[MACRO] CONDVAR_WAIT_TIMEOUT_MS %out_notified, %cond_reg, %mutex_reg, %timeout_ms
+    EXPAND TIME_CHECKED_MUL_NS __cond_ms_ok_%out_notified, __cond_to_ns_%out_notified, %timeout_ms, Time_NS_PER_MS
+    br __cond_ms_ok_%out_notified -> L_CONDVAR_TIMEOUT_MS_OK_%out_notified, L_CONDVAR_TIMEOUT_MS_OVERFLOW_%out_notified
+L_CONDVAR_TIMEOUT_MS_OK_%out_notified:
+    EXPAND CONDVAR_WAIT_TIMEOUT_NS %out_notified, %cond_reg, %mutex_reg, __cond_to_ns_%out_notified
+    !__cond_to_ns_%out_notified
+    !__cond_ms_ok_%out_notified
+    jmp L_CONDVAR_TIMEOUT_MS_DONE_%out_notified
+L_CONDVAR_TIMEOUT_MS_OVERFLOW_%out_notified:
+    %out_notified = add 0, 0
+    !__cond_to_ns_%out_notified
+    !__cond_ms_ok_%out_notified
+L_CONDVAR_TIMEOUT_MS_DONE_%out_notified:
+[END_MACRO]
+
+[MACRO] CONDVAR_WAIT_TIMEOUT_DURATION_NS %out_notified, %cond_reg, %mutex_reg, %duration_ns
+    EXPAND CONDVAR_WAIT_TIMEOUT_NS %out_notified, %cond_reg, %mutex_reg, %duration_ns
+[END_MACRO]

package/sa_std/sync/condvar.sal

@@ -0,0 +1,4 @@
+// Concrete Condvar facade over spin/backoff notify flags (single-thread testable).
+#def Condvar_SIZE = 16
+#def Condvar_waiters = +0
+#def Condvar_notify = +8