@neovand/zilion 0.1.0

package/LICENSE

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+MIT License
+
+Copyright (c) 2026 NeoVand
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

package/README.md

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+<p align="center">
+  <img src="assets/logo.png" width="160" alt="Zilion logo" />
+</p>
+
+<h1 align="center">Zilion</h1>
+
+<p align="center">
+  <b>A zillion Z80s in parallel, on your GPU.</b><br/>
+  A WebGPU-accelerated, differentially-tested Zilog Z80 emulator for massively parallel batch execution.
+</p>
+
+<p align="center">
+  <a href="https://www.npmjs.com/package/@neovand/zilion"><img alt="npm" src="https://img.shields.io/npm/v/@neovand/zilion?color=FF4D6D"></a>
+  <img alt="license" src="https://img.shields.io/badge/license-MIT-8A5CFF">
+  <img alt="webgpu" src="https://img.shields.io/badge/WebGPU-compute-FFB020">
+  <img alt="types" src="https://img.shields.io/badge/types-TypeScript-3178C6">
+</p>
+
+---
+
+Zilion runs **thousands of independent Z80 CPUs at once** as a single WebGPU compute dispatch — one CPU per GPU thread, each with its own private memory. It was born inside an [artificial-life simulator](#origin) that needed to execute tens of millions of tiny Z80 programs per second, so it is built for **scale**: give it a batch of programs, get back their final memory and registers.
+
+```
+4,096 Z80 programs · 16 instructions each · ~2.5 ms on a laptop GPU
+```
+
+## Why?
+
+CPU emulators run one machine at a time. But a whole class of problems needs to run *many* small Z80 programs independently and cheaply:
+
+- 🧬 **Artificial life & open-ended evolution** — soups of self-modifying machine code (à la [BFF / Computational Life](https://arxiv.org/abs/2406.19108)).
+- 🧠 **Genetic programming** — evaluate an entire population of evolved Z80 programs each generation.
+- 🔎 **Search & fuzzing** — brute-force or randomized exploration of program space.
+- 🕹️ **Batch retro tooling** — run many short ROM snippets or test vectors in parallel.
+
+Zilion turns "run N Z80s" into one GPU dispatch instead of N CPU loops.
+
+## Highlights
+
+- ⚡ **Massively parallel** — one Z80 per GPU invocation, thousands at a time.
+- 🎯 **Correct** — the full documented instruction set plus **IX/IY**, **CB/ED/DDCB/FDCB** prefixes, shadow registers, and undocumented flag behavior. Continuously [differential-tested](#correctness) against a real-Z80 reference emulator.
+- 🧩 **Simple API** — `create` once, `run` batches, read back memory + registers.
+- 🪶 **Zero dependencies**, TypeScript-native, ships as ESM.
+- 🔌 **Bring your own `GPUDevice`** or let Zilion request one.
+
+## Install
+
+```bash
+npm install @neovand/zilion
+```
+
+Requires an environment with [WebGPU](https://caniuse.com/webgpu) (Chrome/Edge 113+, Safari 18+, Firefox 141+, or Node 22+ with a WebGPU backend).
+
+## Quick start
+
+```ts
+import { Zilion } from '@neovand/zilion';
+
+const z80 = await Zilion.create({ memBytes: 256 });
+
+// A tiny program: LD A,0x42 ; INC A ; HALT
+const program = [0x3e, 0x42, 0x3c, 0x76];
+
+const result = await z80.run([program], { steps: 16 });
+
+console.log((result.registers[0].af >> 8).toString(16)); // "43"
+console.log(result.memoryOf(0)); // final 256-byte memory image
+
+z80.destroy();
+```
+
+### Running a batch
+
+Every entry in the array is an independent Z80 with its own memory:
+
+```ts
+// 10,000 random 32-byte programs, 128 instructions each — one dispatch.
+const programs = Array.from({ length: 10_000 }, () =>
+  Uint8Array.from({ length: 32 }, () => (Math.random() * 256) | 0)
+);
+
+const { registers, memory, memoryOf } = await z80.run(programs, { steps: 128 });
+// registers[i], memoryOf(i) → the outcome of program i
+```
+
+### Custom starting registers
+
+```ts
+await z80.run([program], {
+  steps: 64,
+  init: [{ af: 0x4100, bc: 0x0008, sp: 0xfff0 }] // A=0x41, BC=8, SP=0xFFF0
+});
+```
+
+## API
+
+### `Zilion.create(options?)`
+
+```ts
+interface ZilionOptions {
+  memBytes?: number; // memory per program, power of two (default 256)
+  device?: GPUDevice; // provide your own, or Zilion requests one
+}
+```
+
+The Z80's 16-bit address space **wraps** onto `memBytes` (so a program can't escape its instance). Smaller memories mean more programs run concurrently; larger memories reduce GPU occupancy.
+
+### `zilion.run(programs, options)`
+
+```ts
+interface RunOptions {
+  steps: number;            // instructions per program (stops early on HALT)
+  init?: Z80RegisterInit[]; // optional per-program starting registers
+}
+
+interface RunResult {
+  count: number;
+  memBytes: number;
+  memory: Uint8Array;              // flat: count * memBytes
+  registers: Z80Registers[];       // af, bc, de, hl, ix, iy, sp, pc, + shadows
+  memoryOf(i: number): Uint8Array; // program i's final memory
+}
+```
+
+Each program is copied into its instance's memory (zero-padded or truncated to `memBytes`). Registers reset to zero except **SP = 0xFFFF** (a real Z80 reset), unless overridden via `init`.
+
+### `zilion.destroy()`
+
+Releases GPU resources (and the device if Zilion created it).
+
+## How it works
+
+Zilion generates a WGSL compute shader containing a complete Z80 core. Each shader invocation:
+
+1. copies its program into a private in-register memory array,
+2. resets a fresh CPU,
+3. runs the fetch–decode–execute loop for `steps` instructions (or until `HALT`),
+4. writes the final memory and registers back to storage buffers.
+
+`workgroup_size = 64`, dispatched over `ceil(count / 64)` workgroups. Because every CPU is independent, this is embarrassingly parallel — the GPU runs as many as it has lanes for.
+
+## Correctness
+
+Emulator bugs hide in undocumented corners, so Zilion's Z80 core is developed against a **real-Z80 oracle** (a Fuse-lineage reference emulator that passes the `zexall`/`zexdoc` conformance suites). Thousands of random programs are run through both the GPU core and the reference each change, and their final **memory and registers** are compared — catching divergences down to individual instructions.
+
+The core implements the full documented instruction set, the **CB**, **ED**, **DD/FD (IX/IY)**, and **DDCB/FDCB** prefix pages (including the undocumented DDCB register-copy side effect and the CPI/CPD undocumented-flag quirk), shadow registers, and `EXX`/`EX AF,AF'`.
+
+> **Scope & honesty:** Zilion is a batch execution core, not a cycle-accurate machine emulator. There are no interrupts, no I/O ports (`IN` reads 0, `OUT` is a no-op), and no cycle timing — every instruction advances the step counter by one. The `R` refresh register and exact `HALT` idle semantics are approximated. If you need cycle-accurate single-machine emulation, use a dedicated emulator; if you need to run a zillion Z80s fast, use Zilion.
+
+## Performance
+
+One dispatch scales with your GPU, not your program count. As a rough sense of scale, a mid-range laptop GPU runs several thousand 16-instruction programs in a couple of milliseconds. For best throughput, keep `memBytes` small and batch as many programs as you can into a single `run`.
+
+## Origin
+
+Zilion was extracted from **[Algocell](https://github.com/NeoVand/algocell)**, a WebGPU artificial-life simulator where random bytes evolve into self-replicating Z80 machine code. The differential-testing methodology and the correctness fixes that made this core trustworthy came from that project.
+
+## License
+
+[MIT](LICENSE) © NeoVand

package/dist/index.d.ts

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+export { Zilion } from './zilion.js';
+export type { ZilionOptions, RunOptions, RunResult, Z80Registers, Z80RegisterInit } from './zilion.js';
+export { buildComputeShader, REG_FIELDS, REGS_PER_PROGRAM } from './shader.js';
+export { Z80_CORE_WGSL } from './z80-core.wgsl.js';
+//# sourceMappingURL=index.d.ts.map

package/dist/index.d.ts.map

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package/dist/index.js

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+export { Zilion } from './zilion.js';
+export { buildComputeShader, REG_FIELDS, REGS_PER_PROGRAM } from './shader.js';
+export { Z80_CORE_WGSL } from './z80-core.wgsl.js';
+//# sourceMappingURL=index.js.map

package/dist/index.js.map

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package/dist/shader.d.ts

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+export declare const REG_FIELDS: readonly ["af", "bc", "de", "hl", "ix", "iy", "sp", "pc", "afPrime", "bcPrime", "dePrime", "hlPrime"];
+export declare const REGS_PER_PROGRAM: 12;
+/**
+ * Build the full WebGPU compute shader for a batch of Z80 programs, each with
+ * `memBytes` bytes of private memory (must be a power of two). One workgroup
+ * invocation runs one program for `params.steps` instructions.
+ *
+ * Bindings:
+ *   0: uniform  Params { count, mem_bytes, steps, sp_init }
+ *   1: storage  mem     — flat u32 array, memBytes/4 words per program (in+out)
+ *   2: storage  regs    — flat u32 array, REGS_PER_PROGRAM per program (out)
+ *   3: storage  init    — flat u32 array, REGS_PER_PROGRAM per program (in)
+ */
+export declare function buildComputeShader(memBytes: number): string;
+//# sourceMappingURL=shader.d.ts.map

package/dist/shader.d.ts.map

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package/dist/shader.js

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+import { Z80_CORE_WGSL } from './z80-core.wgsl.js';
+// Registers written back per program (16-bit values), in this fixed order.
+export const REG_FIELDS = [
+    'af',
+    'bc',
+    'de',
+    'hl',
+    'ix',
+    'iy',
+    'sp',
+    'pc',
+    'afPrime',
+    'bcPrime',
+    'dePrime',
+    'hlPrime'
+];
+export const REGS_PER_PROGRAM = REG_FIELDS.length; // 12 u32 per program
+/**
+ * Build the full WebGPU compute shader for a batch of Z80 programs, each with
+ * `memBytes` bytes of private memory (must be a power of two). One workgroup
+ * invocation runs one program for `params.steps` instructions.
+ *
+ * Bindings:
+ *   0: uniform  Params { count, mem_bytes, steps, sp_init }
+ *   1: storage  mem     — flat u32 array, memBytes/4 words per program (in+out)
+ *   2: storage  regs    — flat u32 array, REGS_PER_PROGRAM per program (out)
+ *   3: storage  init    — flat u32 array, REGS_PER_PROGRAM per program (in)
+ */
+export function buildComputeShader(memBytes) {
+    if (memBytes < 4 || (memBytes & (memBytes - 1)) !== 0) {
+        throw new Error(`memBytes must be a power of two >= 4 (got ${memBytes})`);
+    }
+    const mask = memBytes - 1;
+    return /* wgsl */ `
+struct Params {
+	count: u32,
+	mem_bytes: u32,
+	steps: u32,
+	_pad: u32,
+};
+@group(0) @binding(0) var<uniform> params: Params;
+@group(0) @binding(1) var<storage, read_write> mem_io: array<u32>;
+@group(0) @binding(2) var<storage, read_write> regs_out: array<u32>;
+@group(0) @binding(3) var<storage, read> regs_in: array<u32>;
+
+// --- Host contract for the Z80 core (see z80-core.wgsl.ts) ---
+// Per-instance memory: one byte per u32 slot in a private array. The 16-bit
+// address space wraps onto memBytes (a power of two) via a mask.
+var<private> mem: array<u32, ${memBytes}u>;
+fn mem_read(addr: u32) -> u32 { return mem[addr & ${mask}u]; }
+fn mem_write(addr: u32, val: u32) { mem[addr & ${mask}u] = val & 0xffu; }
+fn on_fetch_opcode(op: u32) -> bool { return false; } // no suppression by default
+
+${Z80_CORE_WGSL}
+
+fn get16(base: u32, idx: u32) -> u32 { return regs_in[base + idx] & 0xffffu; }
+
+@compute @workgroup_size(64)
+fn main(@builtin(global_invocation_id) gid: vec3u) {
+	let id = gid.x;
+	if (id >= params.count) { return; }
+
+	let words = params.mem_bytes >> 2u;
+	let mbase = id * words;
+
+	// Load this program's memory into the private array.
+	for (var i = 0u; i < words; i++) {
+		let w = mem_io[mbase + i];
+		mem[i*4u]      = w & 0xffu;
+		mem[i*4u + 1u] = (w >> 8u) & 0xffu;
+		mem[i*4u + 2u] = (w >> 16u) & 0xffu;
+		mem[i*4u + 3u] = (w >> 24u) & 0xffu;
+	}
+
+	// Initial register state (packed 16-bit values; see REG_FIELDS order).
+	let rb = id * ${REGS_PER_PROGRAM}u;
+	set_af(get16(rb, 0u));
+	set_bc(get16(rb, 1u));
+	set_de(get16(rb, 2u));
+	set_hl(get16(rb, 3u));
+	cpu_ix = get16(rb, 4u);
+	cpu_iy = get16(rb, 5u);
+	cpu_sp = get16(rb, 6u);
+	cpu_pc = get16(rb, 7u);
+	cpu_a2 = (get16(rb, 8u) >> 8u) & 0xffu; cpu_f2 = get16(rb, 8u) & 0xffu;
+	cpu_b2 = (get16(rb, 9u) >> 8u) & 0xffu; cpu_c2 = get16(rb, 9u) & 0xffu;
+	cpu_d2 = (get16(rb, 10u) >> 8u) & 0xffu; cpu_e2 = get16(rb, 10u) & 0xffu;
+	cpu_h2 = (get16(rb, 11u) >> 8u) & 0xffu; cpu_l2 = get16(rb, 11u) & 0xffu;
+	cpu_halted = 0u;
+	cpu_iff1 = 0u; cpu_iff2 = 0u;
+	idx_mode = 0u; idx_disp = 0u; idx_uses_mem = 0u;
+
+	// Run.
+	for (var s = 0u; s < params.steps; s++) {
+		if (cpu_halted != 0u) { break; }
+		z80_step();
+	}
+
+	// Write memory back.
+	for (var i = 0u; i < words; i++) {
+		mem_io[mbase + i] = mem[i*4u] | (mem[i*4u + 1u] << 8u) | (mem[i*4u + 2u] << 16u) | (mem[i*4u + 3u] << 24u);
+	}
+
+	// Write registers back (packed 16-bit).
+	regs_out[rb + 0u]  = get_af();
+	regs_out[rb + 1u]  = get_bc();
+	regs_out[rb + 2u]  = get_de();
+	regs_out[rb + 3u]  = get_hl();
+	regs_out[rb + 4u]  = cpu_ix;
+	regs_out[rb + 5u]  = cpu_iy;
+	regs_out[rb + 6u]  = cpu_sp;
+	regs_out[rb + 7u]  = cpu_pc;
+	regs_out[rb + 8u]  = (cpu_a2 << 8u) | cpu_f2;
+	regs_out[rb + 9u]  = (cpu_b2 << 8u) | cpu_c2;
+	regs_out[rb + 10u] = (cpu_d2 << 8u) | cpu_e2;
+	regs_out[rb + 11u] = (cpu_h2 << 8u) | cpu_l2;
+}
+`;
+}
+//# sourceMappingURL=shader.js.map

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package/dist/z80-core.wgsl.d.ts

@@ -0,0 +1,2 @@
+export declare const Z80_CORE_WGSL = "\n// === Z80 CPU State (per invocation) ===\nvar<private> cpu_a: u32;\nvar<private> cpu_f: u32;\nvar<private> cpu_b: u32;\nvar<private> cpu_c: u32;\nvar<private> cpu_d: u32;\nvar<private> cpu_e: u32;\nvar<private> cpu_h: u32;\nvar<private> cpu_l: u32;\nvar<private> cpu_sp: u32;\nvar<private> cpu_pc: u32;\nvar<private> cpu_a2: u32;\nvar<private> cpu_f2: u32;\nvar<private> cpu_b2: u32;\nvar<private> cpu_c2: u32;\nvar<private> cpu_d2: u32;\nvar<private> cpu_e2: u32;\nvar<private> cpu_h2: u32;\nvar<private> cpu_l2: u32;\nvar<private> cpu_halted: u32;\nvar<private> cpu_iff1: u32;\nvar<private> cpu_iff2: u32;\nvar<private> cpu_ix: u32;\nvar<private> cpu_iy: u32;\n// Index-prefix state for the instruction currently executing:\n//   idx_mode: 0 = HL, 1 = IX, 2 = IY\n//   idx_disp: sign-extended displacement for (IX+d)/(IY+d)\n//   idx_uses_mem: 1 when this instruction dereferences (IX+d)/(IY+d), which\n//     means H/L operands are NOT substituted by IXH/IXL (real Z80 rule).\nvar<private> idx_mode: u32;\nvar<private> idx_disp: u32;\nvar<private> idx_uses_mem: u32;\n\n// HOST CONTRACT: the host shader must declare the following BEFORE this core:\n//   fn mem_read(addr: u32) -> u32               // read one byte from memory\n//   fn mem_write(addr: u32, val: u32)           // write one byte to memory\n//   fn on_fetch_opcode(op: u32) -> bool         // return true to skip (NOP) an\n//                                               // opcode after prefix resolution\n// This lets the host choose the memory model (mask, modulo, storage buffer, \u2026)\n// and hook opcode execution (e.g. instruction suppression). See buildComputeShader.\n\n// Z80 flag bits\nconst CF: u32 = 0x01u;\nconst NF: u32 = 0x02u;\nconst PF: u32 = 0x04u;\nconst F3: u32 = 0x08u;\nconst HF: u32 = 0x10u;\nconst F5: u32 = 0x20u;\nconst ZF: u32 = 0x40u;\nconst SFl: u32 = 0x80u;\n\n\nfn z80_fetch() -> u32 {\n    let val = mem_read(cpu_pc);\n    cpu_pc = (cpu_pc + 1u) & 0xffffu;\n    return val;\n}\n\nfn z80_fetch_word() -> u32 {\n    let lo = z80_fetch();\n    let hi = z80_fetch();\n    return (hi << 8u) | lo;\n}\n\nfn z80_push16(val: u32) {\n    cpu_sp = (cpu_sp - 1u) & 0xffffu;\n    mem_write(cpu_sp, (val >> 8u) & 0xffu);\n    cpu_sp = (cpu_sp - 1u) & 0xffffu;\n    mem_write(cpu_sp, val & 0xffu);\n}\n\nfn z80_pop16() -> u32 {\n    let lo = mem_read(cpu_sp);\n    cpu_sp = (cpu_sp + 1u) & 0xffffu;\n    let hi = mem_read(cpu_sp);\n    cpu_sp = (cpu_sp + 1u) & 0xffffu;\n    return (hi << 8u) | lo;\n}\n\nfn signed_byte(b: u32) -> i32 {\n    let sb = i32(b);\n    if (sb > 127) { return sb - 256; }\n    return sb;\n}\n\n// === Register Access ===\nfn get_bc() -> u32 { return (cpu_b << 8u) | cpu_c; }\nfn get_de() -> u32 { return (cpu_d << 8u) | cpu_e; }\nfn get_hl() -> u32 { return (cpu_h << 8u) | cpu_l; }\nfn get_af() -> u32 { return (cpu_a << 8u) | cpu_f; }\n\nfn set_bc(v: u32) { cpu_b = (v >> 8u) & 0xffu; cpu_c = v & 0xffu; }\nfn set_de(v: u32) { cpu_d = (v >> 8u) & 0xffu; cpu_e = v & 0xffu; }\nfn set_hl(v: u32) { cpu_h = (v >> 8u) & 0xffu; cpu_l = v & 0xffu; }\nfn set_af(v: u32) { cpu_a = (v >> 8u) & 0xffu; cpu_f = v & 0xffu; }\n\nfn get_reg(idx: u32) -> u32 {\n    switch(idx) {\n        case 0u: { return cpu_b; }\n        case 1u: { return cpu_c; }\n        case 2u: { return cpu_d; }\n        case 3u: { return cpu_e; }\n        case 4u: {\n            if (idx_mode != 0u && idx_uses_mem == 0u) { return (idx_reg16() >> 8u) & 0xffu; } // IXH/IYH\n            return cpu_h;\n        }\n        case 5u: {\n            if (idx_mode != 0u && idx_uses_mem == 0u) { return idx_reg16() & 0xffu; } // IXL/IYL\n            return cpu_l;\n        }\n        case 6u: { return mem_read(idx_addr()); }\n        case 7u: { return cpu_a; }\n        default: { return 0u; }\n    }\n}\n\nfn set_reg(idx: u32, val: u32) {\n    let v = val & 0xffu;\n    switch(idx) {\n        case 0u: { cpu_b = v; }\n        case 1u: { cpu_c = v; }\n        case 2u: { cpu_d = v; }\n        case 3u: { cpu_e = v; }\n        case 4u: {\n            if (idx_mode != 0u && idx_uses_mem == 0u) { set_idx_reg16((idx_reg16() & 0x00ffu) | (v << 8u)); }\n            else { cpu_h = v; }\n        }\n        case 5u: {\n            if (idx_mode != 0u && idx_uses_mem == 0u) { set_idx_reg16((idx_reg16() & 0xff00u) | v); }\n            else { cpu_l = v; }\n        }\n        case 6u: { mem_write(idx_addr(), v); }\n        case 7u: { cpu_a = v; }\n        default: {}\n    }\n}\n\nfn get_reg16(idx: u32) -> u32 {\n    switch(idx) {\n        case 0u: { return get_bc(); }\n        case 1u: { return get_de(); }\n        case 2u: { return idx_reg16(); } // HL / IX / IY\n        case 3u: { return cpu_sp; }\n        default: { return 0u; }\n    }\n}\n\nfn set_reg16(idx: u32, val: u32) {\n    let v = val & 0xffffu;\n    switch(idx) {\n        case 0u: { set_bc(v); }\n        case 1u: { set_de(v); }\n        case 2u: { set_idx_reg16(v); } // HL / IX / IY\n        case 3u: { cpu_sp = v; }\n        default: {}\n    }\n}\n\nfn get_reg16_af(idx: u32) -> u32 {\n    if (idx == 3u) { return get_af(); }\n    return get_reg16(idx);\n}\n\nfn set_reg16_af(idx: u32, val: u32) {\n    if (idx == 3u) { set_af(val); } else { set_reg16(idx, val); }\n}\n\n// === Index register (IX/IY) helpers ===\n// The 16-bit register the current prefix maps HL to (HL itself when no prefix).\nfn idx_reg16() -> u32 {\n    if (idx_mode == 1u) { return cpu_ix; }\n    if (idx_mode == 2u) { return cpu_iy; }\n    return get_hl();\n}\nfn set_idx_reg16(v: u32) {\n    if (idx_mode == 1u) { cpu_ix = v & 0xffffu; }\n    else if (idx_mode == 2u) { cpu_iy = v & 0xffffu; }\n    else { set_hl(v); }\n}\n// Address used for (HL) / (IX+d) / (IY+d).\nfn idx_addr() -> u32 {\n    if (idx_mode != 0u) { return (idx_reg16() + idx_disp) & 0xffffu; }\n    return get_hl();\n}\n// Sign-extend a displacement byte to 16 bits (two's complement).\nfn signext(b: u32) -> u32 {\n    if (b >= 0x80u) { return b | 0xff00u; }\n    return b;\n}\n// Does this main opcode dereference (HL)? (Determines displacement fetch and\n// whether H/L operands are IXH/IXL or real H/L under a DD/FD prefix.)\nfn op_uses_hl_mem(op: u32) -> bool {\n    let x = (op >> 6u) & 3u;\n    let y = (op >> 3u) & 7u;\n    let z = op & 7u;\n    if (x == 1u) { return (y == 6u || z == 6u) && !(y == 6u && z == 6u); } // LD r,(HL)/(HL),r (not HALT)\n    if (x == 2u) { return z == 6u; }                                        // ALU A,(HL)\n    if (x == 0u) {\n        if (z == 4u || z == 5u || z == 6u) { return y == 6u; }              // INC/DEC (HL), LD (HL),n\n        return false;\n    }\n    return false;\n}\n// Write a REAL 8-bit register (no IX/IY substitution) \u2014 used by the\n// undocumented DDCB/FDCB register-copy side effect.\nfn set_reg_raw(idx: u32, val: u32) {\n    let v = val & 0xffu;\n    switch(idx) {\n        case 0u: { cpu_b = v; }\n        case 1u: { cpu_c = v; }\n        case 2u: { cpu_d = v; }\n        case 3u: { cpu_e = v; }\n        case 4u: { cpu_h = v; }\n        case 5u: { cpu_l = v; }\n        case 7u: { cpu_a = v; }\n        default: {}\n    }\n}\n\n// === Flag Helpers ===\nfn sz_flags(val: u32) -> u32 {\n    var f = val & SFl;\n    if (val == 0u) { f |= ZF; }\n    f |= val & (F3 | F5);\n    return f;\n}\n\nfn parity(val: u32) -> bool {\n    var p = val;\n    p ^= p >> 4u;\n    p ^= p >> 2u;\n    p ^= p >> 1u;\n    return (p & 1u) == 0u;\n}\n\nfn check_cc(cc: u32) -> bool {\n    switch(cc) {\n        case 0u: { return (cpu_f & ZF) == 0u; }\n        case 1u: { return (cpu_f & ZF) != 0u; }\n        case 2u: { return (cpu_f & CF) == 0u; }\n        case 3u: { return (cpu_f & CF) != 0u; }\n        case 4u: { return (cpu_f & PF) == 0u; }\n        case 5u: { return (cpu_f & PF) != 0u; }\n        case 6u: { return (cpu_f & SFl) == 0u; }\n        case 7u: { return (cpu_f & SFl) != 0u; }\n        default: { return false; }\n    }\n}\n\n// === ALU ===\nfn z80_alu(op: u32, val: u32) {\n    let a = cpu_a;\n    let c = cpu_f & CF;\n    switch(op) {\n        case 0u: { // ADD\n            let r = a + val;\n            cpu_f = sz_flags(r & 0xffu) | select(0u, CF, r > 0xffu) |\n                    ((a ^ val ^ r) & HF) |\n                    select(0u, PF, ((~(a ^ val)) & (a ^ r) & 0x80u) != 0u);\n            cpu_a = r & 0xffu;\n        }\n        case 1u: { // ADC\n            let r = a + val + c;\n            cpu_f = sz_flags(r & 0xffu) | select(0u, CF, r > 0xffu) |\n                    ((a ^ val ^ r) & HF) |\n                    select(0u, PF, ((~(a ^ val)) & (a ^ r) & 0x80u) != 0u);\n            cpu_a = r & 0xffu;\n        }\n        case 2u: { // SUB\n            let r = i32(a) - i32(val);\n            let ru = u32(r) & 0xffu;\n            cpu_f = sz_flags(ru) | NF | select(0u, CF, r < 0) |\n                    ((a ^ val ^ u32(r)) & HF) |\n                    select(0u, PF, (((a ^ val) & (a ^ u32(r))) & 0x80u) != 0u);\n            cpu_a = ru;\n        }\n        case 3u: { // SBC\n            let r = i32(a) - i32(val) - i32(c);\n            let ru = u32(r) & 0xffu;\n            cpu_f = sz_flags(ru) | NF | select(0u, CF, r < 0) |\n                    ((a ^ val ^ u32(r)) & HF) |\n                    select(0u, PF, (((a ^ val) & (a ^ u32(r))) & 0x80u) != 0u);\n            cpu_a = ru;\n        }\n        case 4u: { // AND\n            cpu_a = a & val;\n            cpu_f = sz_flags(cpu_a) | HF | select(0u, PF, parity(cpu_a));\n        }\n        case 5u: { // XOR\n            cpu_a = a ^ val;\n            cpu_f = sz_flags(cpu_a) | select(0u, PF, parity(cpu_a));\n        }\n        case 6u: { // OR\n            cpu_a = a | val;\n            cpu_f = sz_flags(cpu_a) | select(0u, PF, parity(cpu_a));\n        }\n        case 7u: { // CP\n            let r = i32(a) - i32(val);\n            let ru = u32(r) & 0xffu;\n            cpu_f = (ru & SFl) | select(0u, ZF, ru == 0u) | (val & (F3 | F5)) | NF |\n                    select(0u, CF, r < 0) | ((a ^ val ^ u32(r)) & HF) |\n                    select(0u, PF, (((a ^ val) & (a ^ u32(r))) & 0x80u) != 0u);\n        }\n        default: {}\n    }\n}\n\nfn z80_inc8(val: u32) -> u32 {\n    let r = (val + 1u) & 0xffu;\n    cpu_f = (cpu_f & CF) | sz_flags(r) |\n            select(0u, PF, val == 0x7fu) |\n            select(0u, HF, (r & 0x0fu) == 0u);\n    return r;\n}\n\nfn z80_dec8(val: u32) -> u32 {\n    let r = (val - 1u) & 0xffu;\n    cpu_f = (cpu_f & CF) | sz_flags(r) | NF |\n            select(0u, PF, val == 0x80u) |\n            select(0u, HF, (val & 0x0fu) == 0u);\n    return r;\n}\n\nfn z80_add_hl(val: u32) {\n    let hl = idx_reg16(); // ADD HL,rp / ADD IX,rp / ADD IY,rp\n    let r = hl + val;\n    cpu_f = (cpu_f & (SFl | ZF | PF)) |\n            select(0u, CF, r > 0xffffu) |\n            select(0u, HF, ((hl ^ val ^ r) & 0x1000u) != 0u) |\n            ((r >> 8u) & (F3 | F5));\n    set_idx_reg16(r & 0xffffu);\n}\n\n// === Rotate/Shift for accumulator ===\nfn z80_rot_accum(y: u32) {\n    let a = cpu_a;\n    let c = cpu_f & CF;\n    let keep = cpu_f & (SFl | ZF | PF);\n    switch(y) {\n        case 0u: { // RLCA\n            cpu_a = ((a << 1u) | (a >> 7u)) & 0xffu;\n            cpu_f = keep | (a >> 7u) | (cpu_a & (F3 | F5));\n        }\n        case 1u: { // RRCA\n            cpu_a = ((a >> 1u) | (a << 7u)) & 0xffu;\n            cpu_f = keep | (a & 1u) | (cpu_a & (F3 | F5));\n        }\n        case 2u: { // RLA\n            cpu_a = ((a << 1u) | c) & 0xffu;\n            cpu_f = keep | (a >> 7u) | (cpu_a & (F3 | F5));\n        }\n        case 3u: { // RRA\n            cpu_a = ((a >> 1u) | (c << 7u)) & 0xffu;\n            cpu_f = keep | (a & 1u) | (cpu_a & (F3 | F5));\n        }\n        case 4u: { // DAA\n            var correction = 0u;\n            var carry = c;\n            if ((cpu_f & HF) != 0u || (a & 0x0fu) > 9u) { correction |= 0x06u; }\n            if (c != 0u || a > 0x99u) { correction |= 0x60u; carry = 1u; }\n            if ((cpu_f & NF) != 0u) { cpu_a = (a - correction) & 0xffu; }\n            else { cpu_a = (a + correction) & 0xffu; }\n            cpu_f = (cpu_f & NF) | sz_flags(cpu_a) | carry |\n                    ((a ^ cpu_a) & HF) | select(0u, PF, parity(cpu_a));\n        }\n        case 5u: { // CPL\n            cpu_a = (~a) & 0xffu;\n            cpu_f = (cpu_f & (SFl | ZF | PF | CF)) | HF | NF | (cpu_a & (F3 | F5));\n        }\n        case 6u: { // SCF\n            cpu_f = (cpu_f & (SFl | ZF | PF)) | CF | (cpu_a & (F3 | F5));\n        }\n        case 7u: { // CCF\n            cpu_f = (cpu_f & (SFl | ZF | PF)) |\n                    select(0u, HF, c != 0u) |\n                    select(CF, 0u, c != 0u) |\n                    (cpu_a & (F3 | F5));\n        }\n        default: {}\n    }\n}\n\n// === CB Prefix (bit ops, rotates, shifts) ===\nfn z80_cb_rot(op: u32, val: u32) -> u32 {\n    let c = cpu_f & CF;\n    var r = 0u;\n    switch(op) {\n        case 0u: { r = ((val << 1u) | (val >> 7u)) & 0xffu; cpu_f = sz_flags(r) | (val >> 7u) | select(0u, PF, parity(r)); }\n        case 1u: { r = ((val >> 1u) | (val << 7u)) & 0xffu; cpu_f = sz_flags(r) | (val & 1u) | select(0u, PF, parity(r)); }\n        case 2u: { r = ((val << 1u) | c) & 0xffu; cpu_f = sz_flags(r) | (val >> 7u) | select(0u, PF, parity(r)); }\n        case 3u: { r = ((val >> 1u) | (c << 7u)) & 0xffu; cpu_f = sz_flags(r) | (val & 1u) | select(0u, PF, parity(r)); }\n        case 4u: { r = (val << 1u) & 0xffu; cpu_f = sz_flags(r) | (val >> 7u) | select(0u, PF, parity(r)); }\n        case 5u: { r = ((val >> 1u) | (val & 0x80u)) & 0xffu; cpu_f = sz_flags(r) | (val & 1u) | select(0u, PF, parity(r)); }\n        case 6u: { r = ((val << 1u) | 1u) & 0xffu; cpu_f = sz_flags(r) | (val >> 7u) | select(0u, PF, parity(r)); }\n        case 7u: { r = (val >> 1u) & 0xffu; cpu_f = sz_flags(r) | (val & 1u) | select(0u, PF, parity(r)); }\n        default: { r = val; }\n    }\n    return r;\n}\n\nfn z80_exec_cb() {\n    let op = z80_fetch();\n    let x = (op >> 6u) & 3u;\n    let y = (op >> 3u) & 7u;\n    let z = op & 7u;\n    let val = get_reg(z);\n    switch(x) {\n        case 0u: { set_reg(z, z80_cb_rot(y, val)); }\n        case 1u: { // BIT\n            cpu_f = (cpu_f & CF) | HF |\n                    select(0u, ZF | PF, (val & (1u << y)) == 0u) |\n                    select(0u, SFl, y == 7u && (val & 0x80u) != 0u) |\n                    (val & (F3 | F5));\n        }\n        case 2u: { set_reg(z, val & ~(1u << y)); }\n        case 3u: { set_reg(z, val | (1u << y)); }\n        default: {}\n    }\n}\n\n// DDCB / FDCB: operates on (IX+d)/(IY+d). The displacement (idx_disp) has\n// already been fetched. For rot/shift/RES/SET the result is written to memory\n// AND (undocumented) copied to the real register in the low 3 bits unless it is\n// 6. For BIT, the undocumented F3/F5 come from the high byte of the address.\nfn z80_exec_idxcb(cbop: u32) {\n    let addr = (idx_reg16() + idx_disp) & 0xffffu;\n    let cx = (cbop >> 6u) & 3u;\n    let cy = (cbop >> 3u) & 7u;\n    let cz = cbop & 7u;\n    let val = mem_read(addr);\n    switch(cx) {\n        case 0u: {\n            let r = z80_cb_rot(cy, val);\n            mem_write(addr, r);\n            if (cz != 6u) { set_reg_raw(cz, r); }\n        }\n        case 1u: { // BIT n,(IX+d)\n            cpu_f = (cpu_f & CF) | HF |\n                    select(0u, ZF | PF, (val & (1u << cy)) == 0u) |\n                    select(0u, SFl, cy == 7u && (val & 0x80u) != 0u) |\n                    ((addr >> 8u) & (F3 | F5));\n        }\n        case 2u: {\n            let r = val & ~(1u << cy);\n            mem_write(addr, r);\n            if (cz != 6u) { set_reg_raw(cz, r); }\n        }\n        case 3u: {\n            let r = val | (1u << cy);\n            mem_write(addr, r);\n            if (cz != 6u) { set_reg_raw(cz, r); }\n        }\n        default: {}\n    }\n}\n\n// === Block Transfer (ED prefix) ===\nfn z80_ldi() {\n    let val = mem_read(get_hl());\n    mem_write(get_de(), val);\n    set_hl((get_hl() + 1u) & 0xffffu);\n    set_de((get_de() + 1u) & 0xffffu);\n    set_bc((get_bc() - 1u) & 0xffffu);\n    let n = (val + cpu_a) & 0xffu;\n    cpu_f = (cpu_f & (SFl | ZF | CF)) |\n            select(0u, PF, get_bc() != 0u) |\n            (n & F3) | select(0u, F5, (n & 0x02u) != 0u);\n}\n\nfn z80_ldd() {\n    let val = mem_read(get_hl());\n    mem_write(get_de(), val);\n    set_hl((get_hl() - 1u) & 0xffffu);\n    set_de((get_de() - 1u) & 0xffffu);\n    set_bc((get_bc() - 1u) & 0xffffu);\n    let n = (val + cpu_a) & 0xffu;\n    cpu_f = (cpu_f & (SFl | ZF | CF)) |\n            select(0u, PF, get_bc() != 0u) |\n            (n & F3) | select(0u, F5, (n & 0x02u) != 0u);\n}\n\nfn z80_cpi() {\n    let val = mem_read(get_hl());\n    let r = (cpu_a - val) & 0xffu;\n    let hf = (cpu_a ^ val ^ r) & HF;\n    // Undocumented F3/F5 come from n = A-(HL)-HF (bit 3 -> F3, bit 1 -> F5).\n    let n = (r - select(0u, 1u, hf != 0u)) & 0xffu;\n    set_hl((get_hl() + 1u) & 0xffffu);\n    set_bc((get_bc() - 1u) & 0xffffu);\n    cpu_f = (cpu_f & CF) | (r & SFl) | select(0u, ZF, r == 0u) | NF |\n            hf | select(0u, PF, get_bc() != 0u) |\n            (n & F3) | ((n & 0x02u) << 4u);\n}\n\nfn z80_cpd() {\n    let val = mem_read(get_hl());\n    let r = (cpu_a - val) & 0xffu;\n    let hf = (cpu_a ^ val ^ r) & HF;\n    let n = (r - select(0u, 1u, hf != 0u)) & 0xffu;\n    set_hl((get_hl() - 1u) & 0xffffu);\n    set_bc((get_bc() - 1u) & 0xffffu);\n    cpu_f = (cpu_f & CF) | (r & SFl) | select(0u, ZF, r == 0u) | NF |\n            hf | select(0u, PF, get_bc() != 0u) |\n            (n & F3) | ((n & 0x02u) << 4u);\n}\n\n// === ED Prefix ===\nfn z80_exec_ed() {\n    let op = z80_fetch();\n    switch(op) {\n        case 0xa0u: { z80_ldi(); }\n        case 0xa8u: { z80_ldd(); }\n        case 0xb0u: { z80_ldi(); if (get_bc() != 0u) { cpu_pc = (cpu_pc - 2u) & 0xffffu; } } // LDIR\n        case 0xb8u: { z80_ldd(); if (get_bc() != 0u) { cpu_pc = (cpu_pc - 2u) & 0xffffu; } } // LDDR\n        case 0xa1u: { z80_cpi(); }\n        case 0xa9u: { z80_cpd(); }\n        case 0xb1u: { z80_cpi(); if (get_bc() != 0u && (cpu_f & ZF) == 0u) { cpu_pc = (cpu_pc - 2u) & 0xffffu; } }\n        case 0xb9u: { z80_cpd(); if (get_bc() != 0u && (cpu_f & ZF) == 0u) { cpu_pc = (cpu_pc - 2u) & 0xffffu; } }\n        // NEG\n        case 0x44u, 0x4cu, 0x54u, 0x5cu, 0x64u, 0x6cu, 0x74u, 0x7cu: {\n            let a = cpu_a; cpu_a = 0u; z80_alu(2u, a);\n        }\n        // RETN/RETI\n        case 0x45u, 0x4du, 0x55u, 0x5du, 0x65u, 0x6du, 0x75u, 0x7du: {\n            cpu_iff1 = cpu_iff2; cpu_pc = z80_pop16();\n        }\n        // LD I,A / LD R,A / LD A,I / LD A,R\n        case 0x47u: {} // LD I,A - no I register in our sim\n        case 0x4fu: {} // LD R,A\n        // LD A,I / LD A,R: I and R are not modelled (treated as 0), so A becomes 0.\n        // Flags: S/Z from the loaded value, PF = IFF2, N/H reset, C preserved.\n        case 0x57u: { cpu_a = 0u; cpu_f = (cpu_f & CF) | sz_flags(0u) | select(0u, PF, cpu_iff2 != 0u); }\n        case 0x5fu: { cpu_a = 0u; cpu_f = (cpu_f & CF) | sz_flags(0u) | select(0u, PF, cpu_iff2 != 0u); }\n        // LD (nn), rr\n        case 0x43u, 0x53u, 0x63u, 0x73u: {\n            let nn = z80_fetch_word();\n            let rp = (op >> 4u) & 3u;\n            let val = get_reg16(rp);\n            mem_write(nn, val & 0xffu);\n            mem_write((nn + 1u) & 0xffffu, (val >> 8u) & 0xffu);\n        }\n        // LD rr, (nn)\n        case 0x4bu, 0x5bu, 0x6bu, 0x7bu: {\n            let nn = z80_fetch_word();\n            let rp = (op >> 4u) & 3u;\n            let lo = mem_read(nn);\n            let hi = mem_read((nn + 1u) & 0xffffu);\n            set_reg16(rp, (hi << 8u) | lo);\n        }\n        // ADC HL, rr\n        case 0x4au, 0x5au, 0x6au, 0x7au: {\n            let rp = (op >> 4u) & 3u;\n            let hl = get_hl();\n            let val = get_reg16(rp);\n            let c = cpu_f & CF;\n            let r = hl + val + c;\n            cpu_f = ((r >> 8u) & SFl) | select(0u, ZF, (r & 0xffffu) == 0u) |\n                    select(0u, HF, ((hl ^ val ^ r) & 0x1000u) != 0u) |\n                    select(0u, PF, ((~(hl ^ val)) & (hl ^ r) & 0x8000u) != 0u) |\n                    select(0u, CF, r > 0xffffu) | ((r >> 8u) & (F3 | F5));\n            set_hl(r & 0xffffu);\n        }\n        // SBC HL, rr\n        case 0x42u, 0x52u, 0x62u, 0x72u: {\n            let rp = (op >> 4u) & 3u;\n            let hl = get_hl();\n            let val = get_reg16(rp);\n            let c = cpu_f & CF;\n            let r = i32(hl) - i32(val) - i32(c);\n            let ru = u32(r) & 0xffffu;\n            cpu_f = ((ru >> 8u) & SFl) | select(0u, ZF, ru == 0u) | NF |\n                    select(0u, HF, ((hl ^ val ^ u32(r)) & 0x1000u) != 0u) |\n                    select(0u, PF, (((hl ^ val) & (hl ^ u32(r))) & 0x8000u) != 0u) |\n                    select(0u, CF, r < 0) | ((ru >> 8u) & (F3 | F5));\n            set_hl(ru);\n        }\n        // RRD\n        case 0x67u: {\n            let m = mem_read(get_hl());\n            mem_write(get_hl(), ((cpu_a << 4u) | (m >> 4u)) & 0xffu);\n            cpu_a = (cpu_a & 0xf0u) | (m & 0x0fu);\n            cpu_f = (cpu_f & CF) | sz_flags(cpu_a) | select(0u, PF, parity(cpu_a));\n        }\n        // RLD\n        case 0x6fu: {\n            let m = mem_read(get_hl());\n            mem_write(get_hl(), ((m << 4u) | (cpu_a & 0x0fu)) & 0xffu);\n            cpu_a = (cpu_a & 0xf0u) | (m >> 4u);\n            cpu_f = (cpu_f & CF) | sz_flags(cpu_a) | select(0u, PF, parity(cpu_a));\n        }\n        // IN r,(C) - simplified, just set to 0\n        case 0x40u, 0x48u, 0x50u, 0x58u, 0x60u, 0x68u, 0x70u, 0x78u: {\n            set_reg((op >> 3u) & 7u, 0u);\n        }\n        default: {} // unknown ED ops = NOP\n    }\n}\n\n// === Main Opcode Execution ===\nfn z80_exec_x0(y: u32, z: u32, p: u32, q: u32) {\n    switch(z) {\n        case 0u: {\n            switch(y) {\n                case 0u: {} // NOP\n                case 1u: { // EX AF,AF'\n                    var t = cpu_a; cpu_a = cpu_a2; cpu_a2 = t;\n                    t = cpu_f; cpu_f = cpu_f2; cpu_f2 = t;\n                }\n                case 2u: { // DJNZ\n                    let d = signed_byte(z80_fetch());\n                    cpu_b = (cpu_b - 1u) & 0xffu;\n                    if (cpu_b != 0u) { cpu_pc = u32(i32(cpu_pc) + d) & 0xffffu; }\n                }\n                case 3u: { // JR\n                    let d = signed_byte(z80_fetch());\n                    cpu_pc = u32(i32(cpu_pc) + d) & 0xffffu;\n                }\n                default: { // JR cc (y-4)\n                    let d = signed_byte(z80_fetch());\n                    if (check_cc(y - 4u)) { cpu_pc = u32(i32(cpu_pc) + d) & 0xffffu; }\n                }\n            }\n        }\n        case 1u: {\n            if (q == 0u) { set_reg16(p, z80_fetch_word()); }\n            else { z80_add_hl(get_reg16(p)); }\n        }\n        case 2u: {\n            if (q == 0u) {\n                switch(p) {\n                    case 0u: { mem_write(get_bc(), cpu_a); }\n                    case 1u: { mem_write(get_de(), cpu_a); }\n                    case 2u: { let nn = z80_fetch_word(); let hl = idx_reg16(); mem_write(nn, hl & 0xffu); mem_write((nn+1u) & 0xffffu, (hl >> 8u) & 0xffu); }\n                    case 3u: { mem_write(z80_fetch_word(), cpu_a); }\n                    default: {}\n                }\n            } else {\n                switch(p) {\n                    case 0u: { cpu_a = mem_read(get_bc()); }\n                    case 1u: { cpu_a = mem_read(get_de()); }\n                    case 2u: { let nn = z80_fetch_word(); let lo = mem_read(nn); let hi = mem_read((nn+1u) & 0xffffu); set_idx_reg16((hi << 8u) | lo); }\n                    case 3u: { cpu_a = mem_read(z80_fetch_word()); }\n                    default: {}\n                }\n            }\n        }\n        case 3u: {\n            if (q == 0u) { set_reg16(p, (get_reg16(p) + 1u) & 0xffffu); }\n            else { set_reg16(p, (get_reg16(p) - 1u) & 0xffffu); }\n        }\n        case 4u: { set_reg(y, z80_inc8(get_reg(y))); }\n        case 5u: { set_reg(y, z80_dec8(get_reg(y))); }\n        case 6u: { set_reg(y, z80_fetch()); }\n        case 7u: { z80_rot_accum(y); }\n        default: {}\n    }\n}\n\nfn z80_exec_x3(y: u32, z: u32, p: u32, q: u32) {\n    switch(z) {\n        case 0u: { if (check_cc(y)) { cpu_pc = z80_pop16(); } }\n        case 1u: {\n            if (q == 0u) { set_reg16_af(p, z80_pop16()); }\n            else {\n                switch(p) {\n                    case 0u: { cpu_pc = z80_pop16(); } // RET\n                    case 1u: { // EXX\n                        var t = cpu_b; cpu_b = cpu_b2; cpu_b2 = t;\n                        t = cpu_c; cpu_c = cpu_c2; cpu_c2 = t;\n                        t = cpu_d; cpu_d = cpu_d2; cpu_d2 = t;\n                        t = cpu_e; cpu_e = cpu_e2; cpu_e2 = t;\n                        t = cpu_h; cpu_h = cpu_h2; cpu_h2 = t;\n                        t = cpu_l; cpu_l = cpu_l2; cpu_l2 = t;\n                    }\n                    case 2u: { cpu_pc = idx_reg16(); } // JP (HL)/(IX)/(IY)\n                    case 3u: { cpu_sp = idx_reg16(); } // LD SP,HL/IX/IY\n                    default: {}\n                }\n            }\n        }\n        case 2u: { let nn = z80_fetch_word(); if (check_cc(y)) { cpu_pc = nn; } }\n        case 3u: {\n            switch(y) {\n                case 0u: { cpu_pc = z80_fetch_word(); } // JP nn\n                case 1u: { z80_exec_cb(); }\n                case 2u: { z80_fetch(); } // OUT (n),A - no I/O device, discard (matches zff outPort no-op)\n                case 3u: { z80_fetch(); cpu_a = 0u; } // IN A,(n) - no I/O device, reads 0 (matches zff inPort\u21920)\n                case 4u: { // EX (SP),HL / EX (SP),IX / EX (SP),IY\n                    let lo = mem_read(cpu_sp);\n                    let hi = mem_read((cpu_sp + 1u) & 0xffffu);\n                    let hl = idx_reg16();\n                    mem_write(cpu_sp, hl & 0xffu);\n                    mem_write((cpu_sp + 1u) & 0xffffu, (hl >> 8u) & 0xffu);\n                    set_idx_reg16((hi << 8u) | lo);\n                }\n                case 5u: { // EX DE,HL\n                    let td = cpu_d; let te = cpu_e;\n                    cpu_d = cpu_h; cpu_e = cpu_l;\n                    cpu_h = td; cpu_l = te;\n                }\n                case 6u: { cpu_iff1 = 0u; cpu_iff2 = 0u; }\n                case 7u: { cpu_iff1 = 1u; cpu_iff2 = 1u; }\n                default: {}\n            }\n        }\n        case 4u: { let nn = z80_fetch_word(); if (check_cc(y)) { z80_push16(cpu_pc); cpu_pc = nn; } }\n        case 5u: {\n            if (q == 0u) { z80_push16(get_reg16_af(p)); }\n            else {\n                switch(p) {\n                    case 0u: { let nn = z80_fetch_word(); z80_push16(cpu_pc); cpu_pc = nn; } // CALL nn\n                    case 1u, 3u: {} // DD/FD prefix handled in z80_step\n                    case 2u: { z80_exec_ed(); }\n                    default: {}\n                }\n            }\n        }\n        case 6u: { z80_alu(y, z80_fetch()); }\n        case 7u: { z80_push16(cpu_pc); cpu_pc = y * 8u; } // RST\n        default: {}\n    }\n}\n\nfn z80_execute(op: u32) {\n    let x = (op >> 6u) & 3u;\n    let y = (op >> 3u) & 7u;\n    let z = op & 7u;\n    let p = (y >> 1u) & 3u;\n    let q = y & 1u;\n    switch(x) {\n        case 0u: { z80_exec_x0(y, z, p, q); }\n        case 1u: {\n            if (y == 6u && z == 6u) { cpu_halted = 1u; }\n            else { set_reg(y, get_reg(z)); }\n        }\n        case 2u: { z80_alu(y, get_reg(z)); }\n        case 3u: { z80_exec_x3(y, z, p, q); }\n        default: {}\n    }\n}\n\nfn z80_step() {\n    if (cpu_halted != 0u) { return; }\n    // Reset per-instruction index-prefix state.\n    idx_mode = 0u;\n    idx_uses_mem = 0u;\n    idx_disp = 0u;\n\n    var op = z80_fetch();\n    // A DD/FD prefix selects IX/IY for the following opcode.\n    if (op == 0xddu || op == 0xfdu) {\n        idx_mode = select(2u, 1u, op == 0xddu);\n        let next = z80_fetch();\n        // A prefix immediately followed by another prefix or ED is a wasted M1:\n        // this step consumes just the prefix; back up so the next step restarts\n        // at the following byte (matches real Z80 timing and avoids an\n        // unbounded fetch loop on all-prefix programs).\n        if (next == 0xddu || next == 0xfdu || next == 0xedu) {\n            cpu_pc = (cpu_pc - 1u) & 0xffffu;\n            return;\n        }\n        op = next;\n    }\n\n    // Host hook: skip execution (treat as NOP) if requested.\n    if (on_fetch_opcode(op)) { return; }\n\n    if (idx_mode != 0u) {\n        if (op == 0xcbu) {\n            // DDCB/FDCB: displacement precedes the CB opcode.\n            idx_disp = signext(z80_fetch());\n            let cbop = z80_fetch();\n            z80_exec_idxcb(cbop);\n            return;\n        }\n        if (op_uses_hl_mem(op)) {\n            idx_uses_mem = 1u;\n            idx_disp = signext(z80_fetch());\n        }\n    }\n    z80_execute(op);\n}\n";
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package/dist/z80-core.wgsl.d.ts.map

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