@nativescript/visionos 8.7.1 → 8.8.1

package/framework/internal/metadata-generator-arm64/bin/lib/clang/17/include/riscv_vector.h

@@ -0,0 +1,400 @@
+/*===---- riscv_vector.h - RISC-V V-extension RVVIntrinsics -------------------===
+ *
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===-----------------------------------------------------------------------===
+ */
+
+#ifndef __RISCV_VECTOR_H
+#define __RISCV_VECTOR_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#ifndef __riscv_vector
+#error "Vector intrinsics require the vector extension."
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#pragma clang riscv intrinsic vector
+
+
+enum __RISCV_FRM {
+  __RISCV_FRM_RNE = 0,
+  __RISCV_FRM_RTZ = 1,
+  __RISCV_FRM_RDN = 2,
+  __RISCV_FRM_RUP = 3,
+  __RISCV_FRM_RMM = 4,
+};
+
+#define __riscv_vlenb() __builtin_rvv_vlenb()
+
+#define __riscv_vsetvl_e8mf4(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 6)
+#define __riscv_vsetvl_e8mf2(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 7)
+#define __riscv_vsetvl_e8m1(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 0)
+#define __riscv_vsetvl_e8m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 1)
+#define __riscv_vsetvl_e8m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 2)
+#define __riscv_vsetvl_e8m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 3)
+
+#define __riscv_vsetvl_e16mf2(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 7)
+#define __riscv_vsetvl_e16m1(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 0)
+#define __riscv_vsetvl_e16m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 1)
+#define __riscv_vsetvl_e16m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 2)
+#define __riscv_vsetvl_e16m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 3)
+
+#define __riscv_vsetvl_e32m1(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 0)
+#define __riscv_vsetvl_e32m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 1)
+#define __riscv_vsetvl_e32m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 2)
+#define __riscv_vsetvl_e32m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 3)
+
+#if __riscv_v_elen >= 64
+#define __riscv_vsetvl_e8mf8(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 5)
+#define __riscv_vsetvl_e16mf4(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 6)
+#define __riscv_vsetvl_e32mf2(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 7)
+
+#define __riscv_vsetvl_e64m1(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 0)
+#define __riscv_vsetvl_e64m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 1)
+#define __riscv_vsetvl_e64m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 2)
+#define __riscv_vsetvl_e64m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 3, 3)
+#endif
+
+#define __riscv_vsetvlmax_e8mf4() __builtin_rvv_vsetvlimax(0, 6)
+#define __riscv_vsetvlmax_e8mf2() __builtin_rvv_vsetvlimax(0, 7)
+#define __riscv_vsetvlmax_e8m1() __builtin_rvv_vsetvlimax(0, 0)
+#define __riscv_vsetvlmax_e8m2() __builtin_rvv_vsetvlimax(0, 1)
+#define __riscv_vsetvlmax_e8m4() __builtin_rvv_vsetvlimax(0, 2)
+#define __riscv_vsetvlmax_e8m8() __builtin_rvv_vsetvlimax(0, 3)
+
+#define __riscv_vsetvlmax_e16mf2() __builtin_rvv_vsetvlimax(1, 7)
+#define __riscv_vsetvlmax_e16m1() __builtin_rvv_vsetvlimax(1, 0)
+#define __riscv_vsetvlmax_e16m2() __builtin_rvv_vsetvlimax(1, 1)
+#define __riscv_vsetvlmax_e16m4() __builtin_rvv_vsetvlimax(1, 2)
+#define __riscv_vsetvlmax_e16m8() __builtin_rvv_vsetvlimax(1, 3)
+
+#define __riscv_vsetvlmax_e32m1() __builtin_rvv_vsetvlimax(2, 0)
+#define __riscv_vsetvlmax_e32m2() __builtin_rvv_vsetvlimax(2, 1)
+#define __riscv_vsetvlmax_e32m4() __builtin_rvv_vsetvlimax(2, 2)
+#define __riscv_vsetvlmax_e32m8() __builtin_rvv_vsetvlimax(2, 3)
+
+#if __riscv_v_elen >= 64
+#define __riscv_vsetvlmax_e8mf8() __builtin_rvv_vsetvlimax(0, 5)
+#define __riscv_vsetvlmax_e16mf4() __builtin_rvv_vsetvlimax(1, 6)
+#define __riscv_vsetvlmax_e32mf2() __builtin_rvv_vsetvlimax(2, 7)
+
+#define __riscv_vsetvlmax_e64m1() __builtin_rvv_vsetvlimax(3, 0)
+#define __riscv_vsetvlmax_e64m2() __builtin_rvv_vsetvlimax(3, 1)
+#define __riscv_vsetvlmax_e64m4() __builtin_rvv_vsetvlimax(3, 2)
+#define __riscv_vsetvlmax_e64m8() __builtin_rvv_vsetvlimax(3, 3)
+#endif
+
+
+enum __RISCV_VXRM {
+  __RISCV_VXRM_RNU = 0,
+  __RISCV_VXRM_RNE = 1,
+  __RISCV_VXRM_RDN = 2,
+  __RISCV_VXRM_ROD = 3,
+};
+typedef __rvv_bool64_t vbool64_t;
+typedef __rvv_bool32_t vbool32_t;
+typedef __rvv_bool16_t vbool16_t;
+typedef __rvv_bool8_t vbool8_t;
+typedef __rvv_bool4_t vbool4_t;
+typedef __rvv_bool2_t vbool2_t;
+typedef __rvv_bool1_t vbool1_t;
+typedef __rvv_int8mf8_t vint8mf8_t;
+typedef __rvv_uint8mf8_t vuint8mf8_t;
+typedef __rvv_int8mf8x2_t vint8mf8x2_t;
+typedef __rvv_uint8mf8x2_t vuint8mf8x2_t;
+typedef __rvv_int8mf8x3_t vint8mf8x3_t;
+typedef __rvv_uint8mf8x3_t vuint8mf8x3_t;
+typedef __rvv_int8mf8x4_t vint8mf8x4_t;
+typedef __rvv_uint8mf8x4_t vuint8mf8x4_t;
+typedef __rvv_int8mf8x5_t vint8mf8x5_t;
+typedef __rvv_uint8mf8x5_t vuint8mf8x5_t;
+typedef __rvv_int8mf8x6_t vint8mf8x6_t;
+typedef __rvv_uint8mf8x6_t vuint8mf8x6_t;
+typedef __rvv_int8mf8x7_t vint8mf8x7_t;
+typedef __rvv_uint8mf8x7_t vuint8mf8x7_t;
+typedef __rvv_int8mf8x8_t vint8mf8x8_t;
+typedef __rvv_uint8mf8x8_t vuint8mf8x8_t;
+typedef __rvv_int8mf4_t vint8mf4_t;
+typedef __rvv_uint8mf4_t vuint8mf4_t;
+typedef __rvv_int8mf4x2_t vint8mf4x2_t;
+typedef __rvv_uint8mf4x2_t vuint8mf4x2_t;
+typedef __rvv_int8mf4x3_t vint8mf4x3_t;
+typedef __rvv_uint8mf4x3_t vuint8mf4x3_t;
+typedef __rvv_int8mf4x4_t vint8mf4x4_t;
+typedef __rvv_uint8mf4x4_t vuint8mf4x4_t;
+typedef __rvv_int8mf4x5_t vint8mf4x5_t;
+typedef __rvv_uint8mf4x5_t vuint8mf4x5_t;
+typedef __rvv_int8mf4x6_t vint8mf4x6_t;
+typedef __rvv_uint8mf4x6_t vuint8mf4x6_t;
+typedef __rvv_int8mf4x7_t vint8mf4x7_t;
+typedef __rvv_uint8mf4x7_t vuint8mf4x7_t;
+typedef __rvv_int8mf4x8_t vint8mf4x8_t;
+typedef __rvv_uint8mf4x8_t vuint8mf4x8_t;
+typedef __rvv_int8mf2_t vint8mf2_t;
+typedef __rvv_uint8mf2_t vuint8mf2_t;
+typedef __rvv_int8mf2x2_t vint8mf2x2_t;
+typedef __rvv_uint8mf2x2_t vuint8mf2x2_t;
+typedef __rvv_int8mf2x3_t vint8mf2x3_t;
+typedef __rvv_uint8mf2x3_t vuint8mf2x3_t;
+typedef __rvv_int8mf2x4_t vint8mf2x4_t;
+typedef __rvv_uint8mf2x4_t vuint8mf2x4_t;
+typedef __rvv_int8mf2x5_t vint8mf2x5_t;
+typedef __rvv_uint8mf2x5_t vuint8mf2x5_t;
+typedef __rvv_int8mf2x6_t vint8mf2x6_t;
+typedef __rvv_uint8mf2x6_t vuint8mf2x6_t;
+typedef __rvv_int8mf2x7_t vint8mf2x7_t;
+typedef __rvv_uint8mf2x7_t vuint8mf2x7_t;
+typedef __rvv_int8mf2x8_t vint8mf2x8_t;
+typedef __rvv_uint8mf2x8_t vuint8mf2x8_t;
+typedef __rvv_int8m1_t vint8m1_t;
+typedef __rvv_uint8m1_t vuint8m1_t;
+typedef __rvv_int8m1x2_t vint8m1x2_t;
+typedef __rvv_uint8m1x2_t vuint8m1x2_t;
+typedef __rvv_int8m1x3_t vint8m1x3_t;
+typedef __rvv_uint8m1x3_t vuint8m1x3_t;
+typedef __rvv_int8m1x4_t vint8m1x4_t;
+typedef __rvv_uint8m1x4_t vuint8m1x4_t;
+typedef __rvv_int8m1x5_t vint8m1x5_t;
+typedef __rvv_uint8m1x5_t vuint8m1x5_t;
+typedef __rvv_int8m1x6_t vint8m1x6_t;
+typedef __rvv_uint8m1x6_t vuint8m1x6_t;
+typedef __rvv_int8m1x7_t vint8m1x7_t;
+typedef __rvv_uint8m1x7_t vuint8m1x7_t;
+typedef __rvv_int8m1x8_t vint8m1x8_t;
+typedef __rvv_uint8m1x8_t vuint8m1x8_t;
+typedef __rvv_int8m2_t vint8m2_t;
+typedef __rvv_uint8m2_t vuint8m2_t;
+typedef __rvv_int8m2x2_t vint8m2x2_t;
+typedef __rvv_uint8m2x2_t vuint8m2x2_t;
+typedef __rvv_int8m2x3_t vint8m2x3_t;
+typedef __rvv_uint8m2x3_t vuint8m2x3_t;
+typedef __rvv_int8m2x4_t vint8m2x4_t;
+typedef __rvv_uint8m2x4_t vuint8m2x4_t;
+typedef __rvv_int8m4_t vint8m4_t;
+typedef __rvv_uint8m4_t vuint8m4_t;
+typedef __rvv_int8m4x2_t vint8m4x2_t;
+typedef __rvv_uint8m4x2_t vuint8m4x2_t;
+typedef __rvv_int8m8_t vint8m8_t;
+typedef __rvv_uint8m8_t vuint8m8_t;
+typedef __rvv_int16mf4_t vint16mf4_t;
+typedef __rvv_uint16mf4_t vuint16mf4_t;
+typedef __rvv_int16mf4x2_t vint16mf4x2_t;
+typedef __rvv_uint16mf4x2_t vuint16mf4x2_t;
+typedef __rvv_int16mf4x3_t vint16mf4x3_t;
+typedef __rvv_uint16mf4x3_t vuint16mf4x3_t;
+typedef __rvv_int16mf4x4_t vint16mf4x4_t;
+typedef __rvv_uint16mf4x4_t vuint16mf4x4_t;
+typedef __rvv_int16mf4x5_t vint16mf4x5_t;
+typedef __rvv_uint16mf4x5_t vuint16mf4x5_t;
+typedef __rvv_int16mf4x6_t vint16mf4x6_t;
+typedef __rvv_uint16mf4x6_t vuint16mf4x6_t;
+typedef __rvv_int16mf4x7_t vint16mf4x7_t;
+typedef __rvv_uint16mf4x7_t vuint16mf4x7_t;
+typedef __rvv_int16mf4x8_t vint16mf4x8_t;
+typedef __rvv_uint16mf4x8_t vuint16mf4x8_t;
+typedef __rvv_int16mf2_t vint16mf2_t;
+typedef __rvv_uint16mf2_t vuint16mf2_t;
+typedef __rvv_int16mf2x2_t vint16mf2x2_t;
+typedef __rvv_uint16mf2x2_t vuint16mf2x2_t;
+typedef __rvv_int16mf2x3_t vint16mf2x3_t;
+typedef __rvv_uint16mf2x3_t vuint16mf2x3_t;
+typedef __rvv_int16mf2x4_t vint16mf2x4_t;
+typedef __rvv_uint16mf2x4_t vuint16mf2x4_t;
+typedef __rvv_int16mf2x5_t vint16mf2x5_t;
+typedef __rvv_uint16mf2x5_t vuint16mf2x5_t;
+typedef __rvv_int16mf2x6_t vint16mf2x6_t;
+typedef __rvv_uint16mf2x6_t vuint16mf2x6_t;
+typedef __rvv_int16mf2x7_t vint16mf2x7_t;
+typedef __rvv_uint16mf2x7_t vuint16mf2x7_t;
+typedef __rvv_int16mf2x8_t vint16mf2x8_t;
+typedef __rvv_uint16mf2x8_t vuint16mf2x8_t;
+typedef __rvv_int16m1_t vint16m1_t;
+typedef __rvv_uint16m1_t vuint16m1_t;
+typedef __rvv_int16m1x2_t vint16m1x2_t;
+typedef __rvv_uint16m1x2_t vuint16m1x2_t;
+typedef __rvv_int16m1x3_t vint16m1x3_t;
+typedef __rvv_uint16m1x3_t vuint16m1x3_t;
+typedef __rvv_int16m1x4_t vint16m1x4_t;
+typedef __rvv_uint16m1x4_t vuint16m1x4_t;
+typedef __rvv_int16m1x5_t vint16m1x5_t;
+typedef __rvv_uint16m1x5_t vuint16m1x5_t;
+typedef __rvv_int16m1x6_t vint16m1x6_t;
+typedef __rvv_uint16m1x6_t vuint16m1x6_t;
+typedef __rvv_int16m1x7_t vint16m1x7_t;
+typedef __rvv_uint16m1x7_t vuint16m1x7_t;
+typedef __rvv_int16m1x8_t vint16m1x8_t;
+typedef __rvv_uint16m1x8_t vuint16m1x8_t;
+typedef __rvv_int16m2_t vint16m2_t;
+typedef __rvv_uint16m2_t vuint16m2_t;
+typedef __rvv_int16m2x2_t vint16m2x2_t;
+typedef __rvv_uint16m2x2_t vuint16m2x2_t;
+typedef __rvv_int16m2x3_t vint16m2x3_t;
+typedef __rvv_uint16m2x3_t vuint16m2x3_t;
+typedef __rvv_int16m2x4_t vint16m2x4_t;
+typedef __rvv_uint16m2x4_t vuint16m2x4_t;
+typedef __rvv_int16m4_t vint16m4_t;
+typedef __rvv_uint16m4_t vuint16m4_t;
+typedef __rvv_int16m4x2_t vint16m4x2_t;
+typedef __rvv_uint16m4x2_t vuint16m4x2_t;
+typedef __rvv_int16m8_t vint16m8_t;
+typedef __rvv_uint16m8_t vuint16m8_t;
+typedef __rvv_int32mf2_t vint32mf2_t;
+typedef __rvv_uint32mf2_t vuint32mf2_t;
+typedef __rvv_int32mf2x2_t vint32mf2x2_t;
+typedef __rvv_uint32mf2x2_t vuint32mf2x2_t;
+typedef __rvv_int32mf2x3_t vint32mf2x3_t;
+typedef __rvv_uint32mf2x3_t vuint32mf2x3_t;
+typedef __rvv_int32mf2x4_t vint32mf2x4_t;
+typedef __rvv_uint32mf2x4_t vuint32mf2x4_t;
+typedef __rvv_int32mf2x5_t vint32mf2x5_t;
+typedef __rvv_uint32mf2x5_t vuint32mf2x5_t;
+typedef __rvv_int32mf2x6_t vint32mf2x6_t;
+typedef __rvv_uint32mf2x6_t vuint32mf2x6_t;
+typedef __rvv_int32mf2x7_t vint32mf2x7_t;
+typedef __rvv_uint32mf2x7_t vuint32mf2x7_t;
+typedef __rvv_int32mf2x8_t vint32mf2x8_t;
+typedef __rvv_uint32mf2x8_t vuint32mf2x8_t;
+typedef __rvv_int32m1_t vint32m1_t;
+typedef __rvv_uint32m1_t vuint32m1_t;
+typedef __rvv_int32m1x2_t vint32m1x2_t;
+typedef __rvv_uint32m1x2_t vuint32m1x2_t;
+typedef __rvv_int32m1x3_t vint32m1x3_t;
+typedef __rvv_uint32m1x3_t vuint32m1x3_t;
+typedef __rvv_int32m1x4_t vint32m1x4_t;
+typedef __rvv_uint32m1x4_t vuint32m1x4_t;
+typedef __rvv_int32m1x5_t vint32m1x5_t;
+typedef __rvv_uint32m1x5_t vuint32m1x5_t;
+typedef __rvv_int32m1x6_t vint32m1x6_t;
+typedef __rvv_uint32m1x6_t vuint32m1x6_t;
+typedef __rvv_int32m1x7_t vint32m1x7_t;
+typedef __rvv_uint32m1x7_t vuint32m1x7_t;
+typedef __rvv_int32m1x8_t vint32m1x8_t;
+typedef __rvv_uint32m1x8_t vuint32m1x8_t;
+typedef __rvv_int32m2_t vint32m2_t;
+typedef __rvv_uint32m2_t vuint32m2_t;
+typedef __rvv_int32m2x2_t vint32m2x2_t;
+typedef __rvv_uint32m2x2_t vuint32m2x2_t;
+typedef __rvv_int32m2x3_t vint32m2x3_t;
+typedef __rvv_uint32m2x3_t vuint32m2x3_t;
+typedef __rvv_int32m2x4_t vint32m2x4_t;
+typedef __rvv_uint32m2x4_t vuint32m2x4_t;
+typedef __rvv_int32m4_t vint32m4_t;
+typedef __rvv_uint32m4_t vuint32m4_t;
+typedef __rvv_int32m4x2_t vint32m4x2_t;
+typedef __rvv_uint32m4x2_t vuint32m4x2_t;
+typedef __rvv_int32m8_t vint32m8_t;
+typedef __rvv_uint32m8_t vuint32m8_t;
+typedef __rvv_int64m1_t vint64m1_t;
+typedef __rvv_uint64m1_t vuint64m1_t;
+typedef __rvv_int64m1x2_t vint64m1x2_t;
+typedef __rvv_uint64m1x2_t vuint64m1x2_t;
+typedef __rvv_int64m1x3_t vint64m1x3_t;
+typedef __rvv_uint64m1x3_t vuint64m1x3_t;
+typedef __rvv_int64m1x4_t vint64m1x4_t;
+typedef __rvv_uint64m1x4_t vuint64m1x4_t;
+typedef __rvv_int64m1x5_t vint64m1x5_t;
+typedef __rvv_uint64m1x5_t vuint64m1x5_t;
+typedef __rvv_int64m1x6_t vint64m1x6_t;
+typedef __rvv_uint64m1x6_t vuint64m1x6_t;
+typedef __rvv_int64m1x7_t vint64m1x7_t;
+typedef __rvv_uint64m1x7_t vuint64m1x7_t;
+typedef __rvv_int64m1x8_t vint64m1x8_t;
+typedef __rvv_uint64m1x8_t vuint64m1x8_t;
+typedef __rvv_int64m2_t vint64m2_t;
+typedef __rvv_uint64m2_t vuint64m2_t;
+typedef __rvv_int64m2x2_t vint64m2x2_t;
+typedef __rvv_uint64m2x2_t vuint64m2x2_t;
+typedef __rvv_int64m2x3_t vint64m2x3_t;
+typedef __rvv_uint64m2x3_t vuint64m2x3_t;
+typedef __rvv_int64m2x4_t vint64m2x4_t;
+typedef __rvv_uint64m2x4_t vuint64m2x4_t;
+typedef __rvv_int64m4_t vint64m4_t;
+typedef __rvv_uint64m4_t vuint64m4_t;
+typedef __rvv_int64m4x2_t vint64m4x2_t;
+typedef __rvv_uint64m4x2_t vuint64m4x2_t;
+typedef __rvv_int64m8_t vint64m8_t;
+typedef __rvv_uint64m8_t vuint64m8_t;
+typedef __rvv_float16mf4_t vfloat16mf4_t;
+typedef __rvv_float16mf4x2_t vfloat16mf4x2_t;
+typedef __rvv_float16mf4x3_t vfloat16mf4x3_t;
+typedef __rvv_float16mf4x4_t vfloat16mf4x4_t;
+typedef __rvv_float16mf4x5_t vfloat16mf4x5_t;
+typedef __rvv_float16mf4x6_t vfloat16mf4x6_t;
+typedef __rvv_float16mf4x7_t vfloat16mf4x7_t;
+typedef __rvv_float16mf4x8_t vfloat16mf4x8_t;
+typedef __rvv_float16mf2_t vfloat16mf2_t;
+typedef __rvv_float16mf2x2_t vfloat16mf2x2_t;
+typedef __rvv_float16mf2x3_t vfloat16mf2x3_t;
+typedef __rvv_float16mf2x4_t vfloat16mf2x4_t;
+typedef __rvv_float16mf2x5_t vfloat16mf2x5_t;
+typedef __rvv_float16mf2x6_t vfloat16mf2x6_t;
+typedef __rvv_float16mf2x7_t vfloat16mf2x7_t;
+typedef __rvv_float16mf2x8_t vfloat16mf2x8_t;
+typedef __rvv_float16m1_t vfloat16m1_t;
+typedef __rvv_float16m1x2_t vfloat16m1x2_t;
+typedef __rvv_float16m1x3_t vfloat16m1x3_t;
+typedef __rvv_float16m1x4_t vfloat16m1x4_t;
+typedef __rvv_float16m1x5_t vfloat16m1x5_t;
+typedef __rvv_float16m1x6_t vfloat16m1x6_t;
+typedef __rvv_float16m1x7_t vfloat16m1x7_t;
+typedef __rvv_float16m1x8_t vfloat16m1x8_t;
+typedef __rvv_float16m2_t vfloat16m2_t;
+typedef __rvv_float16m2x2_t vfloat16m2x2_t;
+typedef __rvv_float16m2x3_t vfloat16m2x3_t;
+typedef __rvv_float16m2x4_t vfloat16m2x4_t;
+typedef __rvv_float16m4_t vfloat16m4_t;
+typedef __rvv_float16m4x2_t vfloat16m4x2_t;
+typedef __rvv_float16m8_t vfloat16m8_t;
+typedef __rvv_float32mf2_t vfloat32mf2_t;
+typedef __rvv_float32mf2x2_t vfloat32mf2x2_t;
+typedef __rvv_float32mf2x3_t vfloat32mf2x3_t;
+typedef __rvv_float32mf2x4_t vfloat32mf2x4_t;
+typedef __rvv_float32mf2x5_t vfloat32mf2x5_t;
+typedef __rvv_float32mf2x6_t vfloat32mf2x6_t;
+typedef __rvv_float32mf2x7_t vfloat32mf2x7_t;
+typedef __rvv_float32mf2x8_t vfloat32mf2x8_t;
+typedef __rvv_float32m1_t vfloat32m1_t;
+typedef __rvv_float32m1x2_t vfloat32m1x2_t;
+typedef __rvv_float32m1x3_t vfloat32m1x3_t;
+typedef __rvv_float32m1x4_t vfloat32m1x4_t;
+typedef __rvv_float32m1x5_t vfloat32m1x5_t;
+typedef __rvv_float32m1x6_t vfloat32m1x6_t;
+typedef __rvv_float32m1x7_t vfloat32m1x7_t;
+typedef __rvv_float32m1x8_t vfloat32m1x8_t;
+typedef __rvv_float32m2_t vfloat32m2_t;
+typedef __rvv_float32m2x2_t vfloat32m2x2_t;
+typedef __rvv_float32m2x3_t vfloat32m2x3_t;
+typedef __rvv_float32m2x4_t vfloat32m2x4_t;
+typedef __rvv_float32m4_t vfloat32m4_t;
+typedef __rvv_float32m4x2_t vfloat32m4x2_t;
+typedef __rvv_float32m8_t vfloat32m8_t;
+typedef __rvv_float64m1_t vfloat64m1_t;
+typedef __rvv_float64m1x2_t vfloat64m1x2_t;
+typedef __rvv_float64m1x3_t vfloat64m1x3_t;
+typedef __rvv_float64m1x4_t vfloat64m1x4_t;
+typedef __rvv_float64m1x5_t vfloat64m1x5_t;
+typedef __rvv_float64m1x6_t vfloat64m1x6_t;
+typedef __rvv_float64m1x7_t vfloat64m1x7_t;
+typedef __rvv_float64m1x8_t vfloat64m1x8_t;
+typedef __rvv_float64m2_t vfloat64m2_t;
+typedef __rvv_float64m2x2_t vfloat64m2x2_t;
+typedef __rvv_float64m2x3_t vfloat64m2x3_t;
+typedef __rvv_float64m2x4_t vfloat64m2x4_t;
+typedef __rvv_float64m4_t vfloat64m4_t;
+typedef __rvv_float64m4x2_t vfloat64m4x2_t;
+typedef __rvv_float64m8_t vfloat64m8_t;
+#define __riscv_v_intrinsic_overloading 1
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif // __RISCV_VECTOR_H

package/framework/internal/metadata-generator-arm64/bin/lib/clang/17/include/sha512intrin.h

@@ -0,0 +1,200 @@
+/*===--------------- sha512intrin.h - SHA512 intrinsics -----------------===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===-----------------------------------------------------------------------===
+ */
+
+#ifndef __IMMINTRIN_H
+#error "Never use <sha512intrin.h> directly; include <immintrin.h> instead."
+#endif // __IMMINTRIN_H
+
+#ifndef __SHA512INTRIN_H
+#define __SHA512INTRIN_H
+
+#define __DEFAULT_FN_ATTRS256                                                  \
+  __attribute__((__always_inline__, __nodebug__, __target__("sha512"),         \
+                 __min_vector_width__(256)))
+
+/// This intrinisc is one of the two SHA512 message scheduling instructions.
+///    The intrinsic performs an intermediate calculation for the next four
+///    SHA512 message qwords. The calculated results are stored in \a dst.
+///
+/// \headerfile <immintrin.h>
+///
+/// \code
+/// __m256i _mm256_sha512msg1_epi64(__m256i __A, __m128i __B)
+/// \endcode
+///
+/// This intrinsic corresponds to the \c VSHA512MSG1 instruction.
+///
+/// \param __A
+///    A 256-bit vector of [4 x long long].
+/// \param __B
+///    A 128-bit vector of [2 x long long].
+/// \returns
+///    A 256-bit vector of [4 x long long].
+///
+/// \code{.operation}
+/// DEFINE ROR64(qword, n) {
+/// 	count := n % 64
+/// 	dest := (qword >> count) | (qword << (64 - count))
+/// 	RETURN dest
+/// }
+/// DEFINE SHR64(qword, n) {
+/// 	RETURN qword >> n
+/// }
+/// DEFINE s0(qword):
+/// 	RETURN ROR64(qword,1) ^ ROR64(qword, 8) ^ SHR64(qword, 7)
+/// }
+/// W[4] := __B.qword[0]
+/// W[3] := __A.qword[3]
+/// W[2] := __A.qword[2]
+/// W[1] := __A.qword[1]
+/// W[0] := __A.qword[0]
+/// dst.qword[3] := W[3] + s0(W[4])
+/// dst.qword[2] := W[2] + s0(W[3])
+/// dst.qword[1] := W[1] + s0(W[2])
+/// dst.qword[0] := W[0] + s0(W[1])
+/// dst[MAX:256] := 0
+/// \endcode
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
+_mm256_sha512msg1_epi64(__m256i __A, __m128i __B) {
+  return (__m256i)__builtin_ia32_vsha512msg1((__v4du)__A, (__v2du)__B);
+}
+
+/// This intrinisc is one of the two SHA512 message scheduling instructions.
+///    The intrinsic performs the final calculation for the next four SHA512
+///    message qwords. The calculated results are stored in \a dst.
+///
+/// \headerfile <immintrin.h>
+///
+/// \code
+/// __m256i _mm256_sha512msg2_epi64(__m256i __A, __m256i __B)
+/// \endcode
+///
+/// This intrinsic corresponds to the \c VSHA512MSG2 instruction.
+///
+/// \param __A
+///    A 256-bit vector of [4 x long long].
+/// \param __B
+///    A 256-bit vector of [4 x long long].
+/// \returns
+///    A 256-bit vector of [4 x long long].
+///
+/// \code{.operation}
+/// DEFINE ROR64(qword, n) {
+/// 	count := n % 64
+/// 	dest := (qword >> count) | (qword << (64 - count))
+/// 	RETURN dest
+/// }
+/// DEFINE SHR64(qword, n) {
+/// 	RETURN qword >> n
+/// }
+/// DEFINE s1(qword) {
+/// 	RETURN ROR64(qword,19) ^ ROR64(qword, 61) ^ SHR64(qword, 6)
+/// }
+/// W[14] := __B.qword[2]
+/// W[15] := __B.qword[3]
+/// W[16] := __A.qword[0] + s1(W[14])
+/// W[17] := __A.qword[1] + s1(W[15])
+/// W[18] := __A.qword[2] + s1(W[16])
+/// W[19] := __A.qword[3] + s1(W[17])
+/// dst.qword[3] := W[19]
+/// dst.qword[2] := W[18]
+/// dst.qword[1] := W[17]
+/// dst.qword[0] := W[16]
+/// dst[MAX:256] := 0
+/// \endcode
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
+_mm256_sha512msg2_epi64(__m256i __A, __m256i __B) {
+  return (__m256i)__builtin_ia32_vsha512msg2((__v4du)__A, (__v4du)__B);
+}
+
+/// This intrinisc performs two rounds of SHA512 operation using initial SHA512
+///    state (C,D,G,H) from \a __A, an initial SHA512 state (A,B,E,F) from
+///    \a __A, and a pre-computed sum of the next two round message qwords and
+///    the corresponding round constants from \a __C (only the two lower qwords
+///    of the third operand). The updated SHA512 state (A,B,E,F) is written to
+///    \a __A, and \a __A can be used as the updated state (C,D,G,H) in later
+///    rounds.
+///
+/// \headerfile <immintrin.h>
+///
+/// \code
+/// __m256i _mm256_sha512rnds2_epi64(__m256i __A, __m256i __B, __m128i __C)
+/// \endcode
+///
+/// This intrinsic corresponds to the \c VSHA512RNDS2 instruction.
+///
+/// \param __A
+///    A 256-bit vector of [4 x long long].
+/// \param __B
+///    A 256-bit vector of [4 x long long].
+/// \param __C
+///    A 128-bit vector of [2 x long long].
+/// \returns
+///    A 256-bit vector of [4 x long long].
+///
+/// \code{.operation}
+/// DEFINE ROR64(qword, n) {
+/// 	count := n % 64
+/// 	dest := (qword >> count) | (qword << (64 - count))
+/// 	RETURN dest
+/// }
+/// DEFINE SHR64(qword, n) {
+/// 	RETURN qword >> n
+/// }
+/// DEFINE cap_sigma0(qword) {
+/// 	RETURN ROR64(qword,28) ^ ROR64(qword, 34) ^ ROR64(qword, 39)
+/// }
+/// DEFINE cap_sigma1(qword) {
+/// 	RETURN ROR64(qword,14) ^ ROR64(qword, 18) ^ ROR64(qword, 41)
+/// }
+/// DEFINE MAJ(a,b,c) {
+/// 	RETURN (a & b) ^ (a & c) ^ (b & c)
+/// }
+/// DEFINE CH(e,f,g) {
+/// 	RETURN (e & f) ^ (g & ~e)
+/// }
+/// A[0] := __B.qword[3]
+/// B[0] := __B.qword[2]
+/// C[0] := __C.qword[3]
+/// D[0] := __C.qword[2]
+/// E[0] := __B.qword[1]
+/// F[0] := __B.qword[0]
+/// G[0] := __C.qword[1]
+/// H[0] := __C.qword[0]
+/// WK[0]:= __A.qword[0]
+/// WK[1]:= __A.qword[1]
+/// FOR i := 0 to 1:
+/// 	A[i+1] := CH(E[i], F[i], G[i]) +
+/// 	cap_sigma1(E[i]) + WK[i] + H[i] +
+/// 	MAJ(A[i], B[i], C[i]) +
+/// 	cap_sigma0(A[i])
+/// 	B[i+1] := A[i]
+/// 	C[i+1] := B[i]
+/// 	D[i+1] := C[i]
+/// 	E[i+1] := CH(E[i], F[i], G[i]) +
+/// 	cap_sigma1(E[i]) + WK[i] + H[i] + D[i]
+/// 	F[i+1] := E[i]
+/// 	G[i+1] := F[i]
+/// 	H[i+1] := G[i]
+/// ENDFOR
+/// dst.qword[3] := A[2]
+/// dst.qword[2] := B[2]
+/// dst.qword[1] := E[2]
+/// dst.qword[0] := F[2]
+/// dst[MAX:256] := 0
+/// \endcode
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
+_mm256_sha512rnds2_epi64(__m256i __A, __m256i __B, __m128i __C) {
+  return (__m256i)__builtin_ia32_vsha512rnds2((__v4du)__A, (__v4du)__B,
+                                              (__v2du)__C);
+}
+
+#undef __DEFAULT_FN_ATTRS256
+
+#endif // __SHA512INTRIN_H