@nativescript/visionos 8.6.0-alpha.0 → 8.7.0-rc.0

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (395) hide show
  1. package/framework/.build_env_vars.sh +147 -143
  2. package/framework/__PROJECT_NAME__/__PROJECT_NAME__.entitlements +3 -1
  3. package/framework/__PROJECT_NAME__.xcodeproj/project.pbxproj +18 -6
  4. package/framework/__PROJECT_NAME__.xcodeproj/project.xcworkspace/xcuserdata/nstudio.xcuserdatad/UserInterfaceState.xcuserstate +0 -0
  5. package/framework/internal/NativeScriptEmbedder.h +29 -0
  6. package/framework/internal/NativeScriptEmbedder.m +25 -0
  7. package/framework/internal/NativeScriptStart.m +7 -8
  8. package/framework/internal/Swift-ObjC-Bridging-Header.h +1 -0
  9. package/framework/internal/XCFrameworks.zip +0 -0
  10. package/framework/internal/macros.h +17 -0
  11. package/framework/internal/metadata-generator-arm64/bin/build-step-metadata-generator.py +14 -0
  12. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/__clang_cuda_complex_builtins.h +3 -3
  13. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/__clang_cuda_intrinsics.h +38 -6
  14. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/__clang_cuda_libdevice_declares.h +6 -0
  15. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/__clang_cuda_math.h +1 -1
  16. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/__clang_cuda_runtime_wrapper.h +61 -2
  17. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/__clang_cuda_texture_intrinsics.h +740 -0
  18. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/__clang_hip_runtime_wrapper.h +17 -4
  19. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/__wmmintrin_aes.h +1 -1
  20. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/__wmmintrin_pclmul.h +10 -10
  21. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/altivec.h +677 -328
  22. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/ammintrin.h +4 -0
  23. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/amxintrin.h +17 -18
  24. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/arm_acle.h +6 -0
  25. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/arm_neon.h +8010 -8012
  26. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/arm_sve.h +65 -61
  27. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/avx2intrin.h +189 -189
  28. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512bf16intrin.h +3 -3
  29. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/avx512bwintrin.h +83 -83
  30. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512dqintrin.h +365 -365
  31. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512erintrin.h +102 -102
  32. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/avx512fintrin.h +1625 -1618
  33. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/avx512fp16intrin.h +3349 -0
  34. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/avx512vbmi2intrin.h +48 -48
  35. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512vlbf16intrin.h +52 -4
  36. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/avx512vlbwintrin.h +102 -102
  37. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/avx512vldqintrin.h +134 -134
  38. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/avx512vlfp16intrin.h +2068 -0
  39. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512vlintrin.h +596 -610
  40. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512vlvbmi2intrin.h +96 -96
  41. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/avx512vlvnniintrin.h +24 -24
  42. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/avxintrin.h +254 -222
  43. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avxvnniintrin.h +16 -16
  44. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/bmiintrin.h +6 -2
  45. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/cetintrin.h +20 -4
  46. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/cpuid.h +3 -1
  47. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/crc32intrin.h +100 -0
  48. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/emmintrin.h +563 -779
  49. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/f16cintrin.h +4 -4
  50. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/float.h +15 -6
  51. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/gfniintrin.h +47 -48
  52. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/hexagon_protos.h +0 -11
  53. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/hexagon_types.h +0 -32
  54. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/hlsl.h +15 -0
  55. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/hlsl_basic_types.h +64 -0
  56. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/hlsl_intrinsics.h +15 -0
  57. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/hresetintrin.h +2 -2
  58. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/hvx_hexagon_protos.h +1200 -409
  59. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/ia32intrin.h +17 -17
  60. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/immintrin.h +41 -23
  61. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/intrin.h +34 -35
  62. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/keylockerintrin.h +24 -30
  63. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/limits.h +20 -0
  64. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/mm_malloc.h +3 -3
  65. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/mmintrin.h +4 -0
  66. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/nmmintrin.h +4 -0
  67. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/opencl-c-base.h +79 -11
  68. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/opencl-c.h +7145 -6131
  69. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/openmp_wrappers/complex +10 -1
  70. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/openmp_wrappers/complex.h +9 -0
  71. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/pmmintrin.h +5 -1
  72. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/ppc_wrappers/bmi2intrin.h +134 -0
  73. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/ppc_wrappers/bmiintrin.h +165 -0
  74. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/ppc_wrappers/emmintrin.h +2268 -0
  75. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/ppc_wrappers/immintrin.h +27 -0
  76. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/ppc_wrappers/mm_malloc.h +12 -17
  77. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/ppc_wrappers/mmintrin.h +389 -386
  78. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/ppc_wrappers/pmmintrin.h +145 -0
  79. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/ppc_wrappers/smmintrin.h +663 -0
  80. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/ppc_wrappers/tmmintrin.h +453 -0
  81. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1/include/stdnoreturn.h → metadata-generator-arm64/bin/lib/clang/15.0.7/include/ppc_wrappers/x86gprintrin.h} +7 -6
  82. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/ppc_wrappers/x86intrin.h +28 -0
  83. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/ppc_wrappers/xmmintrin.h +1827 -0
  84. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/prfchwintrin.h +5 -2
  85. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/rdpruintrin.h +57 -0
  86. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/rdseedintrin.h +3 -3
  87. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/riscv_vector.h +202 -0
  88. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/rtmintrin.h +1 -1
  89. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/smmintrin.h +258 -360
  90. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/stdatomic.h +11 -1
  91. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/stdbool.h +9 -6
  92. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/stddef.h +1 -1
  93. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/stdint.h +168 -0
  94. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/stdnoreturn.h +29 -0
  95. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/tmmintrin.h +10 -6
  96. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/uintrintrin.h +8 -8
  97. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/unwind.h +10 -6
  98. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/vaesintrin.h +1 -1
  99. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/velintrin.h +71 -0
  100. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/velintrin_approx.h +120 -0
  101. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/velintrin_gen.h +1257 -0
  102. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/vpclmulqdqintrin.h +6 -6
  103. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/wasm_simd128.h +169 -26
  104. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/wmmintrin.h +4 -0
  105. package/framework/internal/metadata-generator-arm64/bin/lib/clang/15.0.7/include/x86gprintrin.h +53 -0
  106. package/framework/internal/{metadata-generator-x86_64/bin/lib/clang/13.0.1 → metadata-generator-arm64/bin/lib/clang/15.0.7}/include/x86intrin.h +4 -0
  107. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/xmmintrin.h +18 -8
  108. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/xopintrin.h +31 -31
  109. package/framework/internal/metadata-generator-arm64/bin/objc-metadata-generator +0 -0
  110. package/framework/internal/metadata-generator-x86_64/bin/build-step-metadata-generator.py +14 -0
  111. package/framework/internal/{metadata-generator-arm64/bin/lib/clang/13.0.1 → metadata-generator-x86_64/bin/lib/clang/15.0.7}/include/__clang_cuda_complex_builtins.h +3 -3
  112. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/__clang_cuda_intrinsics.h +38 -6
  113. package/framework/internal/{metadata-generator-arm64/bin/lib/clang/13.0.1 → metadata-generator-x86_64/bin/lib/clang/15.0.7}/include/__clang_cuda_libdevice_declares.h +6 -0
  114. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/__clang_cuda_math.h +1 -1
  115. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/__clang_cuda_runtime_wrapper.h +61 -2
  116. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/15.0.7/include/__clang_cuda_texture_intrinsics.h +740 -0
  117. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/__clang_hip_runtime_wrapper.h +17 -4
  118. package/framework/internal/{metadata-generator-arm64/bin/lib/clang/13.0.1 → metadata-generator-x86_64/bin/lib/clang/15.0.7}/include/__wmmintrin_aes.h +1 -1
  119. package/framework/internal/{metadata-generator-arm64/bin/lib/clang/13.0.1 → metadata-generator-x86_64/bin/lib/clang/15.0.7}/include/__wmmintrin_pclmul.h +10 -10
  120. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/altivec.h +677 -328
  121. package/framework/internal/{metadata-generator-arm64/bin/lib/clang/13.0.1 → metadata-generator-x86_64/bin/lib/clang/15.0.7}/include/ammintrin.h +4 -0
  122. package/framework/internal/{metadata-generator-arm64/bin/lib/clang/13.0.1 → metadata-generator-x86_64/bin/lib/clang/15.0.7}/include/amxintrin.h +17 -18
  123. package/framework/internal/{metadata-generator-arm64/bin/lib/clang/13.0.1 → metadata-generator-x86_64/bin/lib/clang/15.0.7}/include/arm_acle.h +6 -0
  124. package/framework/internal/{metadata-generator-arm64/bin/lib/clang/13.0.1 → metadata-generator-x86_64/bin/lib/clang/15.0.7}/include/arm_neon.h +8010 -8012
  125. package/framework/internal/{metadata-generator-arm64/bin/lib/clang/13.0.1 → metadata-generator-x86_64/bin/lib/clang/15.0.7}/include/arm_sve.h +65 -61
  126. package/framework/internal/{metadata-generator-arm64/bin/lib/clang/13.0.1 → metadata-generator-x86_64/bin/lib/clang/15.0.7}/include/avx2intrin.h +189 -189
  127. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512bf16intrin.h +3 -3
  128. package/framework/internal/{metadata-generator-arm64/bin/lib/clang/13.0.1 → metadata-generator-x86_64/bin/lib/clang/15.0.7}/include/avx512bwintrin.h +83 -83
  129. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512dqintrin.h +365 -365
  130. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512erintrin.h +102 -102
  131. package/framework/internal/{metadata-generator-arm64/bin/lib/clang/13.0.1 → metadata-generator-x86_64/bin/lib/clang/15.0.7}/include/avx512fintrin.h +1625 -1618
  132. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/15.0.7/include/avx512fp16intrin.h +3349 -0
  133. package/framework/internal/{metadata-generator-arm64/bin/lib/clang/13.0.1 → metadata-generator-x86_64/bin/lib/clang/15.0.7}/include/avx512vbmi2intrin.h +48 -48
  134. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512vlbf16intrin.h +52 -4
  135. package/framework/internal/{metadata-generator-arm64/bin/lib/clang/13.0.1 → metadata-generator-x86_64/bin/lib/clang/15.0.7}/include/avx512vlbwintrin.h +102 -102
  136. package/framework/internal/{metadata-generator-arm64/bin/lib/clang/13.0.1 → metadata-generator-x86_64/bin/lib/clang/15.0.7}/include/avx512vldqintrin.h +134 -134
  137. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/15.0.7/include/avx512vlfp16intrin.h +2068 -0
  138. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512vlintrin.h +596 -610
  139. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512vlvbmi2intrin.h +96 -96
  140. package/framework/internal/{metadata-generator-arm64/bin/lib/clang/13.0.1 → metadata-generator-x86_64/bin/lib/clang/15.0.7}/include/avx512vlvnniintrin.h +24 -24
  141. package/framework/internal/{metadata-generator-arm64/bin/lib/clang/13.0.1 → metadata-generator-x86_64/bin/lib/clang/15.0.7}/include/avxintrin.h +254 -222
  142. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avxvnniintrin.h +16 -16
  143. package/framework/internal/{metadata-generator-arm64/bin/lib/clang/13.0.1 → metadata-generator-x86_64/bin/lib/clang/15.0.7}/include/bmiintrin.h +6 -2
  144. package/framework/internal/{metadata-generator-arm64/bin/lib/clang/13.0.1 → metadata-generator-x86_64/bin/lib/clang/15.0.7}/include/cetintrin.h +20 -4
  145. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/cpuid.h +3 -1
  146. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/15.0.7/include/crc32intrin.h +100 -0
  147. package/framework/internal/{metadata-generator-arm64/bin/lib/clang/13.0.1 → metadata-generator-x86_64/bin/lib/clang/15.0.7}/include/emmintrin.h +563 -779
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  304. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/waitpkgintrin.h +0 -0
  305. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/wbnoinvdintrin.h +0 -0
  306. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/xsavecintrin.h +0 -0
  307. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/xsaveintrin.h +0 -0
  308. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/xsaveoptintrin.h +0 -0
  309. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/xsavesintrin.h +0 -0
  310. package/framework/internal/metadata-generator-arm64/bin/lib/clang/{13.0.1 → 15.0.7}/include/xtestintrin.h +0 -0
  311. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/__clang_cuda_builtin_vars.h +0 -0
  312. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/__clang_cuda_cmath.h +0 -0
  313. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/__clang_cuda_device_functions.h +0 -0
  314. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/__clang_cuda_math_forward_declares.h +0 -0
  315. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/__clang_hip_cmath.h +0 -0
  316. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/__clang_hip_libdevice_declares.h +0 -0
  317. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/__clang_hip_math.h +0 -0
  318. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/__stddef_max_align_t.h +0 -0
  319. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/adxintrin.h +0 -0
  320. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/arm64intr.h +0 -0
  321. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/arm_bf16.h +0 -0
  322. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/arm_cde.h +0 -0
  323. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/arm_cmse.h +0 -0
  324. package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/arm_fp16.h +89 -89
  325. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/arm_mve.h +0 -0
  326. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/armintr.h +0 -0
  327. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512bitalgintrin.h +0 -0
  328. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512cdintrin.h +0 -0
  329. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512ifmaintrin.h +0 -0
  330. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512ifmavlintrin.h +0 -0
  331. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512pfintrin.h +0 -0
  332. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512vbmiintrin.h +0 -0
  333. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512vbmivlintrin.h +0 -0
  334. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512vlbitalgintrin.h +0 -0
  335. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512vlcdintrin.h +0 -0
  336. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512vlvp2intersectintrin.h +0 -0
  337. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512vnniintrin.h +0 -0
  338. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512vp2intersectintrin.h +0 -0
  339. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512vpopcntdqintrin.h +0 -0
  340. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/avx512vpopcntdqvlintrin.h +0 -0
  341. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/bmi2intrin.h +0 -0
  342. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/builtins.h +0 -0
  343. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/cet.h +0 -0
  344. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/cldemoteintrin.h +0 -0
  345. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/clflushoptintrin.h +0 -0
  346. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/clwbintrin.h +0 -0
  347. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/clzerointrin.h +0 -0
  348. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/cuda_wrappers/algorithm +0 -0
  349. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/cuda_wrappers/complex +0 -0
  350. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/cuda_wrappers/new +0 -0
  351. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/enqcmdintrin.h +0 -0
  352. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/fma4intrin.h +0 -0
  353. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/fmaintrin.h +0 -0
  354. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/fxsrintrin.h +0 -0
  355. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/hexagon_circ_brev_intrinsics.h +0 -0
  356. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/htmintrin.h +0 -0
  357. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/htmxlintrin.h +0 -0
  358. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/inttypes.h +0 -0
  359. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/invpcidintrin.h +0 -0
  360. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/iso646.h +0 -0
  361. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/lwpintrin.h +0 -0
  362. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/lzcntintrin.h +0 -0
  363. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/mm3dnow.h +0 -0
  364. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/module.modulemap +0 -0
  365. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/movdirintrin.h +0 -0
  366. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/msa.h +0 -0
  367. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/mwaitxintrin.h +0 -0
  368. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/openmp_wrappers/__clang_openmp_device_functions.h +0 -0
  369. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/openmp_wrappers/cmath +0 -0
  370. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/openmp_wrappers/complex_cmath.h +0 -0
  371. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/openmp_wrappers/math.h +0 -0
  372. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/openmp_wrappers/new +0 -0
  373. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/pconfigintrin.h +0 -0
  374. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/pkuintrin.h +0 -0
  375. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/popcntintrin.h +0 -0
  376. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/ptwriteintrin.h +0 -0
  377. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/s390intrin.h +0 -0
  378. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/serializeintrin.h +0 -0
  379. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/sgxintrin.h +0 -0
  380. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/shaintrin.h +0 -0
  381. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/stdalign.h +0 -0
  382. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/stdarg.h +0 -0
  383. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/tbmintrin.h +0 -0
  384. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/tgmath.h +0 -0
  385. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/tsxldtrkintrin.h +0 -0
  386. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/vadefs.h +0 -0
  387. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/varargs.h +0 -0
  388. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/vecintrin.h +0 -0
  389. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/waitpkgintrin.h +0 -0
  390. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/wbnoinvdintrin.h +0 -0
  391. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/xsavecintrin.h +0 -0
  392. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/xsaveintrin.h +0 -0
  393. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/xsaveoptintrin.h +0 -0
  394. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/xsavesintrin.h +0 -0
  395. /package/framework/internal/metadata-generator-x86_64/bin/lib/clang/{13.0.1 → 15.0.7}/include/xtestintrin.h +0 -0
package/framework/internal/{metadata-generator-arm64/bin/lib/clang/13.0.1 → metadata-generator-x86_64/bin/lib/clang/15.0.7}/include/hvx_hexagon_protos.h RENAMED
@@ -9,7 +9,6 @@
9
9
  //===----------------------------------------------------------------------===//
10
10
 
11
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12
-
13
12
  #ifndef _HVX_HEXAGON_PROTOS_H_
14
13
  #define _HVX_HEXAGON_PROTOS_H_ 1
15
14
 
@@ -28,7 +27,7 @@
28
27
  Execution Slots: SLOT0
29
28
  ========================================================================== */
30
29
 
31
- #define Q6_R_vextract_VR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_extractw)
30
+ #define Q6_R_vextract_VR(Vu,Rs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_extractw)(Vu,Rs)
32
31
  #endif /* __HEXAGON_ARCH___ >= 60 */
33
32
 
34
33
  #if __HVX_ARCH__ >= 60
@@ -39,7 +38,7 @@
39
38
  Execution Slots: SLOT0123
40
39
  ========================================================================== */
41
40
 
42
- #define Q6_V_hi_W __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_hi)
41
+ #define Q6_V_hi_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_hi)(Vss)
43
42
  #endif /* __HEXAGON_ARCH___ >= 60 */
44
43
 
45
44
  #if __HVX_ARCH__ >= 60
@@ -50,7 +49,7 @@
50
49
  Execution Slots: SLOT0123
51
50
  ========================================================================== */
52
51
 
53
- #define Q6_V_lo_W __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lo)
52
+ #define Q6_V_lo_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lo)(Vss)
54
53
  #endif /* __HEXAGON_ARCH___ >= 60 */
55
54
 
56
55
  #if __HVX_ARCH__ >= 60
@@ -61,7 +60,7 @@
61
60
  Execution Slots: SLOT23
62
61
  ========================================================================== */
63
62
 
64
- #define Q6_V_vsplat_R __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatw)
63
+ #define Q6_V_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatw)(Rt)
65
64
  #endif /* __HEXAGON_ARCH___ >= 60 */
66
65
 
67
66
  #if __HVX_ARCH__ >= 60
@@ -72,7 +71,7 @@
72
71
  Execution Slots: SLOT0123
73
72
  ========================================================================== */
74
73
 
75
- #define Q6_Q_and_QQ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and)
74
+ #define Q6_Q_and_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
76
75
  #endif /* __HEXAGON_ARCH___ >= 60 */
77
76
 
78
77
  #if __HVX_ARCH__ >= 60
@@ -83,7 +82,7 @@
83
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  Execution Slots: SLOT0123
84
83
  ========================================================================== */
85
84
 
86
- #define Q6_Q_and_QQn __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and_n)
85
+ #define Q6_Q_and_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
87
86
  #endif /* __HEXAGON_ARCH___ >= 60 */
88
87
 
89
88
  #if __HVX_ARCH__ >= 60
@@ -94,7 +93,7 @@
94
93
  Execution Slots: SLOT0123
95
94
  ========================================================================== */
96
95
 
97
- #define Q6_Q_not_Q __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_not)
96
+ #define Q6_Q_not_Q(Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_not)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1))),-1)
98
97
  #endif /* __HEXAGON_ARCH___ >= 60 */
99
98
 
100
99
  #if __HVX_ARCH__ >= 60
@@ -105,7 +104,7 @@
105
104
  Execution Slots: SLOT0123
106
105
  ========================================================================== */
107
106
 
108
- #define Q6_Q_or_QQ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or)
107
+ #define Q6_Q_or_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
109
108
  #endif /* __HEXAGON_ARCH___ >= 60 */
110
109
 
111
110
  #if __HVX_ARCH__ >= 60
@@ -116,7 +115,7 @@
116
115
  Execution Slots: SLOT0123
117
116
  ========================================================================== */
118
117
 
119
- #define Q6_Q_or_QQn __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or_n)
118
+ #define Q6_Q_or_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
120
119
  #endif /* __HEXAGON_ARCH___ >= 60 */
121
120
 
122
121
  #if __HVX_ARCH__ >= 60
@@ -127,7 +126,7 @@
127
126
  Execution Slots: SLOT0123
128
127
  ========================================================================== */
129
128
 
130
- #define Q6_Q_vsetq_R __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2)
129
+ #define Q6_Q_vsetq_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2)(Rt)),-1)
131
130
  #endif /* __HEXAGON_ARCH___ >= 60 */
132
131
 
133
132
  #if __HVX_ARCH__ >= 60
@@ -138,7 +137,7 @@
138
137
  Execution Slots: SLOT0123
139
138
  ========================================================================== */
140
139
 
141
- #define Q6_Q_xor_QQ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_xor)
140
+ #define Q6_Q_xor_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
142
141
  #endif /* __HEXAGON_ARCH___ >= 60 */
143
142
 
144
143
  #if __HVX_ARCH__ >= 60
@@ -149,7 +148,7 @@
149
148
  Execution Slots: SLOT0
150
149
  ========================================================================== */
151
150
 
152
- #define Q6_vmem_QnRIV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai)
151
+ #define Q6_vmem_QnRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)
153
152
  #endif /* __HEXAGON_ARCH___ >= 60 */
154
153
 
155
154
  #if __HVX_ARCH__ >= 60
@@ -160,7 +159,7 @@
160
159
  Execution Slots: SLOT0
161
160
  ========================================================================== */
162
161
 
163
- #define Q6_vmem_QnRIV_nt __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai)
162
+ #define Q6_vmem_QnRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)
164
163
  #endif /* __HEXAGON_ARCH___ >= 60 */
165
164
 
166
165
  #if __HVX_ARCH__ >= 60
@@ -171,7 +170,7 @@
171
170
  Execution Slots: SLOT0
172
171
  ========================================================================== */
173
172
 
174
- #define Q6_vmem_QRIV_nt __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai)
173
+ #define Q6_vmem_QRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)
175
174
  #endif /* __HEXAGON_ARCH___ >= 60 */
176
175
 
177
176
  #if __HVX_ARCH__ >= 60
@@ -182,7 +181,7 @@
182
181
  Execution Slots: SLOT0
183
182
  ========================================================================== */
184
183
 
185
- #define Q6_vmem_QRIV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_qpred_ai)
184
+ #define Q6_vmem_QRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)
186
185
  #endif /* __HEXAGON_ARCH___ >= 60 */
187
186
 
188
187
  #if __HVX_ARCH__ >= 60
@@ -193,7 +192,7 @@
193
192
  Execution Slots: SLOT23
194
193
  ========================================================================== */
195
194
 
196
- #define Q6_Vuh_vabsdiff_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffh)
195
+ #define Q6_Vuh_vabsdiff_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffh)(Vu,Vv)
197
196
  #endif /* __HEXAGON_ARCH___ >= 60 */
198
197
 
199
198
  #if __HVX_ARCH__ >= 60
@@ -204,7 +203,7 @@
204
203
  Execution Slots: SLOT23
205
204
  ========================================================================== */
206
205
 
207
- #define Q6_Vub_vabsdiff_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffub)
206
+ #define Q6_Vub_vabsdiff_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffub)(Vu,Vv)
208
207
  #endif /* __HEXAGON_ARCH___ >= 60 */
209
208
 
210
209
  #if __HVX_ARCH__ >= 60
@@ -215,7 +214,7 @@
215
214
  Execution Slots: SLOT23
216
215
  ========================================================================== */
217
216
 
218
- #define Q6_Vuh_vabsdiff_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffuh)
217
+ #define Q6_Vuh_vabsdiff_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffuh)(Vu,Vv)
219
218
  #endif /* __HEXAGON_ARCH___ >= 60 */
220
219
 
221
220
  #if __HVX_ARCH__ >= 60
@@ -226,7 +225,7 @@
226
225
  Execution Slots: SLOT23
227
226
  ========================================================================== */
228
227
 
229
- #define Q6_Vuw_vabsdiff_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffw)
228
+ #define Q6_Vuw_vabsdiff_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffw)(Vu,Vv)
230
229
  #endif /* __HEXAGON_ARCH___ >= 60 */
231
230
 
232
231
  #if __HVX_ARCH__ >= 60
@@ -237,7 +236,7 @@
237
236
  Execution Slots: SLOT0123
238
237
  ========================================================================== */
239
238
 
240
- #define Q6_Vh_vabs_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh)
239
+ #define Q6_Vh_vabs_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh)(Vu)
241
240
  #endif /* __HEXAGON_ARCH___ >= 60 */
242
241
 
243
242
  #if __HVX_ARCH__ >= 60
@@ -248,7 +247,7 @@
248
247
  Execution Slots: SLOT0123
249
248
  ========================================================================== */
250
249
 
251
- #define Q6_Vh_vabs_Vh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh_sat)
250
+ #define Q6_Vh_vabs_Vh_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh_sat)(Vu)
252
251
  #endif /* __HEXAGON_ARCH___ >= 60 */
253
252
 
254
253
  #if __HVX_ARCH__ >= 60
@@ -259,7 +258,7 @@
259
258
  Execution Slots: SLOT0123
260
259
  ========================================================================== */
261
260
 
262
- #define Q6_Vw_vabs_Vw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw)
261
+ #define Q6_Vw_vabs_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw)(Vu)
263
262
  #endif /* __HEXAGON_ARCH___ >= 60 */
264
263
 
265
264
  #if __HVX_ARCH__ >= 60
@@ -270,7 +269,7 @@
270
269
  Execution Slots: SLOT0123
271
270
  ========================================================================== */
272
271
 
273
- #define Q6_Vw_vabs_Vw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw_sat)
272
+ #define Q6_Vw_vabs_Vw_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw_sat)(Vu)
274
273
  #endif /* __HEXAGON_ARCH___ >= 60 */
275
274
 
276
275
  #if __HVX_ARCH__ >= 60
@@ -281,7 +280,7 @@
281
280
  Execution Slots: SLOT0123
282
281
  ========================================================================== */
283
282
 
284
- #define Q6_Vb_vadd_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb)
283
+ #define Q6_Vb_vadd_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb)(Vu,Vv)
285
284
  #endif /* __HEXAGON_ARCH___ >= 60 */
286
285
 
287
286
  #if __HVX_ARCH__ >= 60
@@ -292,7 +291,7 @@
292
291
  Execution Slots: SLOT0123
293
292
  ========================================================================== */
294
293
 
295
- #define Q6_Wb_vadd_WbWb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb_dv)
294
+ #define Q6_Wb_vadd_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb_dv)(Vuu,Vvv)
296
295
  #endif /* __HEXAGON_ARCH___ >= 60 */
297
296
 
298
297
  #if __HVX_ARCH__ >= 60
@@ -303,7 +302,7 @@
303
302
  Execution Slots: SLOT0123
304
303
  ========================================================================== */
305
304
 
306
- #define Q6_Vb_condacc_QnVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbnq)
305
+ #define Q6_Vb_condacc_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
307
306
  #endif /* __HEXAGON_ARCH___ >= 60 */
308
307
 
309
308
  #if __HVX_ARCH__ >= 60
@@ -314,7 +313,7 @@
314
313
  Execution Slots: SLOT0123
315
314
  ========================================================================== */
316
315
 
317
- #define Q6_Vb_condacc_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbq)
316
+ #define Q6_Vb_condacc_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
318
317
  #endif /* __HEXAGON_ARCH___ >= 60 */
319
318
 
320
319
  #if __HVX_ARCH__ >= 60
@@ -325,7 +324,7 @@
325
324
  Execution Slots: SLOT0123
326
325
  ========================================================================== */
327
326
 
328
- #define Q6_Vh_vadd_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh)
327
+ #define Q6_Vh_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh)(Vu,Vv)
329
328
  #endif /* __HEXAGON_ARCH___ >= 60 */
330
329
 
331
330
  #if __HVX_ARCH__ >= 60
@@ -336,7 +335,7 @@
336
335
  Execution Slots: SLOT0123
337
336
  ========================================================================== */
338
337
 
339
- #define Q6_Wh_vadd_WhWh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh_dv)
338
+ #define Q6_Wh_vadd_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh_dv)(Vuu,Vvv)
340
339
  #endif /* __HEXAGON_ARCH___ >= 60 */
341
340
 
342
341
  #if __HVX_ARCH__ >= 60
@@ -347,7 +346,7 @@
347
346
  Execution Slots: SLOT0123
348
347
  ========================================================================== */
349
348
 
350
- #define Q6_Vh_condacc_QnVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhnq)
349
+ #define Q6_Vh_condacc_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
351
350
  #endif /* __HEXAGON_ARCH___ >= 60 */
352
351
 
353
352
  #if __HVX_ARCH__ >= 60
@@ -358,7 +357,7 @@
358
357
  Execution Slots: SLOT0123
359
358
  ========================================================================== */
360
359
 
361
- #define Q6_Vh_condacc_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhq)
360
+ #define Q6_Vh_condacc_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
362
361
  #endif /* __HEXAGON_ARCH___ >= 60 */
363
362
 
364
363
  #if __HVX_ARCH__ >= 60
@@ -369,7 +368,7 @@
369
368
  Execution Slots: SLOT0123
370
369
  ========================================================================== */
371
370
 
372
- #define Q6_Vh_vadd_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat)
371
+ #define Q6_Vh_vadd_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat)(Vu,Vv)
373
372
  #endif /* __HEXAGON_ARCH___ >= 60 */
374
373
 
375
374
  #if __HVX_ARCH__ >= 60
@@ -380,7 +379,7 @@
380
379
  Execution Slots: SLOT0123
381
380
  ========================================================================== */
382
381
 
383
- #define Q6_Wh_vadd_WhWh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat_dv)
382
+ #define Q6_Wh_vadd_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat_dv)(Vuu,Vvv)
384
383
  #endif /* __HEXAGON_ARCH___ >= 60 */
385
384
 
386
385
  #if __HVX_ARCH__ >= 60
@@ -391,7 +390,7 @@
391
390
  Execution Slots: SLOT23
392
391
  ========================================================================== */
393
392
 
394
- #define Q6_Ww_vadd_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw)
393
+ #define Q6_Ww_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw)(Vu,Vv)
395
394
  #endif /* __HEXAGON_ARCH___ >= 60 */
396
395
 
397
396
  #if __HVX_ARCH__ >= 60
@@ -402,7 +401,7 @@
402
401
  Execution Slots: SLOT23
403
402
  ========================================================================== */
404
403
 
405
- #define Q6_Wh_vadd_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh)
404
+ #define Q6_Wh_vadd_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh)(Vu,Vv)
406
405
  #endif /* __HEXAGON_ARCH___ >= 60 */
407
406
 
408
407
  #if __HVX_ARCH__ >= 60
@@ -413,7 +412,7 @@
413
412
  Execution Slots: SLOT0123
414
413
  ========================================================================== */
415
414
 
416
- #define Q6_Vub_vadd_VubVub_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat)
415
+ #define Q6_Vub_vadd_VubVub_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat)(Vu,Vv)
417
416
  #endif /* __HEXAGON_ARCH___ >= 60 */
418
417
 
419
418
  #if __HVX_ARCH__ >= 60
@@ -424,7 +423,7 @@
424
423
  Execution Slots: SLOT0123
425
424
  ========================================================================== */
426
425
 
427
- #define Q6_Wub_vadd_WubWub_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat_dv)
426
+ #define Q6_Wub_vadd_WubWub_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat_dv)(Vuu,Vvv)
428
427
  #endif /* __HEXAGON_ARCH___ >= 60 */
429
428
 
430
429
  #if __HVX_ARCH__ >= 60
@@ -435,7 +434,7 @@
435
434
  Execution Slots: SLOT0123
436
435
  ========================================================================== */
437
436
 
438
- #define Q6_Vuh_vadd_VuhVuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat)
437
+ #define Q6_Vuh_vadd_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat)(Vu,Vv)
439
438
  #endif /* __HEXAGON_ARCH___ >= 60 */
440
439
 
441
440
  #if __HVX_ARCH__ >= 60
@@ -446,7 +445,7 @@
446
445
  Execution Slots: SLOT0123
447
446
  ========================================================================== */
448
447
 
449
- #define Q6_Wuh_vadd_WuhWuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat_dv)
448
+ #define Q6_Wuh_vadd_WuhWuh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat_dv)(Vuu,Vvv)
450
449
  #endif /* __HEXAGON_ARCH___ >= 60 */
451
450
 
452
451
  #if __HVX_ARCH__ >= 60
@@ -457,7 +456,7 @@
457
456
  Execution Slots: SLOT23
458
457
  ========================================================================== */
459
458
 
460
- #define Q6_Ww_vadd_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw)
459
+ #define Q6_Ww_vadd_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw)(Vu,Vv)
461
460
  #endif /* __HEXAGON_ARCH___ >= 60 */
462
461
 
463
462
  #if __HVX_ARCH__ >= 60
@@ -468,7 +467,7 @@
468
467
  Execution Slots: SLOT0123
469
468
  ========================================================================== */
470
469
 
471
- #define Q6_Vw_vadd_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw)
470
+ #define Q6_Vw_vadd_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw)(Vu,Vv)
472
471
  #endif /* __HEXAGON_ARCH___ >= 60 */
473
472
 
474
473
  #if __HVX_ARCH__ >= 60
@@ -479,7 +478,7 @@
479
478
  Execution Slots: SLOT0123
480
479
  ========================================================================== */
481
480
 
482
- #define Q6_Ww_vadd_WwWw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw_dv)
481
+ #define Q6_Ww_vadd_WwWw(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw_dv)(Vuu,Vvv)
483
482
  #endif /* __HEXAGON_ARCH___ >= 60 */
484
483
 
485
484
  #if __HVX_ARCH__ >= 60
@@ -490,7 +489,7 @@
490
489
  Execution Slots: SLOT0123
491
490
  ========================================================================== */
492
491
 
493
- #define Q6_Vw_condacc_QnVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwnq)
492
+ #define Q6_Vw_condacc_QnVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
494
493
  #endif /* __HEXAGON_ARCH___ >= 60 */
495
494
 
496
495
  #if __HVX_ARCH__ >= 60
@@ -501,7 +500,7 @@
501
500
  Execution Slots: SLOT0123
502
501
  ========================================================================== */
503
502
 
504
- #define Q6_Vw_condacc_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwq)
503
+ #define Q6_Vw_condacc_QVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
505
504
  #endif /* __HEXAGON_ARCH___ >= 60 */
506
505
 
507
506
  #if __HVX_ARCH__ >= 60
@@ -512,7 +511,7 @@
512
511
  Execution Slots: SLOT0123
513
512
  ========================================================================== */
514
513
 
515
- #define Q6_Vw_vadd_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat)
514
+ #define Q6_Vw_vadd_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat)(Vu,Vv)
516
515
  #endif /* __HEXAGON_ARCH___ >= 60 */
517
516
 
518
517
  #if __HVX_ARCH__ >= 60
@@ -523,7 +522,7 @@
523
522
  Execution Slots: SLOT0123
524
523
  ========================================================================== */
525
524
 
526
- #define Q6_Ww_vadd_WwWw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat_dv)
525
+ #define Q6_Ww_vadd_WwWw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat_dv)(Vuu,Vvv)
527
526
  #endif /* __HEXAGON_ARCH___ >= 60 */
528
527
 
529
528
  #if __HVX_ARCH__ >= 60
@@ -534,7 +533,7 @@
534
533
  Execution Slots: SLOT0123
535
534
  ========================================================================== */
536
535
 
537
- #define Q6_V_valign_VVR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignb)
536
+ #define Q6_V_valign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignb)(Vu,Vv,Rt)
538
537
  #endif /* __HEXAGON_ARCH___ >= 60 */
539
538
 
540
539
  #if __HVX_ARCH__ >= 60
@@ -545,7 +544,7 @@
545
544
  Execution Slots: SLOT0123
546
545
  ========================================================================== */
547
546
 
548
- #define Q6_V_valign_VVI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignbi)
547
+ #define Q6_V_valign_VVI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignbi)(Vu,Vv,Iu3)
549
548
  #endif /* __HEXAGON_ARCH___ >= 60 */
550
549
 
551
550
  #if __HVX_ARCH__ >= 60
@@ -556,7 +555,7 @@
556
555
  Execution Slots: SLOT0123
557
556
  ========================================================================== */
558
557
 
559
- #define Q6_V_vand_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vand)
558
+ #define Q6_V_vand_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vand)(Vu,Vv)
560
559
  #endif /* __HEXAGON_ARCH___ >= 60 */
561
560
 
562
561
  #if __HVX_ARCH__ >= 60
@@ -567,7 +566,7 @@
567
566
  Execution Slots: SLOT23
568
567
  ========================================================================== */
569
568
 
570
- #define Q6_V_vand_QR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)
569
+ #define Q6_V_vand_QR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt)
571
570
  #endif /* __HEXAGON_ARCH___ >= 60 */
572
571
 
573
572
  #if __HVX_ARCH__ >= 60
@@ -578,7 +577,7 @@
578
577
  Execution Slots: SLOT23
579
578
  ========================================================================== */
580
579
 
581
- #define Q6_V_vandor_VQR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt_acc)
580
+ #define Q6_V_vandor_VQR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt)
582
581
  #endif /* __HEXAGON_ARCH___ >= 60 */
583
582
 
584
583
  #if __HVX_ARCH__ >= 60
@@ -589,7 +588,7 @@
589
588
  Execution Slots: SLOT23
590
589
  ========================================================================== */
591
590
 
592
- #define Q6_Q_vand_VR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)
591
+ #define Q6_Q_vand_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)(Vu,Rt)),-1)
593
592
  #endif /* __HEXAGON_ARCH___ >= 60 */
594
593
 
595
594
  #if __HVX_ARCH__ >= 60
@@ -600,7 +599,7 @@
600
599
  Execution Slots: SLOT23
601
600
  ========================================================================== */
602
601
 
603
- #define Q6_Q_vandor_QVR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt_acc)
602
+ #define Q6_Q_vandor_QVR(Qx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt_acc)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Rt)),-1)
604
603
  #endif /* __HEXAGON_ARCH___ >= 60 */
605
604
 
606
605
  #if __HVX_ARCH__ >= 60
@@ -611,7 +610,7 @@
611
610
  Execution Slots: SLOT0123
612
611
  ========================================================================== */
613
612
 
614
- #define Q6_Vh_vasl_VhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh)
613
+ #define Q6_Vh_vasl_VhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh)(Vu,Rt)
615
614
  #endif /* __HEXAGON_ARCH___ >= 60 */
616
615
 
617
616
  #if __HVX_ARCH__ >= 60
@@ -622,7 +621,7 @@
622
621
  Execution Slots: SLOT0123
623
622
  ========================================================================== */
624
623
 
625
- #define Q6_Vh_vasl_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslhv)
624
+ #define Q6_Vh_vasl_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslhv)(Vu,Vv)
626
625
  #endif /* __HEXAGON_ARCH___ >= 60 */
627
626
 
628
627
  #if __HVX_ARCH__ >= 60
@@ -633,7 +632,7 @@
633
632
  Execution Slots: SLOT0123
634
633
  ========================================================================== */
635
634
 
636
- #define Q6_Vw_vasl_VwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw)
635
+ #define Q6_Vw_vasl_VwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw)(Vu,Rt)
637
636
  #endif /* __HEXAGON_ARCH___ >= 60 */
638
637
 
639
638
  #if __HVX_ARCH__ >= 60
@@ -644,7 +643,7 @@
644
643
  Execution Slots: SLOT0123
645
644
  ========================================================================== */
646
645
 
647
- #define Q6_Vw_vaslacc_VwVwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw_acc)
646
+ #define Q6_Vw_vaslacc_VwVwR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw_acc)(Vx,Vu,Rt)
648
647
  #endif /* __HEXAGON_ARCH___ >= 60 */
649
648
 
650
649
  #if __HVX_ARCH__ >= 60
@@ -655,7 +654,7 @@
655
654
  Execution Slots: SLOT0123
656
655
  ========================================================================== */
657
656
 
658
- #define Q6_Vw_vasl_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslwv)
657
+ #define Q6_Vw_vasl_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslwv)(Vu,Vv)
659
658
  #endif /* __HEXAGON_ARCH___ >= 60 */
660
659
 
661
660
  #if __HVX_ARCH__ >= 60
@@ -666,7 +665,7 @@
666
665
  Execution Slots: SLOT0123
667
666
  ========================================================================== */
668
667
 
669
- #define Q6_Vh_vasr_VhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh)
668
+ #define Q6_Vh_vasr_VhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh)(Vu,Rt)
670
669
  #endif /* __HEXAGON_ARCH___ >= 60 */
671
670
 
672
671
  #if __HVX_ARCH__ >= 60
@@ -677,7 +676,7 @@
677
676
  Execution Slots: SLOT0123
678
677
  ========================================================================== */
679
678
 
680
- #define Q6_Vb_vasr_VhVhR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbrndsat)
679
+ #define Q6_Vb_vasr_VhVhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbrndsat)(Vu,Vv,Rt)
681
680
  #endif /* __HEXAGON_ARCH___ >= 60 */
682
681
 
683
682
  #if __HVX_ARCH__ >= 60
@@ -688,7 +687,7 @@
688
687
  Execution Slots: SLOT0123
689
688
  ========================================================================== */
690
689
 
691
- #define Q6_Vub_vasr_VhVhR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubrndsat)
690
+ #define Q6_Vub_vasr_VhVhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubrndsat)(Vu,Vv,Rt)
692
691
  #endif /* __HEXAGON_ARCH___ >= 60 */
693
692
 
694
693
  #if __HVX_ARCH__ >= 60
@@ -699,7 +698,7 @@
699
698
  Execution Slots: SLOT0123
700
699
  ========================================================================== */
701
700
 
702
- #define Q6_Vub_vasr_VhVhR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubsat)
701
+ #define Q6_Vub_vasr_VhVhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubsat)(Vu,Vv,Rt)
703
702
  #endif /* __HEXAGON_ARCH___ >= 60 */
704
703
 
705
704
  #if __HVX_ARCH__ >= 60
@@ -710,7 +709,7 @@
710
709
  Execution Slots: SLOT0123
711
710
  ========================================================================== */
712
711
 
713
- #define Q6_Vh_vasr_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhv)
712
+ #define Q6_Vh_vasr_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhv)(Vu,Vv)
714
713
  #endif /* __HEXAGON_ARCH___ >= 60 */
715
714
 
716
715
  #if __HVX_ARCH__ >= 60
@@ -721,7 +720,7 @@
721
720
  Execution Slots: SLOT0123
722
721
  ========================================================================== */
723
722
 
724
- #define Q6_Vw_vasr_VwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw)
723
+ #define Q6_Vw_vasr_VwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw)(Vu,Rt)
725
724
  #endif /* __HEXAGON_ARCH___ >= 60 */
726
725
 
727
726
  #if __HVX_ARCH__ >= 60
@@ -732,7 +731,7 @@
732
731
  Execution Slots: SLOT0123
733
732
  ========================================================================== */
734
733
 
735
- #define Q6_Vw_vasracc_VwVwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw_acc)
734
+ #define Q6_Vw_vasracc_VwVwR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw_acc)(Vx,Vu,Rt)
736
735
  #endif /* __HEXAGON_ARCH___ >= 60 */
737
736
 
738
737
  #if __HVX_ARCH__ >= 60
@@ -743,7 +742,7 @@
743
742
  Execution Slots: SLOT0123
744
743
  ========================================================================== */
745
744
 
746
- #define Q6_Vh_vasr_VwVwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwh)
745
+ #define Q6_Vh_vasr_VwVwR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwh)(Vu,Vv,Rt)
747
746
  #endif /* __HEXAGON_ARCH___ >= 60 */
748
747
 
749
748
  #if __HVX_ARCH__ >= 60
@@ -754,7 +753,7 @@
754
753
  Execution Slots: SLOT0123
755
754
  ========================================================================== */
756
755
 
757
- #define Q6_Vh_vasr_VwVwR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhrndsat)
756
+ #define Q6_Vh_vasr_VwVwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhrndsat)(Vu,Vv,Rt)
758
757
  #endif /* __HEXAGON_ARCH___ >= 60 */
759
758
 
760
759
  #if __HVX_ARCH__ >= 60
@@ -765,7 +764,7 @@
765
764
  Execution Slots: SLOT0123
766
765
  ========================================================================== */
767
766
 
768
- #define Q6_Vh_vasr_VwVwR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhsat)
767
+ #define Q6_Vh_vasr_VwVwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhsat)(Vu,Vv,Rt)
769
768
  #endif /* __HEXAGON_ARCH___ >= 60 */
770
769
 
771
770
  #if __HVX_ARCH__ >= 60
@@ -776,7 +775,7 @@
776
775
  Execution Slots: SLOT0123
777
776
  ========================================================================== */
778
777
 
779
- #define Q6_Vuh_vasr_VwVwR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhsat)
778
+ #define Q6_Vuh_vasr_VwVwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhsat)(Vu,Vv,Rt)
780
779
  #endif /* __HEXAGON_ARCH___ >= 60 */
781
780
 
782
781
  #if __HVX_ARCH__ >= 60
@@ -787,7 +786,7 @@
787
786
  Execution Slots: SLOT0123
788
787
  ========================================================================== */
789
788
 
790
- #define Q6_Vw_vasr_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwv)
789
+ #define Q6_Vw_vasr_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwv)(Vu,Vv)
791
790
  #endif /* __HEXAGON_ARCH___ >= 60 */
792
791
 
793
792
  #if __HVX_ARCH__ >= 60
@@ -798,7 +797,7 @@
798
797
  Execution Slots: SLOT0123
799
798
  ========================================================================== */
800
799
 
801
- #define Q6_V_equals_V __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign)
800
+ #define Q6_V_equals_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign)(Vu)
802
801
  #endif /* __HEXAGON_ARCH___ >= 60 */
803
802
 
804
803
  #if __HVX_ARCH__ >= 60
@@ -809,7 +808,7 @@
809
808
  Execution Slots: SLOT0123
810
809
  ========================================================================== */
811
810
 
812
- #define Q6_W_equals_W __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassignp)
811
+ #define Q6_W_equals_W(Vuu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassignp)(Vuu)
813
812
  #endif /* __HEXAGON_ARCH___ >= 60 */
814
813
 
815
814
  #if __HVX_ARCH__ >= 60
@@ -820,7 +819,7 @@
820
819
  Execution Slots: SLOT0123
821
820
  ========================================================================== */
822
821
 
823
- #define Q6_Vh_vavg_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgh)
822
+ #define Q6_Vh_vavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgh)(Vu,Vv)
824
823
  #endif /* __HEXAGON_ARCH___ >= 60 */
825
824
 
826
825
  #if __HVX_ARCH__ >= 60
@@ -831,7 +830,7 @@
831
830
  Execution Slots: SLOT0123
832
831
  ========================================================================== */
833
832
 
834
- #define Q6_Vh_vavg_VhVh_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavghrnd)
833
+ #define Q6_Vh_vavg_VhVh_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavghrnd)(Vu,Vv)
835
834
  #endif /* __HEXAGON_ARCH___ >= 60 */
836
835
 
837
836
  #if __HVX_ARCH__ >= 60
@@ -842,7 +841,7 @@
842
841
  Execution Slots: SLOT0123
843
842
  ========================================================================== */
844
843
 
845
- #define Q6_Vub_vavg_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgub)
844
+ #define Q6_Vub_vavg_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgub)(Vu,Vv)
846
845
  #endif /* __HEXAGON_ARCH___ >= 60 */
847
846
 
848
847
  #if __HVX_ARCH__ >= 60
@@ -853,7 +852,7 @@
853
852
  Execution Slots: SLOT0123
854
853
  ========================================================================== */
855
854
 
856
- #define Q6_Vub_vavg_VubVub_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgubrnd)
855
+ #define Q6_Vub_vavg_VubVub_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgubrnd)(Vu,Vv)
857
856
  #endif /* __HEXAGON_ARCH___ >= 60 */
858
857
 
859
858
  #if __HVX_ARCH__ >= 60
@@ -864,7 +863,7 @@
864
863
  Execution Slots: SLOT0123
865
864
  ========================================================================== */
866
865
 
867
- #define Q6_Vuh_vavg_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguh)
866
+ #define Q6_Vuh_vavg_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguh)(Vu,Vv)
868
867
  #endif /* __HEXAGON_ARCH___ >= 60 */
869
868
 
870
869
  #if __HVX_ARCH__ >= 60
@@ -875,7 +874,7 @@
875
874
  Execution Slots: SLOT0123
876
875
  ========================================================================== */
877
876
 
878
- #define Q6_Vuh_vavg_VuhVuh_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguhrnd)
877
+ #define Q6_Vuh_vavg_VuhVuh_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguhrnd)(Vu,Vv)
879
878
  #endif /* __HEXAGON_ARCH___ >= 60 */
880
879
 
881
880
  #if __HVX_ARCH__ >= 60
@@ -886,7 +885,7 @@
886
885
  Execution Slots: SLOT0123
887
886
  ========================================================================== */
888
887
 
889
- #define Q6_Vw_vavg_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgw)
888
+ #define Q6_Vw_vavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgw)(Vu,Vv)
890
889
  #endif /* __HEXAGON_ARCH___ >= 60 */
891
890
 
892
891
  #if __HVX_ARCH__ >= 60
@@ -897,7 +896,7 @@
897
896
  Execution Slots: SLOT0123
898
897
  ========================================================================== */
899
898
 
900
- #define Q6_Vw_vavg_VwVw_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgwrnd)
899
+ #define Q6_Vw_vavg_VwVw_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgwrnd)(Vu,Vv)
901
900
  #endif /* __HEXAGON_ARCH___ >= 60 */
902
901
 
903
902
  #if __HVX_ARCH__ >= 60
@@ -908,7 +907,7 @@
908
907
  Execution Slots: SLOT0123
909
908
  ========================================================================== */
910
909
 
911
- #define Q6_Vuh_vcl0_Vuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0h)
910
+ #define Q6_Vuh_vcl0_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0h)(Vu)
912
911
  #endif /* __HEXAGON_ARCH___ >= 60 */
913
912
 
914
913
  #if __HVX_ARCH__ >= 60
@@ -919,7 +918,7 @@
919
918
  Execution Slots: SLOT0123
920
919
  ========================================================================== */
921
920
 
922
- #define Q6_Vuw_vcl0_Vuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0w)
921
+ #define Q6_Vuw_vcl0_Vuw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0w)(Vu)
923
922
  #endif /* __HEXAGON_ARCH___ >= 60 */
924
923
 
925
924
  #if __HVX_ARCH__ >= 60
@@ -930,7 +929,7 @@
930
929
  Execution Slots: SLOT0123
931
930
  ========================================================================== */
932
931
 
933
- #define Q6_W_vcombine_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcombine)
932
+ #define Q6_W_vcombine_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcombine)(Vu,Vv)
934
933
  #endif /* __HEXAGON_ARCH___ >= 60 */
935
934
 
936
935
  #if __HVX_ARCH__ >= 60
@@ -941,7 +940,7 @@
941
940
  Execution Slots: SLOT0123
942
941
  ========================================================================== */
943
942
 
944
- #define Q6_V_vzero __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vd0)
943
+ #define Q6_V_vzero() __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vd0)()
945
944
  #endif /* __HEXAGON_ARCH___ >= 60 */
946
945
 
947
946
  #if __HVX_ARCH__ >= 60
@@ -952,7 +951,7 @@
952
951
  Execution Slots: SLOT0123
953
952
  ========================================================================== */
954
953
 
955
- #define Q6_Vb_vdeal_Vb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb)
954
+ #define Q6_Vb_vdeal_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb)(Vu)
956
955
  #endif /* __HEXAGON_ARCH___ >= 60 */
957
956
 
958
957
  #if __HVX_ARCH__ >= 60
@@ -963,7 +962,7 @@
963
962
  Execution Slots: SLOT0123
964
963
  ========================================================================== */
965
964
 
966
- #define Q6_Vb_vdeale_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb4w)
965
+ #define Q6_Vb_vdeale_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb4w)(Vu,Vv)
967
966
  #endif /* __HEXAGON_ARCH___ >= 60 */
968
967
 
969
968
  #if __HVX_ARCH__ >= 60
@@ -974,7 +973,7 @@
974
973
  Execution Slots: SLOT0123
975
974
  ========================================================================== */
976
975
 
977
- #define Q6_Vh_vdeal_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealh)
976
+ #define Q6_Vh_vdeal_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealh)(Vu)
978
977
  #endif /* __HEXAGON_ARCH___ >= 60 */
979
978
 
980
979
  #if __HVX_ARCH__ >= 60
@@ -985,7 +984,7 @@
985
984
  Execution Slots: SLOT0123
986
985
  ========================================================================== */
987
986
 
988
- #define Q6_W_vdeal_VVR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealvdd)
987
+ #define Q6_W_vdeal_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealvdd)(Vu,Vv,Rt)
989
988
  #endif /* __HEXAGON_ARCH___ >= 60 */
990
989
 
991
990
  #if __HVX_ARCH__ >= 60
@@ -996,7 +995,7 @@
996
995
  Execution Slots: SLOT0123
997
996
  ========================================================================== */
998
997
 
999
- #define Q6_V_vdelta_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdelta)
998
+ #define Q6_V_vdelta_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdelta)(Vu,Vv)
1000
999
  #endif /* __HEXAGON_ARCH___ >= 60 */
1001
1000
 
1002
1001
  #if __HVX_ARCH__ >= 60
@@ -1007,7 +1006,7 @@
1007
1006
  Execution Slots: SLOT23
1008
1007
  ========================================================================== */
1009
1008
 
1010
- #define Q6_Vh_vdmpy_VubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus)
1009
+ #define Q6_Vh_vdmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus)(Vu,Rt)
1011
1010
  #endif /* __HEXAGON_ARCH___ >= 60 */
1012
1011
 
1013
1012
  #if __HVX_ARCH__ >= 60
@@ -1018,7 +1017,7 @@
1018
1017
  Execution Slots: SLOT23
1019
1018
  ========================================================================== */
1020
1019
 
1021
- #define Q6_Vh_vdmpyacc_VhVubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_acc)
1020
+ #define Q6_Vh_vdmpyacc_VhVubRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_acc)(Vx,Vu,Rt)
1022
1021
  #endif /* __HEXAGON_ARCH___ >= 60 */
1023
1022
 
1024
1023
  #if __HVX_ARCH__ >= 60
@@ -1029,7 +1028,7 @@
1029
1028
  Execution Slots: SLOT23
1030
1029
  ========================================================================== */
1031
1030
 
1032
- #define Q6_Wh_vdmpy_WubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv)
1031
+ #define Q6_Wh_vdmpy_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv)(Vuu,Rt)
1033
1032
  #endif /* __HEXAGON_ARCH___ >= 60 */
1034
1033
 
1035
1034
  #if __HVX_ARCH__ >= 60
@@ -1040,7 +1039,7 @@
1040
1039
  Execution Slots: SLOT23
1041
1040
  ========================================================================== */
1042
1041
 
1043
- #define Q6_Wh_vdmpyacc_WhWubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv_acc)
1042
+ #define Q6_Wh_vdmpyacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv_acc)(Vxx,Vuu,Rt)
1044
1043
  #endif /* __HEXAGON_ARCH___ >= 60 */
1045
1044
 
1046
1045
  #if __HVX_ARCH__ >= 60
@@ -1051,7 +1050,7 @@
1051
1050
  Execution Slots: SLOT23
1052
1051
  ========================================================================== */
1053
1052
 
1054
- #define Q6_Vw_vdmpy_VhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb)
1053
+ #define Q6_Vw_vdmpy_VhRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb)(Vu,Rt)
1055
1054
  #endif /* __HEXAGON_ARCH___ >= 60 */
1056
1055
 
1057
1056
  #if __HVX_ARCH__ >= 60
@@ -1062,7 +1061,7 @@
1062
1061
  Execution Slots: SLOT23
1063
1062
  ========================================================================== */
1064
1063
 
1065
- #define Q6_Vw_vdmpyacc_VwVhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_acc)
1064
+ #define Q6_Vw_vdmpyacc_VwVhRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_acc)(Vx,Vu,Rt)
1066
1065
  #endif /* __HEXAGON_ARCH___ >= 60 */
1067
1066
 
1068
1067
  #if __HVX_ARCH__ >= 60
@@ -1073,7 +1072,7 @@
1073
1072
  Execution Slots: SLOT23
1074
1073
  ========================================================================== */
1075
1074
 
1076
- #define Q6_Ww_vdmpy_WhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv)
1075
+ #define Q6_Ww_vdmpy_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv)(Vuu,Rt)
1077
1076
  #endif /* __HEXAGON_ARCH___ >= 60 */
1078
1077
 
1079
1078
  #if __HVX_ARCH__ >= 60
@@ -1084,7 +1083,7 @@
1084
1083
  Execution Slots: SLOT23
1085
1084
  ========================================================================== */
1086
1085
 
1087
- #define Q6_Ww_vdmpyacc_WwWhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv_acc)
1086
+ #define Q6_Ww_vdmpyacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv_acc)(Vxx,Vuu,Rt)
1088
1087
  #endif /* __HEXAGON_ARCH___ >= 60 */
1089
1088
 
1090
1089
  #if __HVX_ARCH__ >= 60
@@ -1095,7 +1094,7 @@
1095
1094
  Execution Slots: SLOT23
1096
1095
  ========================================================================== */
1097
1096
 
1098
- #define Q6_Vw_vdmpy_WhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat)
1097
+ #define Q6_Vw_vdmpy_WhRh_sat(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat)(Vuu,Rt)
1099
1098
  #endif /* __HEXAGON_ARCH___ >= 60 */
1100
1099
 
1101
1100
  #if __HVX_ARCH__ >= 60
@@ -1106,29 +1105,29 @@
1106
1105
  Execution Slots: SLOT23
1107
1106
  ========================================================================== */
1108
1107
 
1109
- #define Q6_Vw_vdmpyacc_VwWhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat_acc)
1108
+ #define Q6_Vw_vdmpyacc_VwWhRh_sat(Vx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat_acc)(Vx,Vuu,Rt)
1110
1109
  #endif /* __HEXAGON_ARCH___ >= 60 */
1111
1110
 
1112
1111
  #if __HVX_ARCH__ >= 60
1113
1112
  /* ==========================================================================
1114
1113
  Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.h):sat
1115
1114
  C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRh_sat(HVX_Vector Vu, Word32 Rt)
1116
- Instruction Type: CVI_VX_DV
1115
+ Instruction Type: CVI_VX
1117
1116
  Execution Slots: SLOT23
1118
1117
  ========================================================================== */
1119
1118
 
1120
- #define Q6_Vw_vdmpy_VhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat)
1119
+ #define Q6_Vw_vdmpy_VhRh_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat)(Vu,Rt)
1121
1120
  #endif /* __HEXAGON_ARCH___ >= 60 */
1122
1121
 
1123
1122
  #if __HVX_ARCH__ >= 60
1124
1123
  /* ==========================================================================
1125
1124
  Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.h):sat
1126
1125
  C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
1127
- Instruction Type: CVI_VX_DV
1126
+ Instruction Type: CVI_VX
1128
1127
  Execution Slots: SLOT23
1129
1128
  ========================================================================== */
1130
1129
 
1131
- #define Q6_Vw_vdmpyacc_VwVhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat_acc)
1130
+ #define Q6_Vw_vdmpyacc_VwVhRh_sat(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat_acc)(Vx,Vu,Rt)
1132
1131
  #endif /* __HEXAGON_ARCH___ >= 60 */
1133
1132
 
1134
1133
  #if __HVX_ARCH__ >= 60
@@ -1139,7 +1138,7 @@
1139
1138
  Execution Slots: SLOT23
1140
1139
  ========================================================================== */
1141
1140
 
1142
- #define Q6_Vw_vdmpy_WhRuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat)
1141
+ #define Q6_Vw_vdmpy_WhRuh_sat(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat)(Vuu,Rt)
1143
1142
  #endif /* __HEXAGON_ARCH___ >= 60 */
1144
1143
 
1145
1144
  #if __HVX_ARCH__ >= 60
@@ -1150,40 +1149,40 @@
1150
1149
  Execution Slots: SLOT23
1151
1150
  ========================================================================== */
1152
1151
 
1153
- #define Q6_Vw_vdmpyacc_VwWhRuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat_acc)
1152
+ #define Q6_Vw_vdmpyacc_VwWhRuh_sat(Vx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat_acc)(Vx,Vuu,Rt)
1154
1153
  #endif /* __HEXAGON_ARCH___ >= 60 */
1155
1154
 
1156
1155
  #if __HVX_ARCH__ >= 60
1157
1156
  /* ==========================================================================
1158
1157
  Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.uh):sat
1159
1158
  C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRuh_sat(HVX_Vector Vu, Word32 Rt)
1160
- Instruction Type: CVI_VX_DV
1159
+ Instruction Type: CVI_VX
1161
1160
  Execution Slots: SLOT23
1162
1161
  ========================================================================== */
1163
1162
 
1164
- #define Q6_Vw_vdmpy_VhRuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat)
1163
+ #define Q6_Vw_vdmpy_VhRuh_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat)(Vu,Rt)
1165
1164
  #endif /* __HEXAGON_ARCH___ >= 60 */
1166
1165
 
1167
1166
  #if __HVX_ARCH__ >= 60
1168
1167
  /* ==========================================================================
1169
1168
  Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.uh):sat
1170
1169
  C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
1171
- Instruction Type: CVI_VX_DV
1170
+ Instruction Type: CVI_VX
1172
1171
  Execution Slots: SLOT23
1173
1172
  ========================================================================== */
1174
1173
 
1175
- #define Q6_Vw_vdmpyacc_VwVhRuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat_acc)
1174
+ #define Q6_Vw_vdmpyacc_VwVhRuh_sat(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat_acc)(Vx,Vu,Rt)
1176
1175
  #endif /* __HEXAGON_ARCH___ >= 60 */
1177
1176
 
1178
1177
  #if __HVX_ARCH__ >= 60
1179
1178
  /* ==========================================================================
1180
1179
  Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Vv32.h):sat
1181
1180
  C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
1182
- Instruction Type: CVI_VX_DV
1181
+ Instruction Type: CVI_VX
1183
1182
  Execution Slots: SLOT23
1184
1183
  ========================================================================== */
1185
1184
 
1186
- #define Q6_Vw_vdmpy_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat)
1185
+ #define Q6_Vw_vdmpy_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat)(Vu,Vv)
1187
1186
  #endif /* __HEXAGON_ARCH___ >= 60 */
1188
1187
 
1189
1188
  #if __HVX_ARCH__ >= 60
@@ -1194,7 +1193,7 @@
1194
1193
  Execution Slots: SLOT23
1195
1194
  ========================================================================== */
1196
1195
 
1197
- #define Q6_Vw_vdmpyacc_VwVhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat_acc)
1196
+ #define Q6_Vw_vdmpyacc_VwVhVh_sat(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat_acc)(Vx,Vu,Vv)
1198
1197
  #endif /* __HEXAGON_ARCH___ >= 60 */
1199
1198
 
1200
1199
  #if __HVX_ARCH__ >= 60
@@ -1205,7 +1204,7 @@
1205
1204
  Execution Slots: SLOT23
1206
1205
  ========================================================================== */
1207
1206
 
1208
- #define Q6_Wuw_vdsad_WuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh)
1207
+ #define Q6_Wuw_vdsad_WuhRuh(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh)(Vuu,Rt)
1209
1208
  #endif /* __HEXAGON_ARCH___ >= 60 */
1210
1209
 
1211
1210
  #if __HVX_ARCH__ >= 60
@@ -1216,7 +1215,7 @@
1216
1215
  Execution Slots: SLOT23
1217
1216
  ========================================================================== */
1218
1217
 
1219
- #define Q6_Wuw_vdsadacc_WuwWuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh_acc)
1218
+ #define Q6_Wuw_vdsadacc_WuwWuhRuh(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh_acc)(Vxx,Vuu,Rt)
1220
1219
  #endif /* __HEXAGON_ARCH___ >= 60 */
1221
1220
 
1222
1221
  #if __HVX_ARCH__ >= 60
@@ -1227,7 +1226,7 @@
1227
1226
  Execution Slots: SLOT0123
1228
1227
  ========================================================================== */
1229
1228
 
1230
- #define Q6_Q_vcmp_eq_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb)
1229
+ #define Q6_Q_vcmp_eq_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb)(Vu,Vv)),-1)
1231
1230
  #endif /* __HEXAGON_ARCH___ >= 60 */
1232
1231
 
1233
1232
  #if __HVX_ARCH__ >= 60
@@ -1238,7 +1237,7 @@
1238
1237
  Execution Slots: SLOT0123
1239
1238
  ========================================================================== */
1240
1239
 
1241
- #define Q6_Q_vcmp_eqand_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_and)
1240
+ #define Q6_Q_vcmp_eqand_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1242
1241
  #endif /* __HEXAGON_ARCH___ >= 60 */
1243
1242
 
1244
1243
  #if __HVX_ARCH__ >= 60
@@ -1249,7 +1248,7 @@
1249
1248
  Execution Slots: SLOT0123
1250
1249
  ========================================================================== */
1251
1250
 
1252
- #define Q6_Q_vcmp_eqor_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_or)
1251
+ #define Q6_Q_vcmp_eqor_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1253
1252
  #endif /* __HEXAGON_ARCH___ >= 60 */
1254
1253
 
1255
1254
  #if __HVX_ARCH__ >= 60
@@ -1260,7 +1259,7 @@
1260
1259
  Execution Slots: SLOT0123
1261
1260
  ========================================================================== */
1262
1261
 
1263
- #define Q6_Q_vcmp_eqxacc_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_xor)
1262
+ #define Q6_Q_vcmp_eqxacc_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1264
1263
  #endif /* __HEXAGON_ARCH___ >= 60 */
1265
1264
 
1266
1265
  #if __HVX_ARCH__ >= 60
@@ -1271,7 +1270,7 @@
1271
1270
  Execution Slots: SLOT0123
1272
1271
  ========================================================================== */
1273
1272
 
1274
- #define Q6_Q_vcmp_eq_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh)
1273
+ #define Q6_Q_vcmp_eq_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh)(Vu,Vv)),-1)
1275
1274
  #endif /* __HEXAGON_ARCH___ >= 60 */
1276
1275
 
1277
1276
  #if __HVX_ARCH__ >= 60
@@ -1282,7 +1281,7 @@
1282
1281
  Execution Slots: SLOT0123
1283
1282
  ========================================================================== */
1284
1283
 
1285
- #define Q6_Q_vcmp_eqand_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_and)
1284
+ #define Q6_Q_vcmp_eqand_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1286
1285
  #endif /* __HEXAGON_ARCH___ >= 60 */
1287
1286
 
1288
1287
  #if __HVX_ARCH__ >= 60
@@ -1293,7 +1292,7 @@
1293
1292
  Execution Slots: SLOT0123
1294
1293
  ========================================================================== */
1295
1294
 
1296
- #define Q6_Q_vcmp_eqor_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_or)
1295
+ #define Q6_Q_vcmp_eqor_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1297
1296
  #endif /* __HEXAGON_ARCH___ >= 60 */
1298
1297
 
1299
1298
  #if __HVX_ARCH__ >= 60
@@ -1304,7 +1303,7 @@
1304
1303
  Execution Slots: SLOT0123
1305
1304
  ========================================================================== */
1306
1305
 
1307
- #define Q6_Q_vcmp_eqxacc_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_xor)
1306
+ #define Q6_Q_vcmp_eqxacc_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1308
1307
  #endif /* __HEXAGON_ARCH___ >= 60 */
1309
1308
 
1310
1309
  #if __HVX_ARCH__ >= 60
@@ -1315,7 +1314,7 @@
1315
1314
  Execution Slots: SLOT0123
1316
1315
  ========================================================================== */
1317
1316
 
1318
- #define Q6_Q_vcmp_eq_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw)
1317
+ #define Q6_Q_vcmp_eq_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw)(Vu,Vv)),-1)
1319
1318
  #endif /* __HEXAGON_ARCH___ >= 60 */
1320
1319
 
1321
1320
  #if __HVX_ARCH__ >= 60
@@ -1326,7 +1325,7 @@
1326
1325
  Execution Slots: SLOT0123
1327
1326
  ========================================================================== */
1328
1327
 
1329
- #define Q6_Q_vcmp_eqand_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_and)
1328
+ #define Q6_Q_vcmp_eqand_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1330
1329
  #endif /* __HEXAGON_ARCH___ >= 60 */
1331
1330
 
1332
1331
  #if __HVX_ARCH__ >= 60
@@ -1337,7 +1336,7 @@
1337
1336
  Execution Slots: SLOT0123
1338
1337
  ========================================================================== */
1339
1338
 
1340
- #define Q6_Q_vcmp_eqor_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_or)
1339
+ #define Q6_Q_vcmp_eqor_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1341
1340
  #endif /* __HEXAGON_ARCH___ >= 60 */
1342
1341
 
1343
1342
  #if __HVX_ARCH__ >= 60
@@ -1348,7 +1347,7 @@
1348
1347
  Execution Slots: SLOT0123
1349
1348
  ========================================================================== */
1350
1349
 
1351
- #define Q6_Q_vcmp_eqxacc_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_xor)
1350
+ #define Q6_Q_vcmp_eqxacc_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1352
1351
  #endif /* __HEXAGON_ARCH___ >= 60 */
1353
1352
 
1354
1353
  #if __HVX_ARCH__ >= 60
@@ -1359,7 +1358,7 @@
1359
1358
  Execution Slots: SLOT0123
1360
1359
  ========================================================================== */
1361
1360
 
1362
- #define Q6_Q_vcmp_gt_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb)
1361
+ #define Q6_Q_vcmp_gt_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb)(Vu,Vv)),-1)
1363
1362
  #endif /* __HEXAGON_ARCH___ >= 60 */
1364
1363
 
1365
1364
  #if __HVX_ARCH__ >= 60
@@ -1370,7 +1369,7 @@
1370
1369
  Execution Slots: SLOT0123
1371
1370
  ========================================================================== */
1372
1371
 
1373
- #define Q6_Q_vcmp_gtand_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_and)
1372
+ #define Q6_Q_vcmp_gtand_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1374
1373
  #endif /* __HEXAGON_ARCH___ >= 60 */
1375
1374
 
1376
1375
  #if __HVX_ARCH__ >= 60
@@ -1381,7 +1380,7 @@
1381
1380
  Execution Slots: SLOT0123
1382
1381
  ========================================================================== */
1383
1382
 
1384
- #define Q6_Q_vcmp_gtor_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_or)
1383
+ #define Q6_Q_vcmp_gtor_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1385
1384
  #endif /* __HEXAGON_ARCH___ >= 60 */
1386
1385
 
1387
1386
  #if __HVX_ARCH__ >= 60
@@ -1392,7 +1391,7 @@
1392
1391
  Execution Slots: SLOT0123
1393
1392
  ========================================================================== */
1394
1393
 
1395
- #define Q6_Q_vcmp_gtxacc_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_xor)
1394
+ #define Q6_Q_vcmp_gtxacc_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1396
1395
  #endif /* __HEXAGON_ARCH___ >= 60 */
1397
1396
 
1398
1397
  #if __HVX_ARCH__ >= 60
@@ -1403,7 +1402,7 @@
1403
1402
  Execution Slots: SLOT0123
1404
1403
  ========================================================================== */
1405
1404
 
1406
- #define Q6_Q_vcmp_gt_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth)
1405
+ #define Q6_Q_vcmp_gt_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth)(Vu,Vv)),-1)
1407
1406
  #endif /* __HEXAGON_ARCH___ >= 60 */
1408
1407
 
1409
1408
  #if __HVX_ARCH__ >= 60
@@ -1414,7 +1413,7 @@
1414
1413
  Execution Slots: SLOT0123
1415
1414
  ========================================================================== */
1416
1415
 
1417
- #define Q6_Q_vcmp_gtand_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_and)
1416
+ #define Q6_Q_vcmp_gtand_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1418
1417
  #endif /* __HEXAGON_ARCH___ >= 60 */
1419
1418
 
1420
1419
  #if __HVX_ARCH__ >= 60
@@ -1425,7 +1424,7 @@
1425
1424
  Execution Slots: SLOT0123
1426
1425
  ========================================================================== */
1427
1426
 
1428
- #define Q6_Q_vcmp_gtor_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_or)
1427
+ #define Q6_Q_vcmp_gtor_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1429
1428
  #endif /* __HEXAGON_ARCH___ >= 60 */
1430
1429
 
1431
1430
  #if __HVX_ARCH__ >= 60
@@ -1436,7 +1435,7 @@
1436
1435
  Execution Slots: SLOT0123
1437
1436
  ========================================================================== */
1438
1437
 
1439
- #define Q6_Q_vcmp_gtxacc_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_xor)
1438
+ #define Q6_Q_vcmp_gtxacc_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1440
1439
  #endif /* __HEXAGON_ARCH___ >= 60 */
1441
1440
 
1442
1441
  #if __HVX_ARCH__ >= 60
@@ -1447,7 +1446,7 @@
1447
1446
  Execution Slots: SLOT0123
1448
1447
  ========================================================================== */
1449
1448
 
1450
- #define Q6_Q_vcmp_gt_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub)
1449
+ #define Q6_Q_vcmp_gt_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub)(Vu,Vv)),-1)
1451
1450
  #endif /* __HEXAGON_ARCH___ >= 60 */
1452
1451
 
1453
1452
  #if __HVX_ARCH__ >= 60
@@ -1458,7 +1457,7 @@
1458
1457
  Execution Slots: SLOT0123
1459
1458
  ========================================================================== */
1460
1459
 
1461
- #define Q6_Q_vcmp_gtand_QVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_and)
1460
+ #define Q6_Q_vcmp_gtand_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1462
1461
  #endif /* __HEXAGON_ARCH___ >= 60 */
1463
1462
 
1464
1463
  #if __HVX_ARCH__ >= 60
@@ -1469,7 +1468,7 @@
1469
1468
  Execution Slots: SLOT0123
1470
1469
  ========================================================================== */
1471
1470
 
1472
- #define Q6_Q_vcmp_gtor_QVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_or)
1471
+ #define Q6_Q_vcmp_gtor_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1473
1472
  #endif /* __HEXAGON_ARCH___ >= 60 */
1474
1473
 
1475
1474
  #if __HVX_ARCH__ >= 60
@@ -1480,7 +1479,7 @@
1480
1479
  Execution Slots: SLOT0123
1481
1480
  ========================================================================== */
1482
1481
 
1483
- #define Q6_Q_vcmp_gtxacc_QVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_xor)
1482
+ #define Q6_Q_vcmp_gtxacc_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1484
1483
  #endif /* __HEXAGON_ARCH___ >= 60 */
1485
1484
 
1486
1485
  #if __HVX_ARCH__ >= 60
@@ -1491,7 +1490,7 @@
1491
1490
  Execution Slots: SLOT0123
1492
1491
  ========================================================================== */
1493
1492
 
1494
- #define Q6_Q_vcmp_gt_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh)
1493
+ #define Q6_Q_vcmp_gt_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh)(Vu,Vv)),-1)
1495
1494
  #endif /* __HEXAGON_ARCH___ >= 60 */
1496
1495
 
1497
1496
  #if __HVX_ARCH__ >= 60
@@ -1502,7 +1501,7 @@
1502
1501
  Execution Slots: SLOT0123
1503
1502
  ========================================================================== */
1504
1503
 
1505
- #define Q6_Q_vcmp_gtand_QVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_and)
1504
+ #define Q6_Q_vcmp_gtand_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1506
1505
  #endif /* __HEXAGON_ARCH___ >= 60 */
1507
1506
 
1508
1507
  #if __HVX_ARCH__ >= 60
@@ -1513,7 +1512,7 @@
1513
1512
  Execution Slots: SLOT0123
1514
1513
  ========================================================================== */
1515
1514
 
1516
- #define Q6_Q_vcmp_gtor_QVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_or)
1515
+ #define Q6_Q_vcmp_gtor_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1517
1516
  #endif /* __HEXAGON_ARCH___ >= 60 */
1518
1517
 
1519
1518
  #if __HVX_ARCH__ >= 60
@@ -1524,7 +1523,7 @@
1524
1523
  Execution Slots: SLOT0123
1525
1524
  ========================================================================== */
1526
1525
 
1527
- #define Q6_Q_vcmp_gtxacc_QVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_xor)
1526
+ #define Q6_Q_vcmp_gtxacc_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1528
1527
  #endif /* __HEXAGON_ARCH___ >= 60 */
1529
1528
 
1530
1529
  #if __HVX_ARCH__ >= 60
@@ -1535,7 +1534,7 @@
1535
1534
  Execution Slots: SLOT0123
1536
1535
  ========================================================================== */
1537
1536
 
1538
- #define Q6_Q_vcmp_gt_VuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw)
1537
+ #define Q6_Q_vcmp_gt_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw)(Vu,Vv)),-1)
1539
1538
  #endif /* __HEXAGON_ARCH___ >= 60 */
1540
1539
 
1541
1540
  #if __HVX_ARCH__ >= 60
@@ -1546,7 +1545,7 @@
1546
1545
  Execution Slots: SLOT0123
1547
1546
  ========================================================================== */
1548
1547
 
1549
- #define Q6_Q_vcmp_gtand_QVuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_and)
1548
+ #define Q6_Q_vcmp_gtand_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1550
1549
  #endif /* __HEXAGON_ARCH___ >= 60 */
1551
1550
 
1552
1551
  #if __HVX_ARCH__ >= 60
@@ -1557,7 +1556,7 @@
1557
1556
  Execution Slots: SLOT0123
1558
1557
  ========================================================================== */
1559
1558
 
1560
- #define Q6_Q_vcmp_gtor_QVuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_or)
1559
+ #define Q6_Q_vcmp_gtor_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1561
1560
  #endif /* __HEXAGON_ARCH___ >= 60 */
1562
1561
 
1563
1562
  #if __HVX_ARCH__ >= 60
@@ -1568,7 +1567,7 @@
1568
1567
  Execution Slots: SLOT0123
1569
1568
  ========================================================================== */
1570
1569
 
1571
- #define Q6_Q_vcmp_gtxacc_QVuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_xor)
1570
+ #define Q6_Q_vcmp_gtxacc_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1572
1571
  #endif /* __HEXAGON_ARCH___ >= 60 */
1573
1572
 
1574
1573
  #if __HVX_ARCH__ >= 60
@@ -1579,7 +1578,7 @@
1579
1578
  Execution Slots: SLOT0123
1580
1579
  ========================================================================== */
1581
1580
 
1582
- #define Q6_Q_vcmp_gt_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw)
1581
+ #define Q6_Q_vcmp_gt_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw)(Vu,Vv)),-1)
1583
1582
  #endif /* __HEXAGON_ARCH___ >= 60 */
1584
1583
 
1585
1584
  #if __HVX_ARCH__ >= 60
@@ -1590,7 +1589,7 @@
1590
1589
  Execution Slots: SLOT0123
1591
1590
  ========================================================================== */
1592
1591
 
1593
- #define Q6_Q_vcmp_gtand_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_and)
1592
+ #define Q6_Q_vcmp_gtand_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1594
1593
  #endif /* __HEXAGON_ARCH___ >= 60 */
1595
1594
 
1596
1595
  #if __HVX_ARCH__ >= 60
@@ -1601,7 +1600,7 @@
1601
1600
  Execution Slots: SLOT0123
1602
1601
  ========================================================================== */
1603
1602
 
1604
- #define Q6_Q_vcmp_gtor_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_or)
1603
+ #define Q6_Q_vcmp_gtor_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1605
1604
  #endif /* __HEXAGON_ARCH___ >= 60 */
1606
1605
 
1607
1606
  #if __HVX_ARCH__ >= 60
@@ -1612,7 +1611,7 @@
1612
1611
  Execution Slots: SLOT0123
1613
1612
  ========================================================================== */
1614
1613
 
1615
- #define Q6_Q_vcmp_gtxacc_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_xor)
1614
+ #define Q6_Q_vcmp_gtxacc_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
1616
1615
  #endif /* __HEXAGON_ARCH___ >= 60 */
1617
1616
 
1618
1617
  #if __HVX_ARCH__ >= 60
@@ -1623,7 +1622,7 @@
1623
1622
  Execution Slots: SLOT23
1624
1623
  ========================================================================== */
1625
1624
 
1626
- #define Q6_Vw_vinsert_VwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vinsertwr)
1625
+ #define Q6_Vw_vinsert_VwR(Vx,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vinsertwr)(Vx,Rt)
1627
1626
  #endif /* __HEXAGON_ARCH___ >= 60 */
1628
1627
 
1629
1628
  #if __HVX_ARCH__ >= 60
@@ -1634,7 +1633,7 @@
1634
1633
  Execution Slots: SLOT0123
1635
1634
  ========================================================================== */
1636
1635
 
1637
- #define Q6_V_vlalign_VVR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignb)
1636
+ #define Q6_V_vlalign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignb)(Vu,Vv,Rt)
1638
1637
  #endif /* __HEXAGON_ARCH___ >= 60 */
1639
1638
 
1640
1639
  #if __HVX_ARCH__ >= 60
@@ -1645,7 +1644,7 @@
1645
1644
  Execution Slots: SLOT0123
1646
1645
  ========================================================================== */
1647
1646
 
1648
- #define Q6_V_vlalign_VVI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignbi)
1647
+ #define Q6_V_vlalign_VVI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignbi)(Vu,Vv,Iu3)
1649
1648
  #endif /* __HEXAGON_ARCH___ >= 60 */
1650
1649
 
1651
1650
  #if __HVX_ARCH__ >= 60
@@ -1656,7 +1655,7 @@
1656
1655
  Execution Slots: SLOT0123
1657
1656
  ========================================================================== */
1658
1657
 
1659
- #define Q6_Vuh_vlsr_VuhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrh)
1658
+ #define Q6_Vuh_vlsr_VuhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrh)(Vu,Rt)
1660
1659
  #endif /* __HEXAGON_ARCH___ >= 60 */
1661
1660
 
1662
1661
  #if __HVX_ARCH__ >= 60
@@ -1667,7 +1666,7 @@
1667
1666
  Execution Slots: SLOT0123
1668
1667
  ========================================================================== */
1669
1668
 
1670
- #define Q6_Vh_vlsr_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrhv)
1669
+ #define Q6_Vh_vlsr_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrhv)(Vu,Vv)
1671
1670
  #endif /* __HEXAGON_ARCH___ >= 60 */
1672
1671
 
1673
1672
  #if __HVX_ARCH__ >= 60
@@ -1678,7 +1677,7 @@
1678
1677
  Execution Slots: SLOT0123
1679
1678
  ========================================================================== */
1680
1679
 
1681
- #define Q6_Vuw_vlsr_VuwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrw)
1680
+ #define Q6_Vuw_vlsr_VuwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrw)(Vu,Rt)
1682
1681
  #endif /* __HEXAGON_ARCH___ >= 60 */
1683
1682
 
1684
1683
  #if __HVX_ARCH__ >= 60
@@ -1689,7 +1688,7 @@
1689
1688
  Execution Slots: SLOT0123
1690
1689
  ========================================================================== */
1691
1690
 
1692
- #define Q6_Vw_vlsr_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrwv)
1691
+ #define Q6_Vw_vlsr_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrwv)(Vu,Vv)
1693
1692
  #endif /* __HEXAGON_ARCH___ >= 60 */
1694
1693
 
1695
1694
  #if __HVX_ARCH__ >= 60
@@ -1700,7 +1699,7 @@
1700
1699
  Execution Slots: SLOT0123
1701
1700
  ========================================================================== */
1702
1701
 
1703
- #define Q6_Vb_vlut32_VbVbR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb)
1702
+ #define Q6_Vb_vlut32_VbVbR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb)(Vu,Vv,Rt)
1704
1703
  #endif /* __HEXAGON_ARCH___ >= 60 */
1705
1704
 
1706
1705
  #if __HVX_ARCH__ >= 60
@@ -1711,7 +1710,7 @@
1711
1710
  Execution Slots: SLOT0123
1712
1711
  ========================================================================== */
1713
1712
 
1714
- #define Q6_Vb_vlut32or_VbVbVbR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracc)
1713
+ #define Q6_Vb_vlut32or_VbVbVbR(Vx,Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracc)(Vx,Vu,Vv,Rt)
1715
1714
  #endif /* __HEXAGON_ARCH___ >= 60 */
1716
1715
 
1717
1716
  #if __HVX_ARCH__ >= 60
@@ -1722,7 +1721,7 @@
1722
1721
  Execution Slots: SLOT0123
1723
1722
  ========================================================================== */
1724
1723
 
1725
- #define Q6_Wh_vlut16_VbVhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh)
1724
+ #define Q6_Wh_vlut16_VbVhR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh)(Vu,Vv,Rt)
1726
1725
  #endif /* __HEXAGON_ARCH___ >= 60 */
1727
1726
 
1728
1727
  #if __HVX_ARCH__ >= 60
@@ -1733,7 +1732,7 @@
1733
1732
  Execution Slots: SLOT0123
1734
1733
  ========================================================================== */
1735
1734
 
1736
- #define Q6_Wh_vlut16or_WhVbVhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracc)
1735
+ #define Q6_Wh_vlut16or_WhVbVhR(Vxx,Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracc)(Vxx,Vu,Vv,Rt)
1737
1736
  #endif /* __HEXAGON_ARCH___ >= 60 */
1738
1737
 
1739
1738
  #if __HVX_ARCH__ >= 60
@@ -1744,7 +1743,7 @@
1744
1743
  Execution Slots: SLOT0123
1745
1744
  ========================================================================== */
1746
1745
 
1747
- #define Q6_Vh_vmax_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxh)
1746
+ #define Q6_Vh_vmax_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxh)(Vu,Vv)
1748
1747
  #endif /* __HEXAGON_ARCH___ >= 60 */
1749
1748
 
1750
1749
  #if __HVX_ARCH__ >= 60
@@ -1755,7 +1754,7 @@
1755
1754
  Execution Slots: SLOT0123
1756
1755
  ========================================================================== */
1757
1756
 
1758
- #define Q6_Vub_vmax_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxub)
1757
+ #define Q6_Vub_vmax_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxub)(Vu,Vv)
1759
1758
  #endif /* __HEXAGON_ARCH___ >= 60 */
1760
1759
 
1761
1760
  #if __HVX_ARCH__ >= 60
@@ -1766,7 +1765,7 @@
1766
1765
  Execution Slots: SLOT0123
1767
1766
  ========================================================================== */
1768
1767
 
1769
- #define Q6_Vuh_vmax_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxuh)
1768
+ #define Q6_Vuh_vmax_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxuh)(Vu,Vv)
1770
1769
  #endif /* __HEXAGON_ARCH___ >= 60 */
1771
1770
 
1772
1771
  #if __HVX_ARCH__ >= 60
@@ -1777,7 +1776,7 @@
1777
1776
  Execution Slots: SLOT0123
1778
1777
  ========================================================================== */
1779
1778
 
1780
- #define Q6_Vw_vmax_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxw)
1779
+ #define Q6_Vw_vmax_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxw)(Vu,Vv)
1781
1780
  #endif /* __HEXAGON_ARCH___ >= 60 */
1782
1781
 
1783
1782
  #if __HVX_ARCH__ >= 60
@@ -1788,7 +1787,7 @@
1788
1787
  Execution Slots: SLOT0123
1789
1788
  ========================================================================== */
1790
1789
 
1791
- #define Q6_Vh_vmin_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminh)
1790
+ #define Q6_Vh_vmin_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminh)(Vu,Vv)
1792
1791
  #endif /* __HEXAGON_ARCH___ >= 60 */
1793
1792
 
1794
1793
  #if __HVX_ARCH__ >= 60
@@ -1799,7 +1798,7 @@
1799
1798
  Execution Slots: SLOT0123
1800
1799
  ========================================================================== */
1801
1800
 
1802
- #define Q6_Vub_vmin_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminub)
1801
+ #define Q6_Vub_vmin_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminub)(Vu,Vv)
1803
1802
  #endif /* __HEXAGON_ARCH___ >= 60 */
1804
1803
 
1805
1804
  #if __HVX_ARCH__ >= 60
@@ -1810,7 +1809,7 @@
1810
1809
  Execution Slots: SLOT0123
1811
1810
  ========================================================================== */
1812
1811
 
1813
- #define Q6_Vuh_vmin_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminuh)
1812
+ #define Q6_Vuh_vmin_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminuh)(Vu,Vv)
1814
1813
  #endif /* __HEXAGON_ARCH___ >= 60 */
1815
1814
 
1816
1815
  #if __HVX_ARCH__ >= 60
@@ -1821,7 +1820,7 @@
1821
1820
  Execution Slots: SLOT0123
1822
1821
  ========================================================================== */
1823
1822
 
1824
- #define Q6_Vw_vmin_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminw)
1823
+ #define Q6_Vw_vmin_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminw)(Vu,Vv)
1825
1824
  #endif /* __HEXAGON_ARCH___ >= 60 */
1826
1825
 
1827
1826
  #if __HVX_ARCH__ >= 60
@@ -1832,7 +1831,7 @@
1832
1831
  Execution Slots: SLOT23
1833
1832
  ========================================================================== */
1834
1833
 
1835
- #define Q6_Wh_vmpa_WubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus)
1834
+ #define Q6_Wh_vmpa_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus)(Vuu,Rt)
1836
1835
  #endif /* __HEXAGON_ARCH___ >= 60 */
1837
1836
 
1838
1837
  #if __HVX_ARCH__ >= 60
@@ -1843,7 +1842,7 @@
1843
1842
  Execution Slots: SLOT23
1844
1843
  ========================================================================== */
1845
1844
 
1846
- #define Q6_Wh_vmpaacc_WhWubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus_acc)
1845
+ #define Q6_Wh_vmpaacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus_acc)(Vxx,Vuu,Rt)
1847
1846
  #endif /* __HEXAGON_ARCH___ >= 60 */
1848
1847
 
1849
1848
  #if __HVX_ARCH__ >= 60
@@ -1854,7 +1853,7 @@
1854
1853
  Execution Slots: SLOT23
1855
1854
  ========================================================================== */
1856
1855
 
1857
- #define Q6_Wh_vmpa_WubWb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabusv)
1856
+ #define Q6_Wh_vmpa_WubWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabusv)(Vuu,Vvv)
1858
1857
  #endif /* __HEXAGON_ARCH___ >= 60 */
1859
1858
 
1860
1859
  #if __HVX_ARCH__ >= 60
@@ -1865,7 +1864,7 @@
1865
1864
  Execution Slots: SLOT23
1866
1865
  ========================================================================== */
1867
1866
 
1868
- #define Q6_Wh_vmpa_WubWub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuuv)
1867
+ #define Q6_Wh_vmpa_WubWub(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuuv)(Vuu,Vvv)
1869
1868
  #endif /* __HEXAGON_ARCH___ >= 60 */
1870
1869
 
1871
1870
  #if __HVX_ARCH__ >= 60
@@ -1876,7 +1875,7 @@
1876
1875
  Execution Slots: SLOT23
1877
1876
  ========================================================================== */
1878
1877
 
1879
- #define Q6_Ww_vmpa_WhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb)
1878
+ #define Q6_Ww_vmpa_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb)(Vuu,Rt)
1880
1879
  #endif /* __HEXAGON_ARCH___ >= 60 */
1881
1880
 
1882
1881
  #if __HVX_ARCH__ >= 60
@@ -1887,7 +1886,7 @@
1887
1886
  Execution Slots: SLOT23
1888
1887
  ========================================================================== */
1889
1888
 
1890
- #define Q6_Ww_vmpaacc_WwWhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb_acc)
1889
+ #define Q6_Ww_vmpaacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb_acc)(Vxx,Vuu,Rt)
1891
1890
  #endif /* __HEXAGON_ARCH___ >= 60 */
1892
1891
 
1893
1892
  #if __HVX_ARCH__ >= 60
@@ -1898,7 +1897,7 @@
1898
1897
  Execution Slots: SLOT23
1899
1898
  ========================================================================== */
1900
1899
 
1901
- #define Q6_Wh_vmpy_VubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus)
1900
+ #define Q6_Wh_vmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus)(Vu,Rt)
1902
1901
  #endif /* __HEXAGON_ARCH___ >= 60 */
1903
1902
 
1904
1903
  #if __HVX_ARCH__ >= 60
@@ -1909,7 +1908,7 @@
1909
1908
  Execution Slots: SLOT23
1910
1909
  ========================================================================== */
1911
1910
 
1912
- #define Q6_Wh_vmpyacc_WhVubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus_acc)
1911
+ #define Q6_Wh_vmpyacc_WhVubRb(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus_acc)(Vxx,Vu,Rt)
1913
1912
  #endif /* __HEXAGON_ARCH___ >= 60 */
1914
1913
 
1915
1914
  #if __HVX_ARCH__ >= 60
@@ -1920,7 +1919,7 @@
1920
1919
  Execution Slots: SLOT23
1921
1920
  ========================================================================== */
1922
1921
 
1923
- #define Q6_Wh_vmpy_VubVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv)
1922
+ #define Q6_Wh_vmpy_VubVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv)(Vu,Vv)
1924
1923
  #endif /* __HEXAGON_ARCH___ >= 60 */
1925
1924
 
1926
1925
  #if __HVX_ARCH__ >= 60
@@ -1931,7 +1930,7 @@
1931
1930
  Execution Slots: SLOT23
1932
1931
  ========================================================================== */
1933
1932
 
1934
- #define Q6_Wh_vmpyacc_WhVubVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv_acc)
1933
+ #define Q6_Wh_vmpyacc_WhVubVb(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv_acc)(Vxx,Vu,Vv)
1935
1934
  #endif /* __HEXAGON_ARCH___ >= 60 */
1936
1935
 
1937
1936
  #if __HVX_ARCH__ >= 60
@@ -1942,7 +1941,7 @@
1942
1941
  Execution Slots: SLOT23
1943
1942
  ========================================================================== */
1944
1943
 
1945
- #define Q6_Wh_vmpy_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv)
1944
+ #define Q6_Wh_vmpy_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv)(Vu,Vv)
1946
1945
  #endif /* __HEXAGON_ARCH___ >= 60 */
1947
1946
 
1948
1947
  #if __HVX_ARCH__ >= 60
@@ -1953,7 +1952,7 @@
1953
1952
  Execution Slots: SLOT23
1954
1953
  ========================================================================== */
1955
1954
 
1956
- #define Q6_Wh_vmpyacc_WhVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv_acc)
1955
+ #define Q6_Wh_vmpyacc_WhVbVb(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv_acc)(Vxx,Vu,Vv)
1957
1956
  #endif /* __HEXAGON_ARCH___ >= 60 */
1958
1957
 
1959
1958
  #if __HVX_ARCH__ >= 60
@@ -1964,7 +1963,7 @@
1964
1963
  Execution Slots: SLOT23
1965
1964
  ========================================================================== */
1966
1965
 
1967
- #define Q6_Vw_vmpye_VwVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh)
1966
+ #define Q6_Vw_vmpye_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh)(Vu,Vv)
1968
1967
  #endif /* __HEXAGON_ARCH___ >= 60 */
1969
1968
 
1970
1969
  #if __HVX_ARCH__ >= 60
@@ -1975,7 +1974,7 @@
1975
1974
  Execution Slots: SLOT23
1976
1975
  ========================================================================== */
1977
1976
 
1978
- #define Q6_Ww_vmpy_VhRh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh)
1977
+ #define Q6_Ww_vmpy_VhRh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh)(Vu,Rt)
1979
1978
  #endif /* __HEXAGON_ARCH___ >= 60 */
1980
1979
 
1981
1980
  #if __HVX_ARCH__ >= 60
@@ -1986,29 +1985,29 @@
1986
1985
  Execution Slots: SLOT23
1987
1986
  ========================================================================== */
1988
1987
 
1989
- #define Q6_Ww_vmpyacc_WwVhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsat_acc)
1988
+ #define Q6_Ww_vmpyacc_WwVhRh_sat(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsat_acc)(Vxx,Vu,Rt)
1990
1989
  #endif /* __HEXAGON_ARCH___ >= 60 */
1991
1990
 
1992
1991
  #if __HVX_ARCH__ >= 60
1993
1992
  /* ==========================================================================
1994
1993
  Assembly Syntax: Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:rnd:sat
1995
1994
  C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_rnd_sat(HVX_Vector Vu, Word32 Rt)
1996
- Instruction Type: CVI_VX_DV
1995
+ Instruction Type: CVI_VX
1997
1996
  Execution Slots: SLOT23
1998
1997
  ========================================================================== */
1999
1998
 
2000
- #define Q6_Vh_vmpy_VhRh_s1_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsrs)
1999
+ #define Q6_Vh_vmpy_VhRh_s1_rnd_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsrs)(Vu,Rt)
2001
2000
  #endif /* __HEXAGON_ARCH___ >= 60 */
2002
2001
 
2003
2002
  #if __HVX_ARCH__ >= 60
2004
2003
  /* ==========================================================================
2005
2004
  Assembly Syntax: Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:sat
2006
2005
  C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_sat(HVX_Vector Vu, Word32 Rt)
2007
- Instruction Type: CVI_VX_DV
2006
+ Instruction Type: CVI_VX
2008
2007
  Execution Slots: SLOT23
2009
2008
  ========================================================================== */
2010
2009
 
2011
- #define Q6_Vh_vmpy_VhRh_s1_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhss)
2010
+ #define Q6_Vh_vmpy_VhRh_s1_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhss)(Vu,Rt)
2012
2011
  #endif /* __HEXAGON_ARCH___ >= 60 */
2013
2012
 
2014
2013
  #if __HVX_ARCH__ >= 60
@@ -2019,7 +2018,7 @@
2019
2018
  Execution Slots: SLOT23
2020
2019
  ========================================================================== */
2021
2020
 
2022
- #define Q6_Ww_vmpy_VhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus)
2021
+ #define Q6_Ww_vmpy_VhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus)(Vu,Vv)
2023
2022
  #endif /* __HEXAGON_ARCH___ >= 60 */
2024
2023
 
2025
2024
  #if __HVX_ARCH__ >= 60
@@ -2030,7 +2029,7 @@
2030
2029
  Execution Slots: SLOT23
2031
2030
  ========================================================================== */
2032
2031
 
2033
- #define Q6_Ww_vmpyacc_WwVhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus_acc)
2032
+ #define Q6_Ww_vmpyacc_WwVhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus_acc)(Vxx,Vu,Vv)
2034
2033
  #endif /* __HEXAGON_ARCH___ >= 60 */
2035
2034
 
2036
2035
  #if __HVX_ARCH__ >= 60
@@ -2041,7 +2040,7 @@
2041
2040
  Execution Slots: SLOT23
2042
2041
  ========================================================================== */
2043
2042
 
2044
- #define Q6_Ww_vmpy_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv)
2043
+ #define Q6_Ww_vmpy_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv)(Vu,Vv)
2045
2044
  #endif /* __HEXAGON_ARCH___ >= 60 */
2046
2045
 
2047
2046
  #if __HVX_ARCH__ >= 60
@@ -2052,18 +2051,18 @@
2052
2051
  Execution Slots: SLOT23
2053
2052
  ========================================================================== */
2054
2053
 
2055
- #define Q6_Ww_vmpyacc_WwVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv_acc)
2054
+ #define Q6_Ww_vmpyacc_WwVhVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv_acc)(Vxx,Vu,Vv)
2056
2055
  #endif /* __HEXAGON_ARCH___ >= 60 */
2057
2056
 
2058
2057
  #if __HVX_ARCH__ >= 60
2059
2058
  /* ==========================================================================
2060
2059
  Assembly Syntax: Vd32.h=vmpy(Vu32.h,Vv32.h):<<1:rnd:sat
2061
2060
  C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv)
2062
- Instruction Type: CVI_VX_DV
2061
+ Instruction Type: CVI_VX
2063
2062
  Execution Slots: SLOT23
2064
2063
  ========================================================================== */
2065
2064
 
2066
- #define Q6_Vh_vmpy_VhVh_s1_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhvsrs)
2065
+ #define Q6_Vh_vmpy_VhVh_s1_rnd_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhvsrs)(Vu,Vv)
2067
2066
  #endif /* __HEXAGON_ARCH___ >= 60 */
2068
2067
 
2069
2068
  #if __HVX_ARCH__ >= 60
@@ -2074,7 +2073,7 @@
2074
2073
  Execution Slots: SLOT23
2075
2074
  ========================================================================== */
2076
2075
 
2077
- #define Q6_Vw_vmpyieo_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyieoh)
2076
+ #define Q6_Vw_vmpyieo_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyieoh)(Vu,Vv)
2078
2077
  #endif /* __HEXAGON_ARCH___ >= 60 */
2079
2078
 
2080
2079
  #if __HVX_ARCH__ >= 60
@@ -2085,7 +2084,7 @@
2085
2084
  Execution Slots: SLOT23
2086
2085
  ========================================================================== */
2087
2086
 
2088
- #define Q6_Vw_vmpyieacc_VwVwVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewh_acc)
2087
+ #define Q6_Vw_vmpyieacc_VwVwVh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewh_acc)(Vx,Vu,Vv)
2089
2088
  #endif /* __HEXAGON_ARCH___ >= 60 */
2090
2089
 
2091
2090
  #if __HVX_ARCH__ >= 60
@@ -2096,7 +2095,7 @@
2096
2095
  Execution Slots: SLOT23
2097
2096
  ========================================================================== */
2098
2097
 
2099
- #define Q6_Vw_vmpyie_VwVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh)
2098
+ #define Q6_Vw_vmpyie_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh)(Vu,Vv)
2100
2099
  #endif /* __HEXAGON_ARCH___ >= 60 */
2101
2100
 
2102
2101
  #if __HVX_ARCH__ >= 60
@@ -2107,7 +2106,7 @@
2107
2106
  Execution Slots: SLOT23
2108
2107
  ========================================================================== */
2109
2108
 
2110
- #define Q6_Vw_vmpyieacc_VwVwVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh_acc)
2109
+ #define Q6_Vw_vmpyieacc_VwVwVuh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh_acc)(Vx,Vu,Vv)
2111
2110
  #endif /* __HEXAGON_ARCH___ >= 60 */
2112
2111
 
2113
2112
  #if __HVX_ARCH__ >= 60
@@ -2118,7 +2117,7 @@
2118
2117
  Execution Slots: SLOT23
2119
2118
  ========================================================================== */
2120
2119
 
2121
- #define Q6_Vh_vmpyi_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih)
2120
+ #define Q6_Vh_vmpyi_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih)(Vu,Vv)
2122
2121
  #endif /* __HEXAGON_ARCH___ >= 60 */
2123
2122
 
2124
2123
  #if __HVX_ARCH__ >= 60
@@ -2129,7 +2128,7 @@
2129
2128
  Execution Slots: SLOT23
2130
2129
  ========================================================================== */
2131
2130
 
2132
- #define Q6_Vh_vmpyiacc_VhVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih_acc)
2131
+ #define Q6_Vh_vmpyiacc_VhVhVh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih_acc)(Vx,Vu,Vv)
2133
2132
  #endif /* __HEXAGON_ARCH___ >= 60 */
2134
2133
 
2135
2134
  #if __HVX_ARCH__ >= 60
@@ -2140,7 +2139,7 @@
2140
2139
  Execution Slots: SLOT23
2141
2140
  ========================================================================== */
2142
2141
 
2143
- #define Q6_Vh_vmpyi_VhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb)
2142
+ #define Q6_Vh_vmpyi_VhRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb)(Vu,Rt)
2144
2143
  #endif /* __HEXAGON_ARCH___ >= 60 */
2145
2144
 
2146
2145
  #if __HVX_ARCH__ >= 60
@@ -2151,7 +2150,7 @@
2151
2150
  Execution Slots: SLOT23
2152
2151
  ========================================================================== */
2153
2152
 
2154
- #define Q6_Vh_vmpyiacc_VhVhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb_acc)
2153
+ #define Q6_Vh_vmpyiacc_VhVhRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb_acc)(Vx,Vu,Rt)
2155
2154
  #endif /* __HEXAGON_ARCH___ >= 60 */
2156
2155
 
2157
2156
  #if __HVX_ARCH__ >= 60
@@ -2162,7 +2161,7 @@
2162
2161
  Execution Slots: SLOT23
2163
2162
  ========================================================================== */
2164
2163
 
2165
- #define Q6_Vw_vmpyio_VwVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiowh)
2164
+ #define Q6_Vw_vmpyio_VwVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiowh)(Vu,Vv)
2166
2165
  #endif /* __HEXAGON_ARCH___ >= 60 */
2167
2166
 
2168
2167
  #if __HVX_ARCH__ >= 60
@@ -2173,7 +2172,7 @@
2173
2172
  Execution Slots: SLOT23
2174
2173
  ========================================================================== */
2175
2174
 
2176
- #define Q6_Vw_vmpyi_VwRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb)
2175
+ #define Q6_Vw_vmpyi_VwRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb)(Vu,Rt)
2177
2176
  #endif /* __HEXAGON_ARCH___ >= 60 */
2178
2177
 
2179
2178
  #if __HVX_ARCH__ >= 60
@@ -2184,7 +2183,7 @@
2184
2183
  Execution Slots: SLOT23
2185
2184
  ========================================================================== */
2186
2185
 
2187
- #define Q6_Vw_vmpyiacc_VwVwRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb_acc)
2186
+ #define Q6_Vw_vmpyiacc_VwVwRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb_acc)(Vx,Vu,Rt)
2188
2187
  #endif /* __HEXAGON_ARCH___ >= 60 */
2189
2188
 
2190
2189
  #if __HVX_ARCH__ >= 60
@@ -2195,7 +2194,7 @@
2195
2194
  Execution Slots: SLOT23
2196
2195
  ========================================================================== */
2197
2196
 
2198
- #define Q6_Vw_vmpyi_VwRh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh)
2197
+ #define Q6_Vw_vmpyi_VwRh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh)(Vu,Rt)
2199
2198
  #endif /* __HEXAGON_ARCH___ >= 60 */
2200
2199
 
2201
2200
  #if __HVX_ARCH__ >= 60
@@ -2206,7 +2205,7 @@
2206
2205
  Execution Slots: SLOT23
2207
2206
  ========================================================================== */
2208
2207
 
2209
- #define Q6_Vw_vmpyiacc_VwVwRh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh_acc)
2208
+ #define Q6_Vw_vmpyiacc_VwVwRh(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh_acc)(Vx,Vu,Rt)
2210
2209
  #endif /* __HEXAGON_ARCH___ >= 60 */
2211
2210
 
2212
2211
  #if __HVX_ARCH__ >= 60
@@ -2217,7 +2216,7 @@
2217
2216
  Execution Slots: SLOT23
2218
2217
  ========================================================================== */
2219
2218
 
2220
- #define Q6_Vw_vmpyo_VwVh_s1_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh)
2219
+ #define Q6_Vw_vmpyo_VwVh_s1_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh)(Vu,Vv)
2221
2220
  #endif /* __HEXAGON_ARCH___ >= 60 */
2222
2221
 
2223
2222
  #if __HVX_ARCH__ >= 60
@@ -2228,7 +2227,7 @@
2228
2227
  Execution Slots: SLOT23
2229
2228
  ========================================================================== */
2230
2229
 
2231
- #define Q6_Vw_vmpyo_VwVh_s1_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd)
2230
+ #define Q6_Vw_vmpyo_VwVh_s1_rnd_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd)(Vu,Vv)
2232
2231
  #endif /* __HEXAGON_ARCH___ >= 60 */
2233
2232
 
2234
2233
  #if __HVX_ARCH__ >= 60
@@ -2239,7 +2238,7 @@
2239
2238
  Execution Slots: SLOT23
2240
2239
  ========================================================================== */
2241
2240
 
2242
- #define Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd_sacc)
2241
+ #define Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd_sacc)(Vx,Vu,Vv)
2243
2242
  #endif /* __HEXAGON_ARCH___ >= 60 */
2244
2243
 
2245
2244
  #if __HVX_ARCH__ >= 60
@@ -2250,7 +2249,7 @@
2250
2249
  Execution Slots: SLOT23
2251
2250
  ========================================================================== */
2252
2251
 
2253
- #define Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_sacc)
2252
+ #define Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_sacc)(Vx,Vu,Vv)
2254
2253
  #endif /* __HEXAGON_ARCH___ >= 60 */
2255
2254
 
2256
2255
  #if __HVX_ARCH__ >= 60
@@ -2261,7 +2260,7 @@
2261
2260
  Execution Slots: SLOT23
2262
2261
  ========================================================================== */
2263
2262
 
2264
- #define Q6_Wuh_vmpy_VubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub)
2263
+ #define Q6_Wuh_vmpy_VubRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub)(Vu,Rt)
2265
2264
  #endif /* __HEXAGON_ARCH___ >= 60 */
2266
2265
 
2267
2266
  #if __HVX_ARCH__ >= 60
@@ -2272,7 +2271,7 @@
2272
2271
  Execution Slots: SLOT23
2273
2272
  ========================================================================== */
2274
2273
 
2275
- #define Q6_Wuh_vmpyacc_WuhVubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub_acc)
2274
+ #define Q6_Wuh_vmpyacc_WuhVubRub(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub_acc)(Vxx,Vu,Rt)
2276
2275
  #endif /* __HEXAGON_ARCH___ >= 60 */
2277
2276
 
2278
2277
  #if __HVX_ARCH__ >= 60
@@ -2283,7 +2282,7 @@
2283
2282
  Execution Slots: SLOT23
2284
2283
  ========================================================================== */
2285
2284
 
2286
- #define Q6_Wuh_vmpy_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv)
2285
+ #define Q6_Wuh_vmpy_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv)(Vu,Vv)
2287
2286
  #endif /* __HEXAGON_ARCH___ >= 60 */
2288
2287
 
2289
2288
  #if __HVX_ARCH__ >= 60
@@ -2294,7 +2293,7 @@
2294
2293
  Execution Slots: SLOT23
2295
2294
  ========================================================================== */
2296
2295
 
2297
- #define Q6_Wuh_vmpyacc_WuhVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv_acc)
2296
+ #define Q6_Wuh_vmpyacc_WuhVubVub(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv_acc)(Vxx,Vu,Vv)
2298
2297
  #endif /* __HEXAGON_ARCH___ >= 60 */
2299
2298
 
2300
2299
  #if __HVX_ARCH__ >= 60
@@ -2305,7 +2304,7 @@
2305
2304
  Execution Slots: SLOT23
2306
2305
  ========================================================================== */
2307
2306
 
2308
- #define Q6_Wuw_vmpy_VuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh)
2307
+ #define Q6_Wuw_vmpy_VuhRuh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh)(Vu,Rt)
2309
2308
  #endif /* __HEXAGON_ARCH___ >= 60 */
2310
2309
 
2311
2310
  #if __HVX_ARCH__ >= 60
@@ -2316,7 +2315,7 @@
2316
2315
  Execution Slots: SLOT23
2317
2316
  ========================================================================== */
2318
2317
 
2319
- #define Q6_Wuw_vmpyacc_WuwVuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh_acc)
2318
+ #define Q6_Wuw_vmpyacc_WuwVuhRuh(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh_acc)(Vxx,Vu,Rt)
2320
2319
  #endif /* __HEXAGON_ARCH___ >= 60 */
2321
2320
 
2322
2321
  #if __HVX_ARCH__ >= 60
@@ -2327,7 +2326,7 @@
2327
2326
  Execution Slots: SLOT23
2328
2327
  ========================================================================== */
2329
2328
 
2330
- #define Q6_Wuw_vmpy_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv)
2329
+ #define Q6_Wuw_vmpy_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv)(Vu,Vv)
2331
2330
  #endif /* __HEXAGON_ARCH___ >= 60 */
2332
2331
 
2333
2332
  #if __HVX_ARCH__ >= 60
@@ -2338,7 +2337,7 @@
2338
2337
  Execution Slots: SLOT23
2339
2338
  ========================================================================== */
2340
2339
 
2341
- #define Q6_Wuw_vmpyacc_WuwVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv_acc)
2340
+ #define Q6_Wuw_vmpyacc_WuwVuhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv_acc)(Vxx,Vu,Vv)
2342
2341
  #endif /* __HEXAGON_ARCH___ >= 60 */
2343
2342
 
2344
2343
  #if __HVX_ARCH__ >= 60
@@ -2349,7 +2348,7 @@
2349
2348
  Execution Slots: SLOT0123
2350
2349
  ========================================================================== */
2351
2350
 
2352
- #define Q6_V_vmux_QVV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmux)
2351
+ #define Q6_V_vmux_QVV(Qt,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmux)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1),Vu,Vv)
2353
2352
  #endif /* __HEXAGON_ARCH___ >= 60 */
2354
2353
 
2355
2354
  #if __HVX_ARCH__ >= 60
@@ -2360,7 +2359,7 @@
2360
2359
  Execution Slots: SLOT0123
2361
2360
  ========================================================================== */
2362
2361
 
2363
- #define Q6_Vh_vnavg_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgh)
2362
+ #define Q6_Vh_vnavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgh)(Vu,Vv)
2364
2363
  #endif /* __HEXAGON_ARCH___ >= 60 */
2365
2364
 
2366
2365
  #if __HVX_ARCH__ >= 60
@@ -2371,7 +2370,7 @@
2371
2370
  Execution Slots: SLOT0123
2372
2371
  ========================================================================== */
2373
2372
 
2374
- #define Q6_Vb_vnavg_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgub)
2373
+ #define Q6_Vb_vnavg_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgub)(Vu,Vv)
2375
2374
  #endif /* __HEXAGON_ARCH___ >= 60 */
2376
2375
 
2377
2376
  #if __HVX_ARCH__ >= 60
@@ -2382,7 +2381,7 @@
2382
2381
  Execution Slots: SLOT0123
2383
2382
  ========================================================================== */
2384
2383
 
2385
- #define Q6_Vw_vnavg_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgw)
2384
+ #define Q6_Vw_vnavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgw)(Vu,Vv)
2386
2385
  #endif /* __HEXAGON_ARCH___ >= 60 */
2387
2386
 
2388
2387
  #if __HVX_ARCH__ >= 60
@@ -2393,7 +2392,7 @@
2393
2392
  Execution Slots: SLOT0123
2394
2393
  ========================================================================== */
2395
2394
 
2396
- #define Q6_Vh_vnormamt_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamth)
2395
+ #define Q6_Vh_vnormamt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamth)(Vu)
2397
2396
  #endif /* __HEXAGON_ARCH___ >= 60 */
2398
2397
 
2399
2398
  #if __HVX_ARCH__ >= 60
@@ -2404,7 +2403,7 @@
2404
2403
  Execution Slots: SLOT0123
2405
2404
  ========================================================================== */
2406
2405
 
2407
- #define Q6_Vw_vnormamt_Vw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamtw)
2406
+ #define Q6_Vw_vnormamt_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamtw)(Vu)
2408
2407
  #endif /* __HEXAGON_ARCH___ >= 60 */
2409
2408
 
2410
2409
  #if __HVX_ARCH__ >= 60
@@ -2415,7 +2414,7 @@
2415
2414
  Execution Slots: SLOT0123
2416
2415
  ========================================================================== */
2417
2416
 
2418
- #define Q6_V_vnot_V __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnot)
2417
+ #define Q6_V_vnot_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnot)(Vu)
2419
2418
  #endif /* __HEXAGON_ARCH___ >= 60 */
2420
2419
 
2421
2420
  #if __HVX_ARCH__ >= 60
@@ -2426,7 +2425,7 @@
2426
2425
  Execution Slots: SLOT0123
2427
2426
  ========================================================================== */
2428
2427
 
2429
- #define Q6_V_vor_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vor)
2428
+ #define Q6_V_vor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vor)(Vu,Vv)
2430
2429
  #endif /* __HEXAGON_ARCH___ >= 60 */
2431
2430
 
2432
2431
  #if __HVX_ARCH__ >= 60
@@ -2437,7 +2436,7 @@
2437
2436
  Execution Slots: SLOT0123
2438
2437
  ========================================================================== */
2439
2438
 
2440
- #define Q6_Vb_vpacke_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeb)
2439
+ #define Q6_Vb_vpacke_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeb)(Vu,Vv)
2441
2440
  #endif /* __HEXAGON_ARCH___ >= 60 */
2442
2441
 
2443
2442
  #if __HVX_ARCH__ >= 60
@@ -2448,7 +2447,7 @@
2448
2447
  Execution Slots: SLOT0123
2449
2448
  ========================================================================== */
2450
2449
 
2451
- #define Q6_Vh_vpacke_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeh)
2450
+ #define Q6_Vh_vpacke_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeh)(Vu,Vv)
2452
2451
  #endif /* __HEXAGON_ARCH___ >= 60 */
2453
2452
 
2454
2453
  #if __HVX_ARCH__ >= 60
@@ -2459,7 +2458,7 @@
2459
2458
  Execution Slots: SLOT0123
2460
2459
  ========================================================================== */
2461
2460
 
2462
- #define Q6_Vb_vpack_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhb_sat)
2461
+ #define Q6_Vb_vpack_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhb_sat)(Vu,Vv)
2463
2462
  #endif /* __HEXAGON_ARCH___ >= 60 */
2464
2463
 
2465
2464
  #if __HVX_ARCH__ >= 60
@@ -2470,7 +2469,7 @@
2470
2469
  Execution Slots: SLOT0123
2471
2470
  ========================================================================== */
2472
2471
 
2473
- #define Q6_Vub_vpack_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhub_sat)
2472
+ #define Q6_Vub_vpack_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhub_sat)(Vu,Vv)
2474
2473
  #endif /* __HEXAGON_ARCH___ >= 60 */
2475
2474
 
2476
2475
  #if __HVX_ARCH__ >= 60
@@ -2481,7 +2480,7 @@
2481
2480
  Execution Slots: SLOT0123
2482
2481
  ========================================================================== */
2483
2482
 
2484
- #define Q6_Vb_vpacko_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackob)
2483
+ #define Q6_Vb_vpacko_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackob)(Vu,Vv)
2485
2484
  #endif /* __HEXAGON_ARCH___ >= 60 */
2486
2485
 
2487
2486
  #if __HVX_ARCH__ >= 60
@@ -2492,7 +2491,7 @@
2492
2491
  Execution Slots: SLOT0123
2493
2492
  ========================================================================== */
2494
2493
 
2495
- #define Q6_Vh_vpacko_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackoh)
2494
+ #define Q6_Vh_vpacko_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackoh)(Vu,Vv)
2496
2495
  #endif /* __HEXAGON_ARCH___ >= 60 */
2497
2496
 
2498
2497
  #if __HVX_ARCH__ >= 60
@@ -2503,7 +2502,7 @@
2503
2502
  Execution Slots: SLOT0123
2504
2503
  ========================================================================== */
2505
2504
 
2506
- #define Q6_Vh_vpack_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwh_sat)
2505
+ #define Q6_Vh_vpack_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwh_sat)(Vu,Vv)
2507
2506
  #endif /* __HEXAGON_ARCH___ >= 60 */
2508
2507
 
2509
2508
  #if __HVX_ARCH__ >= 60
@@ -2514,7 +2513,7 @@
2514
2513
  Execution Slots: SLOT0123
2515
2514
  ========================================================================== */
2516
2515
 
2517
- #define Q6_Vuh_vpack_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwuh_sat)
2516
+ #define Q6_Vuh_vpack_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwuh_sat)(Vu,Vv)
2518
2517
  #endif /* __HEXAGON_ARCH___ >= 60 */
2519
2518
 
2520
2519
  #if __HVX_ARCH__ >= 60
@@ -2525,7 +2524,7 @@
2525
2524
  Execution Slots: SLOT0123
2526
2525
  ========================================================================== */
2527
2526
 
2528
- #define Q6_Vh_vpopcount_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpopcounth)
2527
+ #define Q6_Vh_vpopcount_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpopcounth)(Vu)
2529
2528
  #endif /* __HEXAGON_ARCH___ >= 60 */
2530
2529
 
2531
2530
  #if __HVX_ARCH__ >= 60
@@ -2536,7 +2535,7 @@
2536
2535
  Execution Slots: SLOT0123
2537
2536
  ========================================================================== */
2538
2537
 
2539
- #define Q6_V_vrdelta_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrdelta)
2538
+ #define Q6_V_vrdelta_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrdelta)(Vu,Vv)
2540
2539
  #endif /* __HEXAGON_ARCH___ >= 60 */
2541
2540
 
2542
2541
  #if __HVX_ARCH__ >= 60
@@ -2547,7 +2546,7 @@
2547
2546
  Execution Slots: SLOT23
2548
2547
  ========================================================================== */
2549
2548
 
2550
- #define Q6_Vw_vrmpy_VubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus)
2549
+ #define Q6_Vw_vrmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus)(Vu,Rt)
2551
2550
  #endif /* __HEXAGON_ARCH___ >= 60 */
2552
2551
 
2553
2552
  #if __HVX_ARCH__ >= 60
@@ -2558,7 +2557,7 @@
2558
2557
  Execution Slots: SLOT23
2559
2558
  ========================================================================== */
2560
2559
 
2561
- #define Q6_Vw_vrmpyacc_VwVubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus_acc)
2560
+ #define Q6_Vw_vrmpyacc_VwVubRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus_acc)(Vx,Vu,Rt)
2562
2561
  #endif /* __HEXAGON_ARCH___ >= 60 */
2563
2562
 
2564
2563
  #if __HVX_ARCH__ >= 60
@@ -2569,7 +2568,7 @@
2569
2568
  Execution Slots: SLOT23
2570
2569
  ========================================================================== */
2571
2570
 
2572
- #define Q6_Ww_vrmpy_WubRbI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi)
2571
+ #define Q6_Ww_vrmpy_WubRbI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi)(Vuu,Rt,Iu1)
2573
2572
  #endif /* __HEXAGON_ARCH___ >= 60 */
2574
2573
 
2575
2574
  #if __HVX_ARCH__ >= 60
@@ -2580,7 +2579,7 @@
2580
2579
  Execution Slots: SLOT23
2581
2580
  ========================================================================== */
2582
2581
 
2583
- #define Q6_Ww_vrmpyacc_WwWubRbI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi_acc)
2582
+ #define Q6_Ww_vrmpyacc_WwWubRbI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi_acc)(Vxx,Vuu,Rt,Iu1)
2584
2583
  #endif /* __HEXAGON_ARCH___ >= 60 */
2585
2584
 
2586
2585
  #if __HVX_ARCH__ >= 60
@@ -2591,18 +2590,18 @@
2591
2590
  Execution Slots: SLOT23
2592
2591
  ========================================================================== */
2593
2592
 
2594
- #define Q6_Vw_vrmpy_VubVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv)
2593
+ #define Q6_Vw_vrmpy_VubVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv)(Vu,Vv)
2595
2594
  #endif /* __HEXAGON_ARCH___ >= 60 */
2596
2595
 
2597
2596
  #if __HVX_ARCH__ >= 60
2598
2597
  /* ==========================================================================
2599
2598
  Assembly Syntax: Vx32.w+=vrmpy(Vu32.ub,Vv32.b)
2600
2599
  C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
2601
- Instruction Type: CVI_VX_DV
2600
+ Instruction Type: CVI_VX
2602
2601
  Execution Slots: SLOT23
2603
2602
  ========================================================================== */
2604
2603
 
2605
- #define Q6_Vw_vrmpyacc_VwVubVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv_acc)
2604
+ #define Q6_Vw_vrmpyacc_VwVubVb(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv_acc)(Vx,Vu,Vv)
2606
2605
  #endif /* __HEXAGON_ARCH___ >= 60 */
2607
2606
 
2608
2607
  #if __HVX_ARCH__ >= 60
@@ -2613,18 +2612,18 @@
2613
2612
  Execution Slots: SLOT23
2614
2613
  ========================================================================== */
2615
2614
 
2616
- #define Q6_Vw_vrmpy_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv)
2615
+ #define Q6_Vw_vrmpy_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv)(Vu,Vv)
2617
2616
  #endif /* __HEXAGON_ARCH___ >= 60 */
2618
2617
 
2619
2618
  #if __HVX_ARCH__ >= 60
2620
2619
  /* ==========================================================================
2621
2620
  Assembly Syntax: Vx32.w+=vrmpy(Vu32.b,Vv32.b)
2622
2621
  C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVbVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
2623
- Instruction Type: CVI_VX_DV
2622
+ Instruction Type: CVI_VX
2624
2623
  Execution Slots: SLOT23
2625
2624
  ========================================================================== */
2626
2625
 
2627
- #define Q6_Vw_vrmpyacc_VwVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv_acc)
2626
+ #define Q6_Vw_vrmpyacc_VwVbVb(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv_acc)(Vx,Vu,Vv)
2628
2627
  #endif /* __HEXAGON_ARCH___ >= 60 */
2629
2628
 
2630
2629
  #if __HVX_ARCH__ >= 60
@@ -2635,7 +2634,7 @@
2635
2634
  Execution Slots: SLOT23
2636
2635
  ========================================================================== */
2637
2636
 
2638
- #define Q6_Vuw_vrmpy_VubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub)
2637
+ #define Q6_Vuw_vrmpy_VubRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub)(Vu,Rt)
2639
2638
  #endif /* __HEXAGON_ARCH___ >= 60 */
2640
2639
 
2641
2640
  #if __HVX_ARCH__ >= 60
@@ -2646,7 +2645,7 @@
2646
2645
  Execution Slots: SLOT23
2647
2646
  ========================================================================== */
2648
2647
 
2649
- #define Q6_Vuw_vrmpyacc_VuwVubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub_acc)
2648
+ #define Q6_Vuw_vrmpyacc_VuwVubRub(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub_acc)(Vx,Vu,Rt)
2650
2649
  #endif /* __HEXAGON_ARCH___ >= 60 */
2651
2650
 
2652
2651
  #if __HVX_ARCH__ >= 60
@@ -2657,7 +2656,7 @@
2657
2656
  Execution Slots: SLOT23
2658
2657
  ========================================================================== */
2659
2658
 
2660
- #define Q6_Wuw_vrmpy_WubRubI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi)
2659
+ #define Q6_Wuw_vrmpy_WubRubI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi)(Vuu,Rt,Iu1)
2661
2660
  #endif /* __HEXAGON_ARCH___ >= 60 */
2662
2661
 
2663
2662
  #if __HVX_ARCH__ >= 60
@@ -2668,7 +2667,7 @@
2668
2667
  Execution Slots: SLOT23
2669
2668
  ========================================================================== */
2670
2669
 
2671
- #define Q6_Wuw_vrmpyacc_WuwWubRubI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi_acc)
2670
+ #define Q6_Wuw_vrmpyacc_WuwWubRubI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi_acc)(Vxx,Vuu,Rt,Iu1)
2672
2671
  #endif /* __HEXAGON_ARCH___ >= 60 */
2673
2672
 
2674
2673
  #if __HVX_ARCH__ >= 60
@@ -2679,18 +2678,18 @@
2679
2678
  Execution Slots: SLOT23
2680
2679
  ========================================================================== */
2681
2680
 
2682
- #define Q6_Vuw_vrmpy_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv)
2681
+ #define Q6_Vuw_vrmpy_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv)(Vu,Vv)
2683
2682
  #endif /* __HEXAGON_ARCH___ >= 60 */
2684
2683
 
2685
2684
  #if __HVX_ARCH__ >= 60
2686
2685
  /* ==========================================================================
2687
2686
  Assembly Syntax: Vx32.uw+=vrmpy(Vu32.ub,Vv32.ub)
2688
2687
  C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubVub(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
2689
- Instruction Type: CVI_VX_DV
2688
+ Instruction Type: CVI_VX
2690
2689
  Execution Slots: SLOT23
2691
2690
  ========================================================================== */
2692
2691
 
2693
- #define Q6_Vuw_vrmpyacc_VuwVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv_acc)
2692
+ #define Q6_Vuw_vrmpyacc_VuwVubVub(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv_acc)(Vx,Vu,Vv)
2694
2693
  #endif /* __HEXAGON_ARCH___ >= 60 */
2695
2694
 
2696
2695
  #if __HVX_ARCH__ >= 60
@@ -2701,7 +2700,7 @@
2701
2700
  Execution Slots: SLOT0123
2702
2701
  ========================================================================== */
2703
2702
 
2704
- #define Q6_V_vror_VR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vror)
2703
+ #define Q6_V_vror_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vror)(Vu,Rt)
2705
2704
  #endif /* __HEXAGON_ARCH___ >= 60 */
2706
2705
 
2707
2706
  #if __HVX_ARCH__ >= 60
@@ -2712,7 +2711,7 @@
2712
2711
  Execution Slots: SLOT0123
2713
2712
  ========================================================================== */
2714
2713
 
2715
- #define Q6_Vb_vround_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhb)
2714
+ #define Q6_Vb_vround_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhb)(Vu,Vv)
2716
2715
  #endif /* __HEXAGON_ARCH___ >= 60 */
2717
2716
 
2718
2717
  #if __HVX_ARCH__ >= 60
@@ -2723,7 +2722,7 @@
2723
2722
  Execution Slots: SLOT0123
2724
2723
  ========================================================================== */
2725
2724
 
2726
- #define Q6_Vub_vround_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhub)
2725
+ #define Q6_Vub_vround_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhub)(Vu,Vv)
2727
2726
  #endif /* __HEXAGON_ARCH___ >= 60 */
2728
2727
 
2729
2728
  #if __HVX_ARCH__ >= 60
@@ -2734,7 +2733,7 @@
2734
2733
  Execution Slots: SLOT0123
2735
2734
  ========================================================================== */
2736
2735
 
2737
- #define Q6_Vh_vround_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwh)
2736
+ #define Q6_Vh_vround_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwh)(Vu,Vv)
2738
2737
  #endif /* __HEXAGON_ARCH___ >= 60 */
2739
2738
 
2740
2739
  #if __HVX_ARCH__ >= 60
@@ -2745,7 +2744,7 @@
2745
2744
  Execution Slots: SLOT0123
2746
2745
  ========================================================================== */
2747
2746
 
2748
- #define Q6_Vuh_vround_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwuh)
2747
+ #define Q6_Vuh_vround_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwuh)(Vu,Vv)
2749
2748
  #endif /* __HEXAGON_ARCH___ >= 60 */
2750
2749
 
2751
2750
  #if __HVX_ARCH__ >= 60
@@ -2756,7 +2755,7 @@
2756
2755
  Execution Slots: SLOT23
2757
2756
  ========================================================================== */
2758
2757
 
2759
- #define Q6_Wuw_vrsad_WubRubI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi)
2758
+ #define Q6_Wuw_vrsad_WubRubI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi)(Vuu,Rt,Iu1)
2760
2759
  #endif /* __HEXAGON_ARCH___ >= 60 */
2761
2760
 
2762
2761
  #if __HVX_ARCH__ >= 60
@@ -2767,7 +2766,7 @@
2767
2766
  Execution Slots: SLOT23
2768
2767
  ========================================================================== */
2769
2768
 
2770
- #define Q6_Wuw_vrsadacc_WuwWubRubI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi_acc)
2769
+ #define Q6_Wuw_vrsadacc_WuwWubRubI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi_acc)(Vxx,Vuu,Rt,Iu1)
2771
2770
  #endif /* __HEXAGON_ARCH___ >= 60 */
2772
2771
 
2773
2772
  #if __HVX_ARCH__ >= 60
@@ -2778,7 +2777,7 @@
2778
2777
  Execution Slots: SLOT0123
2779
2778
  ========================================================================== */
2780
2779
 
2781
- #define Q6_Vub_vsat_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsathub)
2780
+ #define Q6_Vub_vsat_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsathub)(Vu,Vv)
2782
2781
  #endif /* __HEXAGON_ARCH___ >= 60 */
2783
2782
 
2784
2783
  #if __HVX_ARCH__ >= 60
@@ -2789,7 +2788,7 @@
2789
2788
  Execution Slots: SLOT0123
2790
2789
  ========================================================================== */
2791
2790
 
2792
- #define Q6_Vh_vsat_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatwh)
2791
+ #define Q6_Vh_vsat_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatwh)(Vu,Vv)
2793
2792
  #endif /* __HEXAGON_ARCH___ >= 60 */
2794
2793
 
2795
2794
  #if __HVX_ARCH__ >= 60
@@ -2800,7 +2799,7 @@
2800
2799
  Execution Slots: SLOT0123
2801
2800
  ========================================================================== */
2802
2801
 
2803
- #define Q6_Wh_vsxt_Vb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsb)
2802
+ #define Q6_Wh_vsxt_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsb)(Vu)
2804
2803
  #endif /* __HEXAGON_ARCH___ >= 60 */
2805
2804
 
2806
2805
  #if __HVX_ARCH__ >= 60
@@ -2811,7 +2810,7 @@
2811
2810
  Execution Slots: SLOT0123
2812
2811
  ========================================================================== */
2813
2812
 
2814
- #define Q6_Ww_vsxt_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsh)
2813
+ #define Q6_Ww_vsxt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsh)(Vu)
2815
2814
  #endif /* __HEXAGON_ARCH___ >= 60 */
2816
2815
 
2817
2816
  #if __HVX_ARCH__ >= 60
@@ -2822,7 +2821,7 @@
2822
2821
  Execution Slots: SLOT0123
2823
2822
  ========================================================================== */
2824
2823
 
2825
- #define Q6_Vh_vshuffe_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufeh)
2824
+ #define Q6_Vh_vshuffe_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufeh)(Vu,Vv)
2826
2825
  #endif /* __HEXAGON_ARCH___ >= 60 */
2827
2826
 
2828
2827
  #if __HVX_ARCH__ >= 60
@@ -2833,7 +2832,7 @@
2833
2832
  Execution Slots: SLOT0123
2834
2833
  ========================================================================== */
2835
2834
 
2836
- #define Q6_Vb_vshuff_Vb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffb)
2835
+ #define Q6_Vb_vshuff_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffb)(Vu)
2837
2836
  #endif /* __HEXAGON_ARCH___ >= 60 */
2838
2837
 
2839
2838
  #if __HVX_ARCH__ >= 60
@@ -2844,7 +2843,7 @@
2844
2843
  Execution Slots: SLOT0123
2845
2844
  ========================================================================== */
2846
2845
 
2847
- #define Q6_Vb_vshuffe_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffeb)
2846
+ #define Q6_Vb_vshuffe_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffeb)(Vu,Vv)
2848
2847
  #endif /* __HEXAGON_ARCH___ >= 60 */
2849
2848
 
2850
2849
  #if __HVX_ARCH__ >= 60
@@ -2855,7 +2854,7 @@
2855
2854
  Execution Slots: SLOT0123
2856
2855
  ========================================================================== */
2857
2856
 
2858
- #define Q6_Vh_vshuff_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffh)
2857
+ #define Q6_Vh_vshuff_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffh)(Vu)
2859
2858
  #endif /* __HEXAGON_ARCH___ >= 60 */
2860
2859
 
2861
2860
  #if __HVX_ARCH__ >= 60
@@ -2866,7 +2865,7 @@
2866
2865
  Execution Slots: SLOT0123
2867
2866
  ========================================================================== */
2868
2867
 
2869
- #define Q6_Vb_vshuffo_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffob)
2868
+ #define Q6_Vb_vshuffo_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffob)(Vu,Vv)
2870
2869
  #endif /* __HEXAGON_ARCH___ >= 60 */
2871
2870
 
2872
2871
  #if __HVX_ARCH__ >= 60
@@ -2877,7 +2876,7 @@
2877
2876
  Execution Slots: SLOT0123
2878
2877
  ========================================================================== */
2879
2878
 
2880
- #define Q6_W_vshuff_VVR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffvdd)
2879
+ #define Q6_W_vshuff_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffvdd)(Vu,Vv,Rt)
2881
2880
  #endif /* __HEXAGON_ARCH___ >= 60 */
2882
2881
 
2883
2882
  #if __HVX_ARCH__ >= 60
@@ -2888,7 +2887,7 @@
2888
2887
  Execution Slots: SLOT0123
2889
2888
  ========================================================================== */
2890
2889
 
2891
- #define Q6_Wb_vshuffoe_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeb)
2890
+ #define Q6_Wb_vshuffoe_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeb)(Vu,Vv)
2892
2891
  #endif /* __HEXAGON_ARCH___ >= 60 */
2893
2892
 
2894
2893
  #if __HVX_ARCH__ >= 60
@@ -2899,7 +2898,7 @@
2899
2898
  Execution Slots: SLOT0123
2900
2899
  ========================================================================== */
2901
2900
 
2902
- #define Q6_Wh_vshuffoe_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeh)
2901
+ #define Q6_Wh_vshuffoe_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeh)(Vu,Vv)
2903
2902
  #endif /* __HEXAGON_ARCH___ >= 60 */
2904
2903
 
2905
2904
  #if __HVX_ARCH__ >= 60
@@ -2910,7 +2909,7 @@
2910
2909
  Execution Slots: SLOT0123
2911
2910
  ========================================================================== */
2912
2911
 
2913
- #define Q6_Vh_vshuffo_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoh)
2912
+ #define Q6_Vh_vshuffo_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoh)(Vu,Vv)
2914
2913
  #endif /* __HEXAGON_ARCH___ >= 60 */
2915
2914
 
2916
2915
  #if __HVX_ARCH__ >= 60
@@ -2921,7 +2920,7 @@
2921
2920
  Execution Slots: SLOT0123
2922
2921
  ========================================================================== */
2923
2922
 
2924
- #define Q6_Vb_vsub_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb)
2923
+ #define Q6_Vb_vsub_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb)(Vu,Vv)
2925
2924
  #endif /* __HEXAGON_ARCH___ >= 60 */
2926
2925
 
2927
2926
  #if __HVX_ARCH__ >= 60
@@ -2932,7 +2931,7 @@
2932
2931
  Execution Slots: SLOT0123
2933
2932
  ========================================================================== */
2934
2933
 
2935
- #define Q6_Wb_vsub_WbWb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb_dv)
2934
+ #define Q6_Wb_vsub_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb_dv)(Vuu,Vvv)
2936
2935
  #endif /* __HEXAGON_ARCH___ >= 60 */
2937
2936
 
2938
2937
  #if __HVX_ARCH__ >= 60
@@ -2943,7 +2942,7 @@
2943
2942
  Execution Slots: SLOT0123
2944
2943
  ========================================================================== */
2945
2944
 
2946
- #define Q6_Vb_condnac_QnVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbnq)
2945
+ #define Q6_Vb_condnac_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
2947
2946
  #endif /* __HEXAGON_ARCH___ >= 60 */
2948
2947
 
2949
2948
  #if __HVX_ARCH__ >= 60
@@ -2954,7 +2953,7 @@
2954
2953
  Execution Slots: SLOT0123
2955
2954
  ========================================================================== */
2956
2955
 
2957
- #define Q6_Vb_condnac_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbq)
2956
+ #define Q6_Vb_condnac_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
2958
2957
  #endif /* __HEXAGON_ARCH___ >= 60 */
2959
2958
 
2960
2959
  #if __HVX_ARCH__ >= 60
@@ -2965,7 +2964,7 @@
2965
2964
  Execution Slots: SLOT0123
2966
2965
  ========================================================================== */
2967
2966
 
2968
- #define Q6_Vh_vsub_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh)
2967
+ #define Q6_Vh_vsub_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh)(Vu,Vv)
2969
2968
  #endif /* __HEXAGON_ARCH___ >= 60 */
2970
2969
 
2971
2970
  #if __HVX_ARCH__ >= 60
@@ -2976,7 +2975,7 @@
2976
2975
  Execution Slots: SLOT0123
2977
2976
  ========================================================================== */
2978
2977
 
2979
- #define Q6_Wh_vsub_WhWh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh_dv)
2978
+ #define Q6_Wh_vsub_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh_dv)(Vuu,Vvv)
2980
2979
  #endif /* __HEXAGON_ARCH___ >= 60 */
2981
2980
 
2982
2981
  #if __HVX_ARCH__ >= 60
@@ -2987,7 +2986,7 @@
2987
2986
  Execution Slots: SLOT0123
2988
2987
  ========================================================================== */
2989
2988
 
2990
- #define Q6_Vh_condnac_QnVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhnq)
2989
+ #define Q6_Vh_condnac_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
2991
2990
  #endif /* __HEXAGON_ARCH___ >= 60 */
2992
2991
 
2993
2992
  #if __HVX_ARCH__ >= 60
@@ -2998,7 +2997,7 @@
2998
2997
  Execution Slots: SLOT0123
2999
2998
  ========================================================================== */
3000
2999
 
3001
- #define Q6_Vh_condnac_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhq)
3000
+ #define Q6_Vh_condnac_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
3002
3001
  #endif /* __HEXAGON_ARCH___ >= 60 */
3003
3002
 
3004
3003
  #if __HVX_ARCH__ >= 60
@@ -3009,7 +3008,7 @@
3009
3008
  Execution Slots: SLOT0123
3010
3009
  ========================================================================== */
3011
3010
 
3012
- #define Q6_Vh_vsub_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat)
3011
+ #define Q6_Vh_vsub_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat)(Vu,Vv)
3013
3012
  #endif /* __HEXAGON_ARCH___ >= 60 */
3014
3013
 
3015
3014
  #if __HVX_ARCH__ >= 60
@@ -3020,7 +3019,7 @@
3020
3019
  Execution Slots: SLOT0123
3021
3020
  ========================================================================== */
3022
3021
 
3023
- #define Q6_Wh_vsub_WhWh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat_dv)
3022
+ #define Q6_Wh_vsub_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat_dv)(Vuu,Vvv)
3024
3023
  #endif /* __HEXAGON_ARCH___ >= 60 */
3025
3024
 
3026
3025
  #if __HVX_ARCH__ >= 60
@@ -3031,7 +3030,7 @@
3031
3030
  Execution Slots: SLOT23
3032
3031
  ========================================================================== */
3033
3032
 
3034
- #define Q6_Ww_vsub_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhw)
3033
+ #define Q6_Ww_vsub_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhw)(Vu,Vv)
3035
3034
  #endif /* __HEXAGON_ARCH___ >= 60 */
3036
3035
 
3037
3036
  #if __HVX_ARCH__ >= 60
@@ -3042,7 +3041,7 @@
3042
3041
  Execution Slots: SLOT23
3043
3042
  ========================================================================== */
3044
3043
 
3045
- #define Q6_Wh_vsub_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububh)
3044
+ #define Q6_Wh_vsub_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububh)(Vu,Vv)
3046
3045
  #endif /* __HEXAGON_ARCH___ >= 60 */
3047
3046
 
3048
3047
  #if __HVX_ARCH__ >= 60
@@ -3053,7 +3052,7 @@
3053
3052
  Execution Slots: SLOT0123
3054
3053
  ========================================================================== */
3055
3054
 
3056
- #define Q6_Vub_vsub_VubVub_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat)
3055
+ #define Q6_Vub_vsub_VubVub_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat)(Vu,Vv)
3057
3056
  #endif /* __HEXAGON_ARCH___ >= 60 */
3058
3057
 
3059
3058
  #if __HVX_ARCH__ >= 60
@@ -3064,7 +3063,7 @@
3064
3063
  Execution Slots: SLOT0123
3065
3064
  ========================================================================== */
3066
3065
 
3067
- #define Q6_Wub_vsub_WubWub_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat_dv)
3066
+ #define Q6_Wub_vsub_WubWub_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat_dv)(Vuu,Vvv)
3068
3067
  #endif /* __HEXAGON_ARCH___ >= 60 */
3069
3068
 
3070
3069
  #if __HVX_ARCH__ >= 60
@@ -3075,7 +3074,7 @@
3075
3074
  Execution Slots: SLOT0123
3076
3075
  ========================================================================== */
3077
3076
 
3078
- #define Q6_Vuh_vsub_VuhVuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat)
3077
+ #define Q6_Vuh_vsub_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat)(Vu,Vv)
3079
3078
  #endif /* __HEXAGON_ARCH___ >= 60 */
3080
3079
 
3081
3080
  #if __HVX_ARCH__ >= 60
@@ -3086,7 +3085,7 @@
3086
3085
  Execution Slots: SLOT0123
3087
3086
  ========================================================================== */
3088
3087
 
3089
- #define Q6_Wuh_vsub_WuhWuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat_dv)
3088
+ #define Q6_Wuh_vsub_WuhWuh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat_dv)(Vuu,Vvv)
3090
3089
  #endif /* __HEXAGON_ARCH___ >= 60 */
3091
3090
 
3092
3091
  #if __HVX_ARCH__ >= 60
@@ -3097,7 +3096,7 @@
3097
3096
  Execution Slots: SLOT23
3098
3097
  ========================================================================== */
3099
3098
 
3100
- #define Q6_Ww_vsub_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhw)
3099
+ #define Q6_Ww_vsub_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhw)(Vu,Vv)
3101
3100
  #endif /* __HEXAGON_ARCH___ >= 60 */
3102
3101
 
3103
3102
  #if __HVX_ARCH__ >= 60
@@ -3108,7 +3107,7 @@
3108
3107
  Execution Slots: SLOT0123
3109
3108
  ========================================================================== */
3110
3109
 
3111
- #define Q6_Vw_vsub_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw)
3110
+ #define Q6_Vw_vsub_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw)(Vu,Vv)
3112
3111
  #endif /* __HEXAGON_ARCH___ >= 60 */
3113
3112
 
3114
3113
  #if __HVX_ARCH__ >= 60
@@ -3119,7 +3118,7 @@
3119
3118
  Execution Slots: SLOT0123
3120
3119
  ========================================================================== */
3121
3120
 
3122
- #define Q6_Ww_vsub_WwWw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw_dv)
3121
+ #define Q6_Ww_vsub_WwWw(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw_dv)(Vuu,Vvv)
3123
3122
  #endif /* __HEXAGON_ARCH___ >= 60 */
3124
3123
 
3125
3124
  #if __HVX_ARCH__ >= 60
@@ -3130,7 +3129,7 @@
3130
3129
  Execution Slots: SLOT0123
3131
3130
  ========================================================================== */
3132
3131
 
3133
- #define Q6_Vw_condnac_QnVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwnq)
3132
+ #define Q6_Vw_condnac_QnVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
3134
3133
  #endif /* __HEXAGON_ARCH___ >= 60 */
3135
3134
 
3136
3135
  #if __HVX_ARCH__ >= 60
@@ -3141,7 +3140,7 @@
3141
3140
  Execution Slots: SLOT0123
3142
3141
  ========================================================================== */
3143
3142
 
3144
- #define Q6_Vw_condnac_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwq)
3143
+ #define Q6_Vw_condnac_QVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
3145
3144
  #endif /* __HEXAGON_ARCH___ >= 60 */
3146
3145
 
3147
3146
  #if __HVX_ARCH__ >= 60
@@ -3152,7 +3151,7 @@
3152
3151
  Execution Slots: SLOT0123
3153
3152
  ========================================================================== */
3154
3153
 
3155
- #define Q6_Vw_vsub_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat)
3154
+ #define Q6_Vw_vsub_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat)(Vu,Vv)
3156
3155
  #endif /* __HEXAGON_ARCH___ >= 60 */
3157
3156
 
3158
3157
  #if __HVX_ARCH__ >= 60
@@ -3163,7 +3162,7 @@
3163
3162
  Execution Slots: SLOT0123
3164
3163
  ========================================================================== */
3165
3164
 
3166
- #define Q6_Ww_vsub_WwWw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat_dv)
3165
+ #define Q6_Ww_vsub_WwWw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat_dv)(Vuu,Vvv)
3167
3166
  #endif /* __HEXAGON_ARCH___ >= 60 */
3168
3167
 
3169
3168
  #if __HVX_ARCH__ >= 60
@@ -3174,7 +3173,7 @@
3174
3173
  Execution Slots: SLOT0123
3175
3174
  ========================================================================== */
3176
3175
 
3177
- #define Q6_W_vswap_QVV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vswap)
3176
+ #define Q6_W_vswap_QVV(Qt,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vswap)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1),Vu,Vv)
3178
3177
  #endif /* __HEXAGON_ARCH___ >= 60 */
3179
3178
 
3180
3179
  #if __HVX_ARCH__ >= 60
@@ -3185,7 +3184,7 @@
3185
3184
  Execution Slots: SLOT23
3186
3185
  ========================================================================== */
3187
3186
 
3188
- #define Q6_Wh_vtmpy_WbRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb)
3187
+ #define Q6_Wh_vtmpy_WbRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb)(Vuu,Rt)
3189
3188
  #endif /* __HEXAGON_ARCH___ >= 60 */
3190
3189
 
3191
3190
  #if __HVX_ARCH__ >= 60
@@ -3196,7 +3195,7 @@
3196
3195
  Execution Slots: SLOT23
3197
3196
  ========================================================================== */
3198
3197
 
3199
- #define Q6_Wh_vtmpyacc_WhWbRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb_acc)
3198
+ #define Q6_Wh_vtmpyacc_WhWbRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb_acc)(Vxx,Vuu,Rt)
3200
3199
  #endif /* __HEXAGON_ARCH___ >= 60 */
3201
3200
 
3202
3201
  #if __HVX_ARCH__ >= 60
@@ -3207,7 +3206,7 @@
3207
3206
  Execution Slots: SLOT23
3208
3207
  ========================================================================== */
3209
3208
 
3210
- #define Q6_Wh_vtmpy_WubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus)
3209
+ #define Q6_Wh_vtmpy_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus)(Vuu,Rt)
3211
3210
  #endif /* __HEXAGON_ARCH___ >= 60 */
3212
3211
 
3213
3212
  #if __HVX_ARCH__ >= 60
@@ -3218,7 +3217,7 @@
3218
3217
  Execution Slots: SLOT23
3219
3218
  ========================================================================== */
3220
3219
 
3221
- #define Q6_Wh_vtmpyacc_WhWubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus_acc)
3220
+ #define Q6_Wh_vtmpyacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus_acc)(Vxx,Vuu,Rt)
3222
3221
  #endif /* __HEXAGON_ARCH___ >= 60 */
3223
3222
 
3224
3223
  #if __HVX_ARCH__ >= 60
@@ -3229,7 +3228,7 @@
3229
3228
  Execution Slots: SLOT23
3230
3229
  ========================================================================== */
3231
3230
 
3232
- #define Q6_Ww_vtmpy_WhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb)
3231
+ #define Q6_Ww_vtmpy_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb)(Vuu,Rt)
3233
3232
  #endif /* __HEXAGON_ARCH___ >= 60 */
3234
3233
 
3235
3234
  #if __HVX_ARCH__ >= 60
@@ -3240,7 +3239,7 @@
3240
3239
  Execution Slots: SLOT23
3241
3240
  ========================================================================== */
3242
3241
 
3243
- #define Q6_Ww_vtmpyacc_WwWhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb_acc)
3242
+ #define Q6_Ww_vtmpyacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb_acc)(Vxx,Vuu,Rt)
3244
3243
  #endif /* __HEXAGON_ARCH___ >= 60 */
3245
3244
 
3246
3245
  #if __HVX_ARCH__ >= 60
@@ -3251,7 +3250,7 @@
3251
3250
  Execution Slots: SLOT0123
3252
3251
  ========================================================================== */
3253
3252
 
3254
- #define Q6_Wh_vunpack_Vb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackb)
3253
+ #define Q6_Wh_vunpack_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackb)(Vu)
3255
3254
  #endif /* __HEXAGON_ARCH___ >= 60 */
3256
3255
 
3257
3256
  #if __HVX_ARCH__ >= 60
@@ -3262,7 +3261,7 @@
3262
3261
  Execution Slots: SLOT0123
3263
3262
  ========================================================================== */
3264
3263
 
3265
- #define Q6_Ww_vunpack_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackh)
3264
+ #define Q6_Ww_vunpack_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackh)(Vu)
3266
3265
  #endif /* __HEXAGON_ARCH___ >= 60 */
3267
3266
 
3268
3267
  #if __HVX_ARCH__ >= 60
@@ -3273,7 +3272,7 @@
3273
3272
  Execution Slots: SLOT0123
3274
3273
  ========================================================================== */
3275
3274
 
3276
- #define Q6_Wh_vunpackoor_WhVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackob)
3275
+ #define Q6_Wh_vunpackoor_WhVb(Vxx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackob)(Vxx,Vu)
3277
3276
  #endif /* __HEXAGON_ARCH___ >= 60 */
3278
3277
 
3279
3278
  #if __HVX_ARCH__ >= 60
@@ -3284,7 +3283,7 @@
3284
3283
  Execution Slots: SLOT0123
3285
3284
  ========================================================================== */
3286
3285
 
3287
- #define Q6_Ww_vunpackoor_WwVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackoh)
3286
+ #define Q6_Ww_vunpackoor_WwVh(Vxx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackoh)(Vxx,Vu)
3288
3287
  #endif /* __HEXAGON_ARCH___ >= 60 */
3289
3288
 
3290
3289
  #if __HVX_ARCH__ >= 60
@@ -3295,7 +3294,7 @@
3295
3294
  Execution Slots: SLOT0123
3296
3295
  ========================================================================== */
3297
3296
 
3298
- #define Q6_Wuh_vunpack_Vub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackub)
3297
+ #define Q6_Wuh_vunpack_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackub)(Vu)
3299
3298
  #endif /* __HEXAGON_ARCH___ >= 60 */
3300
3299
 
3301
3300
  #if __HVX_ARCH__ >= 60
@@ -3306,7 +3305,7 @@
3306
3305
  Execution Slots: SLOT0123
3307
3306
  ========================================================================== */
3308
3307
 
3309
- #define Q6_Wuw_vunpack_Vuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackuh)
3308
+ #define Q6_Wuw_vunpack_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackuh)(Vu)
3310
3309
  #endif /* __HEXAGON_ARCH___ >= 60 */
3311
3310
 
3312
3311
  #if __HVX_ARCH__ >= 60
@@ -3317,7 +3316,7 @@
3317
3316
  Execution Slots: SLOT0123
3318
3317
  ========================================================================== */
3319
3318
 
3320
- #define Q6_V_vxor_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vxor)
3319
+ #define Q6_V_vxor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vxor)(Vu,Vv)
3321
3320
  #endif /* __HEXAGON_ARCH___ >= 60 */
3322
3321
 
3323
3322
  #if __HVX_ARCH__ >= 60
@@ -3328,7 +3327,7 @@
3328
3327
  Execution Slots: SLOT0123
3329
3328
  ========================================================================== */
3330
3329
 
3331
- #define Q6_Wuh_vzxt_Vub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzb)
3330
+ #define Q6_Wuh_vzxt_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzb)(Vu)
3332
3331
  #endif /* __HEXAGON_ARCH___ >= 60 */
3333
3332
 
3334
3333
  #if __HVX_ARCH__ >= 60
@@ -3339,7 +3338,7 @@
3339
3338
  Execution Slots: SLOT0123
3340
3339
  ========================================================================== */
3341
3340
 
3342
- #define Q6_Wuw_vzxt_Vuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzh)
3341
+ #define Q6_Wuw_vzxt_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzh)(Vu)
3343
3342
  #endif /* __HEXAGON_ARCH___ >= 60 */
3344
3343
 
3345
3344
  #if __HVX_ARCH__ >= 62
@@ -3350,7 +3349,7 @@
3350
3349
  Execution Slots: SLOT23
3351
3350
  ========================================================================== */
3352
3351
 
3353
- #define Q6_Vb_vsplat_R __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatb)
3352
+ #define Q6_Vb_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatb)(Rt)
3354
3353
  #endif /* __HEXAGON_ARCH___ >= 62 */
3355
3354
 
3356
3355
  #if __HVX_ARCH__ >= 62
@@ -3361,7 +3360,7 @@
3361
3360
  Execution Slots: SLOT23
3362
3361
  ========================================================================== */
3363
3362
 
3364
- #define Q6_Vh_vsplat_R __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplath)
3363
+ #define Q6_Vh_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplath)(Rt)
3365
3364
  #endif /* __HEXAGON_ARCH___ >= 62 */
3366
3365
 
3367
3366
  #if __HVX_ARCH__ >= 62
@@ -3372,7 +3371,7 @@
3372
3371
  Execution Slots: SLOT0123
3373
3372
  ========================================================================== */
3374
3373
 
3375
- #define Q6_Q_vsetq2_R __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2v2)
3374
+ #define Q6_Q_vsetq2_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2v2)(Rt)),-1)
3376
3375
  #endif /* __HEXAGON_ARCH___ >= 62 */
3377
3376
 
3378
3377
  #if __HVX_ARCH__ >= 62
@@ -3383,7 +3382,7 @@
3383
3382
  Execution Slots: SLOT0123
3384
3383
  ========================================================================== */
3385
3384
 
3386
- #define Q6_Qb_vshuffe_QhQh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqh)
3385
+ #define Q6_Qb_vshuffe_QhQh(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqh)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
3387
3386
  #endif /* __HEXAGON_ARCH___ >= 62 */
3388
3387
 
3389
3388
  #if __HVX_ARCH__ >= 62
@@ -3394,7 +3393,7 @@
3394
3393
  Execution Slots: SLOT0123
3395
3394
  ========================================================================== */
3396
3395
 
3397
- #define Q6_Qh_vshuffe_QwQw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqw)
3396
+ #define Q6_Qh_vshuffe_QwQw(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqw)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
3398
3397
  #endif /* __HEXAGON_ARCH___ >= 62 */
3399
3398
 
3400
3399
  #if __HVX_ARCH__ >= 62
@@ -3405,7 +3404,7 @@
3405
3404
  Execution Slots: SLOT0123
3406
3405
  ========================================================================== */
3407
3406
 
3408
- #define Q6_Vb_vadd_VbVb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat)
3407
+ #define Q6_Vb_vadd_VbVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat)(Vu,Vv)
3409
3408
  #endif /* __HEXAGON_ARCH___ >= 62 */
3410
3409
 
3411
3410
  #if __HVX_ARCH__ >= 62
@@ -3416,7 +3415,7 @@
3416
3415
  Execution Slots: SLOT0123
3417
3416
  ========================================================================== */
3418
3417
 
3419
- #define Q6_Wb_vadd_WbWb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat_dv)
3418
+ #define Q6_Wb_vadd_WbWb_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat_dv)(Vuu,Vvv)
3420
3419
  #endif /* __HEXAGON_ARCH___ >= 62 */
3421
3420
 
3422
3421
  #if __HVX_ARCH__ >= 62
@@ -3427,7 +3426,7 @@
3427
3426
  Execution Slots: SLOT0123
3428
3427
  ========================================================================== */
3429
3428
 
3430
- #define Q6_Vw_vadd_VwVwQ_carry __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarry)
3429
+ #define Q6_Vw_vadd_VwVwQ_carry(Vu,Vv,Qx) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarry)(Vu,Vv,Qx)
3431
3430
  #endif /* __HEXAGON_ARCH___ >= 62 */
3432
3431
 
3433
3432
  #if __HVX_ARCH__ >= 62
@@ -3438,7 +3437,7 @@
3438
3437
  Execution Slots: SLOT0123
3439
3438
  ========================================================================== */
3440
3439
 
3441
- #define Q6_Vh_vadd_vclb_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbh)
3440
+ #define Q6_Vh_vadd_vclb_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbh)(Vu,Vv)
3442
3441
  #endif /* __HEXAGON_ARCH___ >= 62 */
3443
3442
 
3444
3443
  #if __HVX_ARCH__ >= 62
@@ -3449,7 +3448,7 @@
3449
3448
  Execution Slots: SLOT0123
3450
3449
  ========================================================================== */
3451
3450
 
3452
- #define Q6_Vw_vadd_vclb_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbw)
3451
+ #define Q6_Vw_vadd_vclb_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbw)(Vu,Vv)
3453
3452
  #endif /* __HEXAGON_ARCH___ >= 62 */
3454
3453
 
3455
3454
  #if __HVX_ARCH__ >= 62
@@ -3460,7 +3459,7 @@
3460
3459
  Execution Slots: SLOT23
3461
3460
  ========================================================================== */
3462
3461
 
3463
- #define Q6_Ww_vaddacc_WwVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw_acc)
3462
+ #define Q6_Ww_vaddacc_WwVhVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw_acc)(Vxx,Vu,Vv)
3464
3463
  #endif /* __HEXAGON_ARCH___ >= 62 */
3465
3464
 
3466
3465
  #if __HVX_ARCH__ >= 62
@@ -3471,7 +3470,7 @@
3471
3470
  Execution Slots: SLOT23
3472
3471
  ========================================================================== */
3473
3472
 
3474
- #define Q6_Wh_vaddacc_WhVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh_acc)
3473
+ #define Q6_Wh_vaddacc_WhVubVub(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh_acc)(Vxx,Vu,Vv)
3475
3474
  #endif /* __HEXAGON_ARCH___ >= 62 */
3476
3475
 
3477
3476
  #if __HVX_ARCH__ >= 62
@@ -3482,7 +3481,7 @@
3482
3481
  Execution Slots: SLOT0123
3483
3482
  ========================================================================== */
3484
3483
 
3485
- #define Q6_Vub_vadd_VubVb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddububb_sat)
3484
+ #define Q6_Vub_vadd_VubVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddububb_sat)(Vu,Vv)
3486
3485
  #endif /* __HEXAGON_ARCH___ >= 62 */
3487
3486
 
3488
3487
  #if __HVX_ARCH__ >= 62
@@ -3493,7 +3492,7 @@
3493
3492
  Execution Slots: SLOT23
3494
3493
  ========================================================================== */
3495
3494
 
3496
- #define Q6_Ww_vaddacc_WwVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw_acc)
3495
+ #define Q6_Ww_vaddacc_WwVuhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw_acc)(Vxx,Vu,Vv)
3497
3496
  #endif /* __HEXAGON_ARCH___ >= 62 */
3498
3497
 
3499
3498
  #if __HVX_ARCH__ >= 62
@@ -3504,7 +3503,7 @@
3504
3503
  Execution Slots: SLOT0123
3505
3504
  ========================================================================== */
3506
3505
 
3507
- #define Q6_Vuw_vadd_VuwVuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat)
3506
+ #define Q6_Vuw_vadd_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat)(Vu,Vv)
3508
3507
  #endif /* __HEXAGON_ARCH___ >= 62 */
3509
3508
 
3510
3509
  #if __HVX_ARCH__ >= 62
@@ -3515,7 +3514,7 @@
3515
3514
  Execution Slots: SLOT0123
3516
3515
  ========================================================================== */
3517
3516
 
3518
- #define Q6_Wuw_vadd_WuwWuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat_dv)
3517
+ #define Q6_Wuw_vadd_WuwWuw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat_dv)(Vuu,Vvv)
3519
3518
  #endif /* __HEXAGON_ARCH___ >= 62 */
3520
3519
 
3521
3520
  #if __HVX_ARCH__ >= 62
@@ -3526,7 +3525,7 @@
3526
3525
  Execution Slots: SLOT23
3527
3526
  ========================================================================== */
3528
3527
 
3529
- #define Q6_V_vand_QnR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt)
3528
+ #define Q6_V_vand_QnR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt)
3530
3529
  #endif /* __HEXAGON_ARCH___ >= 62 */
3531
3530
 
3532
3531
  #if __HVX_ARCH__ >= 62
@@ -3537,7 +3536,7 @@
3537
3536
  Execution Slots: SLOT23
3538
3537
  ========================================================================== */
3539
3538
 
3540
- #define Q6_V_vandor_VQnR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt_acc)
3539
+ #define Q6_V_vandor_VQnR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt)
3541
3540
  #endif /* __HEXAGON_ARCH___ >= 62 */
3542
3541
 
3543
3542
  #if __HVX_ARCH__ >= 62
@@ -3548,7 +3547,7 @@
3548
3547
  Execution Slots: SLOT0123
3549
3548
  ========================================================================== */
3550
3549
 
3551
- #define Q6_V_vand_QnV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvnqv)
3550
+ #define Q6_V_vand_QnV(Qv,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvnqv)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vu)
3552
3551
  #endif /* __HEXAGON_ARCH___ >= 62 */
3553
3552
 
3554
3553
  #if __HVX_ARCH__ >= 62
@@ -3559,7 +3558,7 @@
3559
3558
  Execution Slots: SLOT0123
3560
3559
  ========================================================================== */
3561
3560
 
3562
- #define Q6_V_vand_QV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvqv)
3561
+ #define Q6_V_vand_QV(Qv,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvqv)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vu)
3563
3562
  #endif /* __HEXAGON_ARCH___ >= 62 */
3564
3563
 
3565
3564
  #if __HVX_ARCH__ >= 62
@@ -3570,7 +3569,7 @@
3570
3569
  Execution Slots: SLOT0123
3571
3570
  ========================================================================== */
3572
3571
 
3573
- #define Q6_Vb_vasr_VhVhR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbsat)
3572
+ #define Q6_Vb_vasr_VhVhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbsat)(Vu,Vv,Rt)
3574
3573
  #endif /* __HEXAGON_ARCH___ >= 62 */
3575
3574
 
3576
3575
  #if __HVX_ARCH__ >= 62
@@ -3581,7 +3580,7 @@
3581
3580
  Execution Slots: SLOT0123
3582
3581
  ========================================================================== */
3583
3582
 
3584
- #define Q6_Vuh_vasr_VuwVuwR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhrndsat)
3583
+ #define Q6_Vuh_vasr_VuwVuwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhrndsat)(Vu,Vv,Rt)
3585
3584
  #endif /* __HEXAGON_ARCH___ >= 62 */
3586
3585
 
3587
3586
  #if __HVX_ARCH__ >= 62
@@ -3592,7 +3591,7 @@
3592
3591
  Execution Slots: SLOT0123
3593
3592
  ========================================================================== */
3594
3593
 
3595
- #define Q6_Vuh_vasr_VwVwR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhrndsat)
3594
+ #define Q6_Vuh_vasr_VwVwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhrndsat)(Vu,Vv,Rt)
3596
3595
  #endif /* __HEXAGON_ARCH___ >= 62 */
3597
3596
 
3598
3597
  #if __HVX_ARCH__ >= 62
@@ -3603,7 +3602,7 @@
3603
3602
  Execution Slots: SLOT0123
3604
3603
  ========================================================================== */
3605
3604
 
3606
- #define Q6_Vub_vlsr_VubR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrb)
3605
+ #define Q6_Vub_vlsr_VubR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrb)(Vu,Rt)
3607
3606
  #endif /* __HEXAGON_ARCH___ >= 62 */
3608
3607
 
3609
3608
  #if __HVX_ARCH__ >= 62
@@ -3614,7 +3613,7 @@
3614
3613
  Execution Slots: SLOT0123
3615
3614
  ========================================================================== */
3616
3615
 
3617
- #define Q6_Vb_vlut32_VbVbR_nomatch __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_nm)
3616
+ #define Q6_Vb_vlut32_VbVbR_nomatch(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_nm)(Vu,Vv,Rt)
3618
3617
  #endif /* __HEXAGON_ARCH___ >= 62 */
3619
3618
 
3620
3619
  #if __HVX_ARCH__ >= 62
@@ -3625,7 +3624,7 @@
3625
3624
  Execution Slots: SLOT0123
3626
3625
  ========================================================================== */
3627
3626
 
3628
- #define Q6_Vb_vlut32or_VbVbVbI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracci)
3627
+ #define Q6_Vb_vlut32or_VbVbVbI(Vx,Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracci)(Vx,Vu,Vv,Iu3)
3629
3628
  #endif /* __HEXAGON_ARCH___ >= 62 */
3630
3629
 
3631
3630
  #if __HVX_ARCH__ >= 62
@@ -3636,7 +3635,7 @@
3636
3635
  Execution Slots: SLOT0123
3637
3636
  ========================================================================== */
3638
3637
 
3639
- #define Q6_Vb_vlut32_VbVbI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvbi)
3638
+ #define Q6_Vb_vlut32_VbVbI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvbi)(Vu,Vv,Iu3)
3640
3639
  #endif /* __HEXAGON_ARCH___ >= 62 */
3641
3640
 
3642
3641
  #if __HVX_ARCH__ >= 62
@@ -3647,7 +3646,7 @@
3647
3646
  Execution Slots: SLOT0123
3648
3647
  ========================================================================== */
3649
3648
 
3650
- #define Q6_Wh_vlut16_VbVhR_nomatch __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_nm)
3649
+ #define Q6_Wh_vlut16_VbVhR_nomatch(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_nm)(Vu,Vv,Rt)
3651
3650
  #endif /* __HEXAGON_ARCH___ >= 62 */
3652
3651
 
3653
3652
  #if __HVX_ARCH__ >= 62
@@ -3658,7 +3657,7 @@
3658
3657
  Execution Slots: SLOT0123
3659
3658
  ========================================================================== */
3660
3659
 
3661
- #define Q6_Wh_vlut16or_WhVbVhI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracci)
3660
+ #define Q6_Wh_vlut16or_WhVbVhI(Vxx,Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracci)(Vxx,Vu,Vv,Iu3)
3662
3661
  #endif /* __HEXAGON_ARCH___ >= 62 */
3663
3662
 
3664
3663
  #if __HVX_ARCH__ >= 62
@@ -3669,7 +3668,7 @@
3669
3668
  Execution Slots: SLOT0123
3670
3669
  ========================================================================== */
3671
3670
 
3672
- #define Q6_Wh_vlut16_VbVhI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwhi)
3671
+ #define Q6_Wh_vlut16_VbVhI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwhi)(Vu,Vv,Iu3)
3673
3672
  #endif /* __HEXAGON_ARCH___ >= 62 */
3674
3673
 
3675
3674
  #if __HVX_ARCH__ >= 62
@@ -3680,7 +3679,7 @@
3680
3679
  Execution Slots: SLOT0123
3681
3680
  ========================================================================== */
3682
3681
 
3683
- #define Q6_Vb_vmax_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxb)
3682
+ #define Q6_Vb_vmax_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxb)(Vu,Vv)
3684
3683
  #endif /* __HEXAGON_ARCH___ >= 62 */
3685
3684
 
3686
3685
  #if __HVX_ARCH__ >= 62
@@ -3691,7 +3690,7 @@
3691
3690
  Execution Slots: SLOT0123
3692
3691
  ========================================================================== */
3693
3692
 
3694
- #define Q6_Vb_vmin_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminb)
3693
+ #define Q6_Vb_vmin_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminb)(Vu,Vv)
3695
3694
  #endif /* __HEXAGON_ARCH___ >= 62 */
3696
3695
 
3697
3696
  #if __HVX_ARCH__ >= 62
@@ -3702,7 +3701,7 @@
3702
3701
  Execution Slots: SLOT23
3703
3702
  ========================================================================== */
3704
3703
 
3705
- #define Q6_Ww_vmpa_WuhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb)
3704
+ #define Q6_Ww_vmpa_WuhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb)(Vuu,Rt)
3706
3705
  #endif /* __HEXAGON_ARCH___ >= 62 */
3707
3706
 
3708
3707
  #if __HVX_ARCH__ >= 62
@@ -3713,7 +3712,7 @@
3713
3712
  Execution Slots: SLOT23
3714
3713
  ========================================================================== */
3715
3714
 
3716
- #define Q6_Ww_vmpaacc_WwWuhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb_acc)
3715
+ #define Q6_Ww_vmpaacc_WwWuhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb_acc)(Vxx,Vuu,Rt)
3717
3716
  #endif /* __HEXAGON_ARCH___ >= 62 */
3718
3717
 
3719
3718
  #if __HVX_ARCH__ >= 62
@@ -3724,7 +3723,7 @@
3724
3723
  Execution Slots: SLOT23
3725
3724
  ========================================================================== */
3726
3725
 
3727
- #define Q6_W_vmpye_VwVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh_64)
3726
+ #define Q6_W_vmpye_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh_64)(Vu,Vv)
3728
3727
  #endif /* __HEXAGON_ARCH___ >= 62 */
3729
3728
 
3730
3729
  #if __HVX_ARCH__ >= 62
@@ -3735,7 +3734,7 @@
3735
3734
  Execution Slots: SLOT23
3736
3735
  ========================================================================== */
3737
3736
 
3738
- #define Q6_Vw_vmpyi_VwRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub)
3737
+ #define Q6_Vw_vmpyi_VwRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub)(Vu,Rt)
3739
3738
  #endif /* __HEXAGON_ARCH___ >= 62 */
3740
3739
 
3741
3740
  #if __HVX_ARCH__ >= 62
@@ -3746,7 +3745,7 @@
3746
3745
  Execution Slots: SLOT23
3747
3746
  ========================================================================== */
3748
3747
 
3749
- #define Q6_Vw_vmpyiacc_VwVwRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub_acc)
3748
+ #define Q6_Vw_vmpyiacc_VwVwRub(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub_acc)(Vx,Vu,Rt)
3750
3749
  #endif /* __HEXAGON_ARCH___ >= 62 */
3751
3750
 
3752
3751
  #if __HVX_ARCH__ >= 62
@@ -3757,7 +3756,7 @@
3757
3756
  Execution Slots: SLOT23
3758
3757
  ========================================================================== */
3759
3758
 
3760
- #define Q6_W_vmpyoacc_WVwVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_64_acc)
3759
+ #define Q6_W_vmpyoacc_WVwVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_64_acc)(Vxx,Vu,Vv)
3761
3760
  #endif /* __HEXAGON_ARCH___ >= 62 */
3762
3761
 
3763
3762
  #if __HVX_ARCH__ >= 62
@@ -3768,7 +3767,7 @@
3768
3767
  Execution Slots: SLOT0123
3769
3768
  ========================================================================== */
3770
3769
 
3771
- #define Q6_Vub_vround_VuhVuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduhub)
3770
+ #define Q6_Vub_vround_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduhub)(Vu,Vv)
3772
3771
  #endif /* __HEXAGON_ARCH___ >= 62 */
3773
3772
 
3774
3773
  #if __HVX_ARCH__ >= 62
@@ -3779,7 +3778,7 @@
3779
3778
  Execution Slots: SLOT0123
3780
3779
  ========================================================================== */
3781
3780
 
3782
- #define Q6_Vuh_vround_VuwVuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduwuh)
3781
+ #define Q6_Vuh_vround_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduwuh)(Vu,Vv)
3783
3782
  #endif /* __HEXAGON_ARCH___ >= 62 */
3784
3783
 
3785
3784
  #if __HVX_ARCH__ >= 62
@@ -3790,7 +3789,7 @@
3790
3789
  Execution Slots: SLOT0123
3791
3790
  ========================================================================== */
3792
3791
 
3793
- #define Q6_Vuh_vsat_VuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatuwuh)
3792
+ #define Q6_Vuh_vsat_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatuwuh)(Vu,Vv)
3794
3793
  #endif /* __HEXAGON_ARCH___ >= 62 */
3795
3794
 
3796
3795
  #if __HVX_ARCH__ >= 62
@@ -3801,7 +3800,7 @@
3801
3800
  Execution Slots: SLOT0123
3802
3801
  ========================================================================== */
3803
3802
 
3804
- #define Q6_Vb_vsub_VbVb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat)
3803
+ #define Q6_Vb_vsub_VbVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat)(Vu,Vv)
3805
3804
  #endif /* __HEXAGON_ARCH___ >= 62 */
3806
3805
 
3807
3806
  #if __HVX_ARCH__ >= 62
@@ -3812,7 +3811,7 @@
3812
3811
  Execution Slots: SLOT0123
3813
3812
  ========================================================================== */
3814
3813
 
3815
- #define Q6_Wb_vsub_WbWb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat_dv)
3814
+ #define Q6_Wb_vsub_WbWb_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat_dv)(Vuu,Vvv)
3816
3815
  #endif /* __HEXAGON_ARCH___ >= 62 */
3817
3816
 
3818
3817
  #if __HVX_ARCH__ >= 62
@@ -3823,7 +3822,7 @@
3823
3822
  Execution Slots: SLOT0123
3824
3823
  ========================================================================== */
3825
3824
 
3826
- #define Q6_Vw_vsub_VwVwQ_carry __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubcarry)
3825
+ #define Q6_Vw_vsub_VwVwQ_carry(Vu,Vv,Qx) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubcarry)(Vu,Vv,Qx)
3827
3826
  #endif /* __HEXAGON_ARCH___ >= 62 */
3828
3827
 
3829
3828
  #if __HVX_ARCH__ >= 62
@@ -3834,7 +3833,7 @@
3834
3833
  Execution Slots: SLOT0123
3835
3834
  ========================================================================== */
3836
3835
 
3837
- #define Q6_Vub_vsub_VubVb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubububb_sat)
3836
+ #define Q6_Vub_vsub_VubVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubububb_sat)(Vu,Vv)
3838
3837
  #endif /* __HEXAGON_ARCH___ >= 62 */
3839
3838
 
3840
3839
  #if __HVX_ARCH__ >= 62
@@ -3845,7 +3844,7 @@
3845
3844
  Execution Slots: SLOT0123
3846
3845
  ========================================================================== */
3847
3846
 
3848
- #define Q6_Vuw_vsub_VuwVuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat)
3847
+ #define Q6_Vuw_vsub_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat)(Vu,Vv)
3849
3848
  #endif /* __HEXAGON_ARCH___ >= 62 */
3850
3849
 
3851
3850
  #if __HVX_ARCH__ >= 62
@@ -3856,7 +3855,7 @@
3856
3855
  Execution Slots: SLOT0123
3857
3856
  ========================================================================== */
3858
3857
 
3859
- #define Q6_Wuw_vsub_WuwWuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat_dv)
3858
+ #define Q6_Wuw_vsub_WuwWuw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat_dv)(Vuu,Vvv)
3860
3859
  #endif /* __HEXAGON_ARCH___ >= 62 */
3861
3860
 
3862
3861
  #if __HVX_ARCH__ >= 65
@@ -3867,7 +3866,7 @@
3867
3866
  Execution Slots: SLOT0123
3868
3867
  ========================================================================== */
3869
3868
 
3870
- #define Q6_Vb_vabs_Vb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb)
3869
+ #define Q6_Vb_vabs_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb)(Vu)
3871
3870
  #endif /* __HEXAGON_ARCH___ >= 65 */
3872
3871
 
3873
3872
  #if __HVX_ARCH__ >= 65
@@ -3878,7 +3877,7 @@
3878
3877
  Execution Slots: SLOT0123
3879
3878
  ========================================================================== */
3880
3879
 
3881
- #define Q6_Vb_vabs_Vb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb_sat)
3880
+ #define Q6_Vb_vabs_Vb_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb_sat)(Vu)
3882
3881
  #endif /* __HEXAGON_ARCH___ >= 65 */
3883
3882
 
3884
3883
  #if __HVX_ARCH__ >= 65
@@ -3889,7 +3888,7 @@
3889
3888
  Execution Slots: SLOT0123
3890
3889
  ========================================================================== */
3891
3890
 
3892
- #define Q6_Vh_vaslacc_VhVhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh_acc)
3891
+ #define Q6_Vh_vaslacc_VhVhR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh_acc)(Vx,Vu,Rt)
3893
3892
  #endif /* __HEXAGON_ARCH___ >= 65 */
3894
3893
 
3895
3894
  #if __HVX_ARCH__ >= 65
@@ -3900,7 +3899,7 @@
3900
3899
  Execution Slots: SLOT0123
3901
3900
  ========================================================================== */
3902
3901
 
3903
- #define Q6_Vh_vasracc_VhVhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh_acc)
3902
+ #define Q6_Vh_vasracc_VhVhR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh_acc)(Vx,Vu,Rt)
3904
3903
  #endif /* __HEXAGON_ARCH___ >= 65 */
3905
3904
 
3906
3905
  #if __HVX_ARCH__ >= 65
@@ -3911,7 +3910,7 @@
3911
3910
  Execution Slots: SLOT0123
3912
3911
  ========================================================================== */
3913
3912
 
3914
- #define Q6_Vub_vasr_VuhVuhR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubrndsat)
3913
+ #define Q6_Vub_vasr_VuhVuhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubrndsat)(Vu,Vv,Rt)
3915
3914
  #endif /* __HEXAGON_ARCH___ >= 65 */
3916
3915
 
3917
3916
  #if __HVX_ARCH__ >= 65
@@ -3922,7 +3921,7 @@
3922
3921
  Execution Slots: SLOT0123
3923
3922
  ========================================================================== */
3924
3923
 
3925
- #define Q6_Vub_vasr_VuhVuhR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubsat)
3924
+ #define Q6_Vub_vasr_VuhVuhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubsat)(Vu,Vv,Rt)
3926
3925
  #endif /* __HEXAGON_ARCH___ >= 65 */
3927
3926
 
3928
3927
  #if __HVX_ARCH__ >= 65
@@ -3933,7 +3932,7 @@
3933
3932
  Execution Slots: SLOT0123
3934
3933
  ========================================================================== */
3935
3934
 
3936
- #define Q6_Vuh_vasr_VuwVuwR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhsat)
3935
+ #define Q6_Vuh_vasr_VuwVuwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhsat)(Vu,Vv,Rt)
3937
3936
  #endif /* __HEXAGON_ARCH___ >= 65 */
3938
3937
 
3939
3938
  #if __HVX_ARCH__ >= 65
@@ -3944,7 +3943,7 @@
3944
3943
  Execution Slots: SLOT0123
3945
3944
  ========================================================================== */
3946
3945
 
3947
- #define Q6_Vb_vavg_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgb)
3946
+ #define Q6_Vb_vavg_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgb)(Vu,Vv)
3948
3947
  #endif /* __HEXAGON_ARCH___ >= 65 */
3949
3948
 
3950
3949
  #if __HVX_ARCH__ >= 65
@@ -3955,7 +3954,7 @@
3955
3954
  Execution Slots: SLOT0123
3956
3955
  ========================================================================== */
3957
3956
 
3958
- #define Q6_Vb_vavg_VbVb_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgbrnd)
3957
+ #define Q6_Vb_vavg_VbVb_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgbrnd)(Vu,Vv)
3959
3958
  #endif /* __HEXAGON_ARCH___ >= 65 */
3960
3959
 
3961
3960
  #if __HVX_ARCH__ >= 65
@@ -3966,7 +3965,7 @@
3966
3965
  Execution Slots: SLOT0123
3967
3966
  ========================================================================== */
3968
3967
 
3969
- #define Q6_Vuw_vavg_VuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguw)
3968
+ #define Q6_Vuw_vavg_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguw)(Vu,Vv)
3970
3969
  #endif /* __HEXAGON_ARCH___ >= 65 */
3971
3970
 
3972
3971
  #if __HVX_ARCH__ >= 65
@@ -3977,7 +3976,7 @@
3977
3976
  Execution Slots: SLOT0123
3978
3977
  ========================================================================== */
3979
3978
 
3980
- #define Q6_Vuw_vavg_VuwVuw_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguwrnd)
3979
+ #define Q6_Vuw_vavg_VuwVuw_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguwrnd)(Vu,Vv)
3981
3980
  #endif /* __HEXAGON_ARCH___ >= 65 */
3982
3981
 
3983
3982
  #if __HVX_ARCH__ >= 65
@@ -3988,7 +3987,7 @@
3988
3987
  Execution Slots: SLOT0123
3989
3988
  ========================================================================== */
3990
3989
 
3991
- #define Q6_W_vzero __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdd0)
3990
+ #define Q6_W_vzero() __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdd0)()
3992
3991
  #endif /* __HEXAGON_ARCH___ >= 65 */
3993
3992
 
3994
3993
  #if __HVX_ARCH__ >= 65
@@ -3999,7 +3998,7 @@
3999
3998
  Execution Slots: SLOT01
4000
3999
  ========================================================================== */
4001
4000
 
4002
- #define Q6_vgather_ARMVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermh)
4001
+ #define Q6_vgather_ARMVh(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermh)(Rs,Rt,Mu,Vv)
4003
4002
  #endif /* __HEXAGON_ARCH___ >= 65 */
4004
4003
 
4005
4004
  #if __HVX_ARCH__ >= 65
@@ -4010,7 +4009,7 @@
4010
4009
  Execution Slots: SLOT01
4011
4010
  ========================================================================== */
4012
4011
 
4013
- #define Q6_vgather_AQRMVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhq)
4012
+ #define Q6_vgather_AQRMVh(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv)
4014
4013
  #endif /* __HEXAGON_ARCH___ >= 65 */
4015
4014
 
4016
4015
  #if __HVX_ARCH__ >= 65
@@ -4021,7 +4020,7 @@
4021
4020
  Execution Slots: SLOT01
4022
4021
  ========================================================================== */
4023
4022
 
4024
- #define Q6_vgather_ARMWw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhw)
4023
+ #define Q6_vgather_ARMWw(Rs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhw)(Rs,Rt,Mu,Vvv)
4025
4024
  #endif /* __HEXAGON_ARCH___ >= 65 */
4026
4025
 
4027
4026
  #if __HVX_ARCH__ >= 65
@@ -4032,7 +4031,7 @@
4032
4031
  Execution Slots: SLOT01
4033
4032
  ========================================================================== */
4034
4033
 
4035
- #define Q6_vgather_AQRMWw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhwq)
4034
+ #define Q6_vgather_AQRMWw(Rs,Qs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhwq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vvv)
4036
4035
  #endif /* __HEXAGON_ARCH___ >= 65 */
4037
4036
 
4038
4037
  #if __HVX_ARCH__ >= 65
@@ -4043,7 +4042,7 @@
4043
4042
  Execution Slots: SLOT01
4044
4043
  ========================================================================== */
4045
4044
 
4046
- #define Q6_vgather_ARMVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermw)
4045
+ #define Q6_vgather_ARMVw(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermw)(Rs,Rt,Mu,Vv)
4047
4046
  #endif /* __HEXAGON_ARCH___ >= 65 */
4048
4047
 
4049
4048
  #if __HVX_ARCH__ >= 65
@@ -4054,7 +4053,7 @@
4054
4053
  Execution Slots: SLOT01
4055
4054
  ========================================================================== */
4056
4055
 
4057
- #define Q6_vgather_AQRMVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermwq)
4056
+ #define Q6_vgather_AQRMVw(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermwq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv)
4058
4057
  #endif /* __HEXAGON_ARCH___ >= 65 */
4059
4058
 
4060
4059
  #if __HVX_ARCH__ >= 65
@@ -4065,7 +4064,7 @@
4065
4064
  Execution Slots: SLOT2
4066
4065
  ========================================================================== */
4067
4066
 
4068
- #define Q6_Vh_vlut4_VuhPh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlut4)
4067
+ #define Q6_Vh_vlut4_VuhPh(Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlut4)(Vu,Rtt)
4069
4068
  #endif /* __HEXAGON_ARCH___ >= 65 */
4070
4069
 
4071
4070
  #if __HVX_ARCH__ >= 65
@@ -4076,7 +4075,7 @@
4076
4075
  Execution Slots: SLOT23
4077
4076
  ========================================================================== */
4078
4077
 
4079
- #define Q6_Wh_vmpa_WubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu)
4078
+ #define Q6_Wh_vmpa_WubRub(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu)(Vuu,Rt)
4080
4079
  #endif /* __HEXAGON_ARCH___ >= 65 */
4081
4080
 
4082
4081
  #if __HVX_ARCH__ >= 65
@@ -4087,7 +4086,7 @@
4087
4086
  Execution Slots: SLOT23
4088
4087
  ========================================================================== */
4089
4088
 
4090
- #define Q6_Wh_vmpaacc_WhWubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu_acc)
4089
+ #define Q6_Wh_vmpaacc_WhWubRub(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu_acc)(Vxx,Vuu,Rt)
4091
4090
  #endif /* __HEXAGON_ARCH___ >= 65 */
4092
4091
 
4093
4092
  #if __HVX_ARCH__ >= 65
@@ -4098,7 +4097,7 @@
4098
4097
  Execution Slots: SLOT2
4099
4098
  ========================================================================== */
4100
4099
 
4101
- #define Q6_Vh_vmpa_VhVhVhPh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahhsat)
4100
+ #define Q6_Vh_vmpa_VhVhVhPh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahhsat)(Vx,Vu,Rtt)
4102
4101
  #endif /* __HEXAGON_ARCH___ >= 65 */
4103
4102
 
4104
4103
  #if __HVX_ARCH__ >= 65
@@ -4109,7 +4108,7 @@
4109
4108
  Execution Slots: SLOT2
4110
4109
  ========================================================================== */
4111
4110
 
4112
- #define Q6_Vh_vmpa_VhVhVuhPuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhuhsat)
4111
+ #define Q6_Vh_vmpa_VhVhVuhPuh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhuhsat)(Vx,Vu,Rtt)
4113
4112
  #endif /* __HEXAGON_ARCH___ >= 65 */
4114
4113
 
4115
4114
  #if __HVX_ARCH__ >= 65
@@ -4120,7 +4119,7 @@
4120
4119
  Execution Slots: SLOT2
4121
4120
  ========================================================================== */
4122
4121
 
4123
- #define Q6_Vh_vmps_VhVhVuhPuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpsuhuhsat)
4122
+ #define Q6_Vh_vmps_VhVhVuhPuh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpsuhuhsat)(Vx,Vu,Rtt)
4124
4123
  #endif /* __HEXAGON_ARCH___ >= 65 */
4125
4124
 
4126
4125
  #if __HVX_ARCH__ >= 65
@@ -4131,7 +4130,7 @@
4131
4130
  Execution Slots: SLOT23
4132
4131
  ========================================================================== */
4133
4132
 
4134
- #define Q6_Ww_vmpyacc_WwVhRh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh_acc)
4133
+ #define Q6_Ww_vmpyacc_WwVhRh(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh_acc)(Vxx,Vu,Rt)
4135
4134
  #endif /* __HEXAGON_ARCH___ >= 65 */
4136
4135
 
4137
4136
  #if __HVX_ARCH__ >= 65
@@ -4142,7 +4141,7 @@
4142
4141
  Execution Slots: SLOT23
4143
4142
  ========================================================================== */
4144
4143
 
4145
- #define Q6_Vuw_vmpye_VuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe)
4144
+ #define Q6_Vuw_vmpye_VuhRuh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe)(Vu,Rt)
4146
4145
  #endif /* __HEXAGON_ARCH___ >= 65 */
4147
4146
 
4148
4147
  #if __HVX_ARCH__ >= 65
@@ -4153,7 +4152,7 @@
4153
4152
  Execution Slots: SLOT23
4154
4153
  ========================================================================== */
4155
4154
 
4156
- #define Q6_Vuw_vmpyeacc_VuwVuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe_acc)
4155
+ #define Q6_Vuw_vmpyeacc_VuwVuhRuh(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe_acc)(Vx,Vu,Rt)
4157
4156
  #endif /* __HEXAGON_ARCH___ >= 65 */
4158
4157
 
4159
4158
  #if __HVX_ARCH__ >= 65
@@ -4164,7 +4163,7 @@
4164
4163
  Execution Slots: SLOT0123
4165
4164
  ========================================================================== */
4166
4165
 
4167
- #define Q6_Vb_vnavg_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgb)
4166
+ #define Q6_Vb_vnavg_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgb)(Vu,Vv)
4168
4167
  #endif /* __HEXAGON_ARCH___ >= 65 */
4169
4168
 
4170
4169
  #if __HVX_ARCH__ >= 65
@@ -4175,7 +4174,7 @@
4175
4174
  Execution Slots: SLOT0123
4176
4175
  ========================================================================== */
4177
4176
 
4178
- #define Q6_Vb_prefixsum_Q __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqb)
4177
+ #define Q6_Vb_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqb)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1))
4179
4178
  #endif /* __HEXAGON_ARCH___ >= 65 */
4180
4179
 
4181
4180
  #if __HVX_ARCH__ >= 65
@@ -4186,7 +4185,7 @@
4186
4185
  Execution Slots: SLOT0123
4187
4186
  ========================================================================== */
4188
4187
 
4189
- #define Q6_Vh_prefixsum_Q __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqh)
4188
+ #define Q6_Vh_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqh)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1))
4190
4189
  #endif /* __HEXAGON_ARCH___ >= 65 */
4191
4190
 
4192
4191
  #if __HVX_ARCH__ >= 65
@@ -4197,7 +4196,7 @@
4197
4196
  Execution Slots: SLOT0123
4198
4197
  ========================================================================== */
4199
4198
 
4200
- #define Q6_Vw_prefixsum_Q __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqw)
4199
+ #define Q6_Vw_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqw)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1))
4201
4200
  #endif /* __HEXAGON_ARCH___ >= 65 */
4202
4201
 
4203
4202
  #if __HVX_ARCH__ >= 65
@@ -4208,7 +4207,7 @@
4208
4207
  Execution Slots: SLOT0
4209
4208
  ========================================================================== */
4210
4209
 
4211
- #define Q6_vscatter_RMVhV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh)
4210
+ #define Q6_vscatter_RMVhV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh)(Rt,Mu,Vv,Vw)
4212
4211
  #endif /* __HEXAGON_ARCH___ >= 65 */
4213
4212
 
4214
4213
  #if __HVX_ARCH__ >= 65
@@ -4219,7 +4218,7 @@
4219
4218
  Execution Slots: SLOT0
4220
4219
  ========================================================================== */
4221
4220
 
4222
- #define Q6_vscatteracc_RMVhV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh_add)
4221
+ #define Q6_vscatteracc_RMVhV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh_add)(Rt,Mu,Vv,Vw)
4223
4222
  #endif /* __HEXAGON_ARCH___ >= 65 */
4224
4223
 
4225
4224
  #if __HVX_ARCH__ >= 65
@@ -4230,7 +4229,7 @@
4230
4229
  Execution Slots: SLOT0
4231
4230
  ========================================================================== */
4232
4231
 
4233
- #define Q6_vscatter_QRMVhV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhq)
4232
+ #define Q6_vscatter_QRMVhV(Qs,Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv,Vw)
4234
4233
  #endif /* __HEXAGON_ARCH___ >= 65 */
4235
4234
 
4236
4235
  #if __HVX_ARCH__ >= 65
@@ -4241,7 +4240,7 @@
4241
4240
  Execution Slots: SLOT0
4242
4241
  ========================================================================== */
4243
4242
 
4244
- #define Q6_vscatter_RMWwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw)
4243
+ #define Q6_vscatter_RMWwV(Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw)(Rt,Mu,Vvv,Vw)
4245
4244
  #endif /* __HEXAGON_ARCH___ >= 65 */
4246
4245
 
4247
4246
  #if __HVX_ARCH__ >= 65
@@ -4252,7 +4251,7 @@
4252
4251
  Execution Slots: SLOT0
4253
4252
  ========================================================================== */
4254
4253
 
4255
- #define Q6_vscatteracc_RMWwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw_add)
4254
+ #define Q6_vscatteracc_RMWwV(Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw_add)(Rt,Mu,Vvv,Vw)
4256
4255
  #endif /* __HEXAGON_ARCH___ >= 65 */
4257
4256
 
4258
4257
  #if __HVX_ARCH__ >= 65
@@ -4263,7 +4262,7 @@
4263
4262
  Execution Slots: SLOT0
4264
4263
  ========================================================================== */
4265
4264
 
4266
- #define Q6_vscatter_QRMWwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhwq)
4265
+ #define Q6_vscatter_QRMWwV(Qs,Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vvv,Vw)
4267
4266
  #endif /* __HEXAGON_ARCH___ >= 65 */
4268
4267
 
4269
4268
  #if __HVX_ARCH__ >= 65
@@ -4274,7 +4273,7 @@
4274
4273
  Execution Slots: SLOT0
4275
4274
  ========================================================================== */
4276
4275
 
4277
- #define Q6_vscatter_RMVwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw)
4276
+ #define Q6_vscatter_RMVwV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw)(Rt,Mu,Vv,Vw)
4278
4277
  #endif /* __HEXAGON_ARCH___ >= 65 */
4279
4278
 
4280
4279
  #if __HVX_ARCH__ >= 65
@@ -4285,7 +4284,7 @@
4285
4284
  Execution Slots: SLOT0
4286
4285
  ========================================================================== */
4287
4286
 
4288
- #define Q6_vscatteracc_RMVwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw_add)
4287
+ #define Q6_vscatteracc_RMVwV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw_add)(Rt,Mu,Vv,Vw)
4289
4288
  #endif /* __HEXAGON_ARCH___ >= 65 */
4290
4289
 
4291
4290
  #if __HVX_ARCH__ >= 65
@@ -4296,7 +4295,7 @@
4296
4295
  Execution Slots: SLOT0
4297
4296
  ========================================================================== */
4298
4297
 
4299
- #define Q6_vscatter_QRMVwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermwq)
4298
+ #define Q6_vscatter_QRMVwV(Qs,Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv,Vw)
4300
4299
  #endif /* __HEXAGON_ARCH___ >= 65 */
4301
4300
 
4302
4301
  #if __HVX_ARCH__ >= 66
@@ -4307,7 +4306,7 @@
4307
4306
  Execution Slots: SLOT0123
4308
4307
  ========================================================================== */
4309
4308
 
4310
- #define Q6_Vw_vadd_VwVwQ_carry_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarrysat)
4309
+ #define Q6_Vw_vadd_VwVwQ_carry_sat(Vu,Vv,Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarrysat)(Vu,Vv,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1))
4311
4310
  #endif /* __HEXAGON_ARCH___ >= 66 */
4312
4311
 
4313
4312
  #if __HVX_ARCH__ >= 66
@@ -4318,7 +4317,7 @@
4318
4317
  Execution Slots: SLOT0123
4319
4318
  ========================================================================== */
4320
4319
 
4321
- #define Q6_Ww_vasrinto_WwVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasr_into)
4320
+ #define Q6_Ww_vasrinto_WwVwVw(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasr_into)(Vxx,Vu,Vv)
4322
4321
  #endif /* __HEXAGON_ARCH___ >= 66 */
4323
4322
 
4324
4323
  #if __HVX_ARCH__ >= 66
@@ -4329,7 +4328,7 @@
4329
4328
  Execution Slots: SLOT0123
4330
4329
  ========================================================================== */
4331
4330
 
4332
- #define Q6_Vuw_vrotr_VuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrotr)
4331
+ #define Q6_Vuw_vrotr_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrotr)(Vu,Vv)
4333
4332
  #endif /* __HEXAGON_ARCH___ >= 66 */
4334
4333
 
4335
4334
  #if __HVX_ARCH__ >= 66
@@ -4340,7 +4339,7 @@
4340
4339
  Execution Slots: SLOT0123
4341
4340
  ========================================================================== */
4342
4341
 
4343
- #define Q6_Vw_vsatdw_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatdw)
4342
+ #define Q6_Vw_vsatdw_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatdw)(Vu,Vv)
4344
4343
  #endif /* __HEXAGON_ARCH___ >= 66 */
4345
4344
 
4346
4345
  #if __HVX_ARCH__ >= 68
@@ -4351,7 +4350,7 @@
4351
4350
  Execution Slots: SLOT23
4352
4351
  ========================================================================== */
4353
4352
 
4354
- #define Q6_Ww_v6mpy_WubWbI_h __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10)
4353
+ #define Q6_Ww_v6mpy_WubWbI_h(Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10)(Vuu,Vvv,Iu2)
4355
4354
  #endif /* __HEXAGON_ARCH___ >= 68 */
4356
4355
 
4357
4356
  #if __HVX_ARCH__ >= 68
@@ -4362,7 +4361,7 @@
4362
4361
  Execution Slots: SLOT23
4363
4362
  ========================================================================== */
4364
4363
 
4365
- #define Q6_Ww_v6mpyacc_WwWubWbI_h __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10_vxx)
4364
+ #define Q6_Ww_v6mpyacc_WwWubWbI_h(Vxx,Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10_vxx)(Vxx,Vuu,Vvv,Iu2)
4366
4365
  #endif /* __HEXAGON_ARCH___ >= 68 */
4367
4366
 
4368
4367
  #if __HVX_ARCH__ >= 68
@@ -4373,7 +4372,7 @@
4373
4372
  Execution Slots: SLOT23
4374
4373
  ========================================================================== */
4375
4374
 
4376
- #define Q6_Ww_v6mpy_WubWbI_v __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10)
4375
+ #define Q6_Ww_v6mpy_WubWbI_v(Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10)(Vuu,Vvv,Iu2)
4377
4376
  #endif /* __HEXAGON_ARCH___ >= 68 */
4378
4377
 
4379
4378
  #if __HVX_ARCH__ >= 68
@@ -4384,9 +4383,801 @@
4384
4383
  Execution Slots: SLOT23
4385
4384
  ========================================================================== */
4386
4385
 
4387
- #define Q6_Ww_v6mpyacc_WwWubWbI_v __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10_vxx)
4386
+ #define Q6_Ww_v6mpyacc_WwWubWbI_v(Vxx,Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10_vxx)(Vxx,Vuu,Vvv,Iu2)
4387
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4388
+
4389
+ #if __HVX_ARCH__ >= 68
4390
+ /* ==========================================================================
4391
+ Assembly Syntax: Vd32.hf=vabs(Vu32.hf)
4392
+ C Intrinsic Prototype: HVX_Vector Q6_Vhf_vabs_Vhf(HVX_Vector Vu)
4393
+ Instruction Type: CVI_VX_LATE
4394
+ Execution Slots: SLOT23
4395
+ ========================================================================== */
4396
+
4397
+ #define Q6_Vhf_vabs_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_hf)(Vu)
4398
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4399
+
4400
+ #if __HVX_ARCH__ >= 68
4401
+ /* ==========================================================================
4402
+ Assembly Syntax: Vd32.sf=vabs(Vu32.sf)
4403
+ C Intrinsic Prototype: HVX_Vector Q6_Vsf_vabs_Vsf(HVX_Vector Vu)
4404
+ Instruction Type: CVI_VX_LATE
4405
+ Execution Slots: SLOT23
4406
+ ========================================================================== */
4407
+
4408
+ #define Q6_Vsf_vabs_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_sf)(Vu)
4409
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4410
+
4411
+ #if __HVX_ARCH__ >= 68
4412
+ /* ==========================================================================
4413
+ Assembly Syntax: Vd32.qf16=vadd(Vu32.hf,Vv32.hf)
4414
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
4415
+ Instruction Type: CVI_VS
4416
+ Execution Slots: SLOT0123
4417
+ ========================================================================== */
4418
+
4419
+ #define Q6_Vqf16_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf)(Vu,Vv)
4420
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4421
+
4422
+ #if __HVX_ARCH__ >= 68
4423
+ /* ==========================================================================
4424
+ Assembly Syntax: Vd32.hf=vadd(Vu32.hf,Vv32.hf)
4425
+ C Intrinsic Prototype: HVX_Vector Q6_Vhf_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
4426
+ Instruction Type: CVI_VX
4427
+ Execution Slots: SLOT23
4428
+ ========================================================================== */
4429
+
4430
+ #define Q6_Vhf_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf_hf)(Vu,Vv)
4431
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4432
+
4433
+ #if __HVX_ARCH__ >= 68
4434
+ /* ==========================================================================
4435
+ Assembly Syntax: Vd32.qf16=vadd(Vu32.qf16,Vv32.qf16)
4436
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv)
4437
+ Instruction Type: CVI_VS
4438
+ Execution Slots: SLOT0123
4439
+ ========================================================================== */
4440
+
4441
+ #define Q6_Vqf16_vadd_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf16)(Vu,Vv)
4442
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4443
+
4444
+ #if __HVX_ARCH__ >= 68
4445
+ /* ==========================================================================
4446
+ Assembly Syntax: Vd32.qf16=vadd(Vu32.qf16,Vv32.hf)
4447
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv)
4448
+ Instruction Type: CVI_VS
4449
+ Execution Slots: SLOT0123
4450
+ ========================================================================== */
4451
+
4452
+ #define Q6_Vqf16_vadd_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf16_mix)(Vu,Vv)
4453
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4454
+
4455
+ #if __HVX_ARCH__ >= 68
4456
+ /* ==========================================================================
4457
+ Assembly Syntax: Vd32.qf32=vadd(Vu32.qf32,Vv32.qf32)
4458
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv)
4459
+ Instruction Type: CVI_VS
4460
+ Execution Slots: SLOT0123
4461
+ ========================================================================== */
4462
+
4463
+ #define Q6_Vqf32_vadd_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf32)(Vu,Vv)
4464
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4465
+
4466
+ #if __HVX_ARCH__ >= 68
4467
+ /* ==========================================================================
4468
+ Assembly Syntax: Vd32.qf32=vadd(Vu32.qf32,Vv32.sf)
4469
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_Vqf32Vsf(HVX_Vector Vu, HVX_Vector Vv)
4470
+ Instruction Type: CVI_VS
4471
+ Execution Slots: SLOT0123
4472
+ ========================================================================== */
4473
+
4474
+ #define Q6_Vqf32_vadd_Vqf32Vsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf32_mix)(Vu,Vv)
4475
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4476
+
4477
+ #if __HVX_ARCH__ >= 68
4478
+ /* ==========================================================================
4479
+ Assembly Syntax: Vd32.qf32=vadd(Vu32.sf,Vv32.sf)
4480
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
4481
+ Instruction Type: CVI_VS
4482
+ Execution Slots: SLOT0123
4483
+ ========================================================================== */
4484
+
4485
+ #define Q6_Vqf32_vadd_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf)(Vu,Vv)
4486
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4487
+
4488
+ #if __HVX_ARCH__ >= 68
4489
+ /* ==========================================================================
4490
+ Assembly Syntax: Vdd32.sf=vadd(Vu32.hf,Vv32.hf)
4491
+ C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
4492
+ Instruction Type: CVI_VX_DV
4493
+ Execution Slots: SLOT23
4494
+ ========================================================================== */
4495
+
4496
+ #define Q6_Wsf_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_hf)(Vu,Vv)
4497
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4498
+
4499
+ #if __HVX_ARCH__ >= 68
4500
+ /* ==========================================================================
4501
+ Assembly Syntax: Vd32.sf=vadd(Vu32.sf,Vv32.sf)
4502
+ C Intrinsic Prototype: HVX_Vector Q6_Vsf_vadd_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
4503
+ Instruction Type: CVI_VX
4504
+ Execution Slots: SLOT23
4505
+ ========================================================================== */
4506
+
4507
+ #define Q6_Vsf_vadd_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_sf)(Vu,Vv)
4508
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4509
+
4510
+ #if __HVX_ARCH__ >= 68
4511
+ /* ==========================================================================
4512
+ Assembly Syntax: Vd32.w=vfmv(Vu32.w)
4513
+ C Intrinsic Prototype: HVX_Vector Q6_Vw_vfmv_Vw(HVX_Vector Vu)
4514
+ Instruction Type: CVI_VX_LATE
4515
+ Execution Slots: SLOT23
4516
+ ========================================================================== */
4517
+
4518
+ #define Q6_Vw_vfmv_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign_fp)(Vu)
4519
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4520
+
4521
+ #if __HVX_ARCH__ >= 68
4522
+ /* ==========================================================================
4523
+ Assembly Syntax: Vd32.hf=Vu32.qf16
4524
+ C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Vqf16(HVX_Vector Vu)
4525
+ Instruction Type: CVI_VS
4526
+ Execution Slots: SLOT0123
4527
+ ========================================================================== */
4528
+
4529
+ #define Q6_Vhf_equals_Vqf16(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_qf16)(Vu)
4530
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4531
+
4532
+ #if __HVX_ARCH__ >= 68
4533
+ /* ==========================================================================
4534
+ Assembly Syntax: Vd32.hf=Vuu32.qf32
4535
+ C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Wqf32(HVX_VectorPair Vuu)
4536
+ Instruction Type: CVI_VS
4537
+ Execution Slots: SLOT0123
4538
+ ========================================================================== */
4539
+
4540
+ #define Q6_Vhf_equals_Wqf32(Vuu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_qf32)(Vuu)
4541
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4542
+
4543
+ #if __HVX_ARCH__ >= 68
4544
+ /* ==========================================================================
4545
+ Assembly Syntax: Vd32.sf=Vu32.qf32
4546
+ C Intrinsic Prototype: HVX_Vector Q6_Vsf_equals_Vqf32(HVX_Vector Vu)
4547
+ Instruction Type: CVI_VS
4548
+ Execution Slots: SLOT0123
4549
+ ========================================================================== */
4550
+
4551
+ #define Q6_Vsf_equals_Vqf32(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_sf_qf32)(Vu)
4552
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4553
+
4554
+ #if __HVX_ARCH__ >= 68
4555
+ /* ==========================================================================
4556
+ Assembly Syntax: Vd32.b=vcvt(Vu32.hf,Vv32.hf)
4557
+ C Intrinsic Prototype: HVX_Vector Q6_Vb_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
4558
+ Instruction Type: CVI_VX
4559
+ Execution Slots: SLOT23
4560
+ ========================================================================== */
4561
+
4562
+ #define Q6_Vb_vcvt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_b_hf)(Vu,Vv)
4563
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4564
+
4565
+ #if __HVX_ARCH__ >= 68
4566
+ /* ==========================================================================
4567
+ Assembly Syntax: Vd32.h=vcvt(Vu32.hf)
4568
+ C Intrinsic Prototype: HVX_Vector Q6_Vh_vcvt_Vhf(HVX_Vector Vu)
4569
+ Instruction Type: CVI_VX
4570
+ Execution Slots: SLOT23
4571
+ ========================================================================== */
4572
+
4573
+ #define Q6_Vh_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_h_hf)(Vu)
4574
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4575
+
4576
+ #if __HVX_ARCH__ >= 68
4577
+ /* ==========================================================================
4578
+ Assembly Syntax: Vdd32.hf=vcvt(Vu32.b)
4579
+ C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_Vb(HVX_Vector Vu)
4580
+ Instruction Type: CVI_VX_DV
4581
+ Execution Slots: SLOT23
4582
+ ========================================================================== */
4583
+
4584
+ #define Q6_Whf_vcvt_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_b)(Vu)
4585
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4586
+
4587
+ #if __HVX_ARCH__ >= 68
4588
+ /* ==========================================================================
4589
+ Assembly Syntax: Vd32.hf=vcvt(Vu32.h)
4590
+ C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_Vh(HVX_Vector Vu)
4591
+ Instruction Type: CVI_VX
4592
+ Execution Slots: SLOT23
4593
+ ========================================================================== */
4594
+
4595
+ #define Q6_Vhf_vcvt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_h)(Vu)
4596
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4597
+
4598
+ #if __HVX_ARCH__ >= 68
4599
+ /* ==========================================================================
4600
+ Assembly Syntax: Vd32.hf=vcvt(Vu32.sf,Vv32.sf)
4601
+ C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
4602
+ Instruction Type: CVI_VX
4603
+ Execution Slots: SLOT23
4604
+ ========================================================================== */
4605
+
4606
+ #define Q6_Vhf_vcvt_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_sf)(Vu,Vv)
4607
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4608
+
4609
+ #if __HVX_ARCH__ >= 68
4610
+ /* ==========================================================================
4611
+ Assembly Syntax: Vdd32.hf=vcvt(Vu32.ub)
4612
+ C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_Vub(HVX_Vector Vu)
4613
+ Instruction Type: CVI_VX_DV
4614
+ Execution Slots: SLOT23
4615
+ ========================================================================== */
4616
+
4617
+ #define Q6_Whf_vcvt_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_ub)(Vu)
4618
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4619
+
4620
+ #if __HVX_ARCH__ >= 68
4621
+ /* ==========================================================================
4622
+ Assembly Syntax: Vd32.hf=vcvt(Vu32.uh)
4623
+ C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_Vuh(HVX_Vector Vu)
4624
+ Instruction Type: CVI_VX
4625
+ Execution Slots: SLOT23
4626
+ ========================================================================== */
4627
+
4628
+ #define Q6_Vhf_vcvt_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_uh)(Vu)
4629
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4630
+
4631
+ #if __HVX_ARCH__ >= 68
4632
+ /* ==========================================================================
4633
+ Assembly Syntax: Vdd32.sf=vcvt(Vu32.hf)
4634
+ C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vcvt_Vhf(HVX_Vector Vu)
4635
+ Instruction Type: CVI_VX_DV
4636
+ Execution Slots: SLOT23
4637
+ ========================================================================== */
4638
+
4639
+ #define Q6_Wsf_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_sf_hf)(Vu)
4640
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4641
+
4642
+ #if __HVX_ARCH__ >= 68
4643
+ /* ==========================================================================
4644
+ Assembly Syntax: Vd32.ub=vcvt(Vu32.hf,Vv32.hf)
4645
+ C Intrinsic Prototype: HVX_Vector Q6_Vub_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
4646
+ Instruction Type: CVI_VX
4647
+ Execution Slots: SLOT23
4648
+ ========================================================================== */
4649
+
4650
+ #define Q6_Vub_vcvt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_ub_hf)(Vu,Vv)
4651
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4652
+
4653
+ #if __HVX_ARCH__ >= 68
4654
+ /* ==========================================================================
4655
+ Assembly Syntax: Vd32.uh=vcvt(Vu32.hf)
4656
+ C Intrinsic Prototype: HVX_Vector Q6_Vuh_vcvt_Vhf(HVX_Vector Vu)
4657
+ Instruction Type: CVI_VX
4658
+ Execution Slots: SLOT23
4659
+ ========================================================================== */
4660
+
4661
+ #define Q6_Vuh_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_uh_hf)(Vu)
4662
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4663
+
4664
+ #if __HVX_ARCH__ >= 68
4665
+ /* ==========================================================================
4666
+ Assembly Syntax: Vd32.sf=vdmpy(Vu32.hf,Vv32.hf)
4667
+ C Intrinsic Prototype: HVX_Vector Q6_Vsf_vdmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
4668
+ Instruction Type: CVI_VX
4669
+ Execution Slots: SLOT23
4670
+ ========================================================================== */
4671
+
4672
+ #define Q6_Vsf_vdmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpy_sf_hf)(Vu,Vv)
4673
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4674
+
4675
+ #if __HVX_ARCH__ >= 68
4676
+ /* ==========================================================================
4677
+ Assembly Syntax: Vx32.sf+=vdmpy(Vu32.hf,Vv32.hf)
4678
+ C Intrinsic Prototype: HVX_Vector Q6_Vsf_vdmpyacc_VsfVhfVhf(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
4679
+ Instruction Type: CVI_VX
4680
+ Execution Slots: SLOT23
4681
+ ========================================================================== */
4682
+
4683
+ #define Q6_Vsf_vdmpyacc_VsfVhfVhf(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpy_sf_hf_acc)(Vx,Vu,Vv)
4684
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4685
+
4686
+ #if __HVX_ARCH__ >= 68
4687
+ /* ==========================================================================
4688
+ Assembly Syntax: Vd32.hf=vfmax(Vu32.hf,Vv32.hf)
4689
+ C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfmax_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
4690
+ Instruction Type: CVI_VX_LATE
4691
+ Execution Slots: SLOT23
4692
+ ========================================================================== */
4693
+
4694
+ #define Q6_Vhf_vfmax_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_hf)(Vu,Vv)
4695
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4696
+
4697
+ #if __HVX_ARCH__ >= 68
4698
+ /* ==========================================================================
4699
+ Assembly Syntax: Vd32.sf=vfmax(Vu32.sf,Vv32.sf)
4700
+ C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfmax_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
4701
+ Instruction Type: CVI_VX_LATE
4702
+ Execution Slots: SLOT23
4703
+ ========================================================================== */
4704
+
4705
+ #define Q6_Vsf_vfmax_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_sf)(Vu,Vv)
4388
4706
  #endif /* __HEXAGON_ARCH___ >= 68 */
4389
4707
 
4708
+ #if __HVX_ARCH__ >= 68
4709
+ /* ==========================================================================
4710
+ Assembly Syntax: Vd32.hf=vfmin(Vu32.hf,Vv32.hf)
4711
+ C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfmin_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
4712
+ Instruction Type: CVI_VX_LATE
4713
+ Execution Slots: SLOT23
4714
+ ========================================================================== */
4715
+
4716
+ #define Q6_Vhf_vfmin_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_hf)(Vu,Vv)
4717
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4718
+
4719
+ #if __HVX_ARCH__ >= 68
4720
+ /* ==========================================================================
4721
+ Assembly Syntax: Vd32.sf=vfmin(Vu32.sf,Vv32.sf)
4722
+ C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfmin_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
4723
+ Instruction Type: CVI_VX_LATE
4724
+ Execution Slots: SLOT23
4725
+ ========================================================================== */
4726
+
4727
+ #define Q6_Vsf_vfmin_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_sf)(Vu,Vv)
4728
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4729
+
4730
+ #if __HVX_ARCH__ >= 68
4731
+ /* ==========================================================================
4732
+ Assembly Syntax: Vd32.hf=vfneg(Vu32.hf)
4733
+ C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfneg_Vhf(HVX_Vector Vu)
4734
+ Instruction Type: CVI_VX_LATE
4735
+ Execution Slots: SLOT23
4736
+ ========================================================================== */
4737
+
4738
+ #define Q6_Vhf_vfneg_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_hf)(Vu)
4739
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4740
+
4741
+ #if __HVX_ARCH__ >= 68
4742
+ /* ==========================================================================
4743
+ Assembly Syntax: Vd32.sf=vfneg(Vu32.sf)
4744
+ C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfneg_Vsf(HVX_Vector Vu)
4745
+ Instruction Type: CVI_VX_LATE
4746
+ Execution Slots: SLOT23
4747
+ ========================================================================== */
4748
+
4749
+ #define Q6_Vsf_vfneg_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_sf)(Vu)
4750
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4751
+
4752
+ #if __HVX_ARCH__ >= 68
4753
+ /* ==========================================================================
4754
+ Assembly Syntax: Qd4=vcmp.gt(Vu32.hf,Vv32.hf)
4755
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
4756
+ Instruction Type: CVI_VA
4757
+ Execution Slots: SLOT0123
4758
+ ========================================================================== */
4759
+
4760
+ #define Q6_Q_vcmp_gt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf)(Vu,Vv)),-1)
4761
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4762
+
4763
+ #if __HVX_ARCH__ >= 68
4764
+ /* ==========================================================================
4765
+ Assembly Syntax: Qx4&=vcmp.gt(Vu32.hf,Vv32.hf)
4766
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
4767
+ Instruction Type: CVI_VA
4768
+ Execution Slots: SLOT0123
4769
+ ========================================================================== */
4770
+
4771
+ #define Q6_Q_vcmp_gtand_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
4772
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4773
+
4774
+ #if __HVX_ARCH__ >= 68
4775
+ /* ==========================================================================
4776
+ Assembly Syntax: Qx4|=vcmp.gt(Vu32.hf,Vv32.hf)
4777
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
4778
+ Instruction Type: CVI_VA
4779
+ Execution Slots: SLOT0123
4780
+ ========================================================================== */
4781
+
4782
+ #define Q6_Q_vcmp_gtor_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
4783
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4784
+
4785
+ #if __HVX_ARCH__ >= 68
4786
+ /* ==========================================================================
4787
+ Assembly Syntax: Qx4^=vcmp.gt(Vu32.hf,Vv32.hf)
4788
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
4789
+ Instruction Type: CVI_VA
4790
+ Execution Slots: SLOT0123
4791
+ ========================================================================== */
4792
+
4793
+ #define Q6_Q_vcmp_gtxacc_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
4794
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4795
+
4796
+ #if __HVX_ARCH__ >= 68
4797
+ /* ==========================================================================
4798
+ Assembly Syntax: Qd4=vcmp.gt(Vu32.sf,Vv32.sf)
4799
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
4800
+ Instruction Type: CVI_VA
4801
+ Execution Slots: SLOT0123
4802
+ ========================================================================== */
4803
+
4804
+ #define Q6_Q_vcmp_gt_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf)(Vu,Vv)),-1)
4805
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4806
+
4807
+ #if __HVX_ARCH__ >= 68
4808
+ /* ==========================================================================
4809
+ Assembly Syntax: Qx4&=vcmp.gt(Vu32.sf,Vv32.sf)
4810
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
4811
+ Instruction Type: CVI_VA
4812
+ Execution Slots: SLOT0123
4813
+ ========================================================================== */
4814
+
4815
+ #define Q6_Q_vcmp_gtand_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
4816
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4817
+
4818
+ #if __HVX_ARCH__ >= 68
4819
+ /* ==========================================================================
4820
+ Assembly Syntax: Qx4|=vcmp.gt(Vu32.sf,Vv32.sf)
4821
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
4822
+ Instruction Type: CVI_VA
4823
+ Execution Slots: SLOT0123
4824
+ ========================================================================== */
4825
+
4826
+ #define Q6_Q_vcmp_gtor_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
4827
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4828
+
4829
+ #if __HVX_ARCH__ >= 68
4830
+ /* ==========================================================================
4831
+ Assembly Syntax: Qx4^=vcmp.gt(Vu32.sf,Vv32.sf)
4832
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
4833
+ Instruction Type: CVI_VA
4834
+ Execution Slots: SLOT0123
4835
+ ========================================================================== */
4836
+
4837
+ #define Q6_Q_vcmp_gtxacc_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)
4838
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4839
+
4840
+ #if __HVX_ARCH__ >= 68
4841
+ /* ==========================================================================
4842
+ Assembly Syntax: Vd32.hf=vmax(Vu32.hf,Vv32.hf)
4843
+ C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmax_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
4844
+ Instruction Type: CVI_VA
4845
+ Execution Slots: SLOT0123
4846
+ ========================================================================== */
4847
+
4848
+ #define Q6_Vhf_vmax_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_hf)(Vu,Vv)
4849
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4850
+
4851
+ #if __HVX_ARCH__ >= 68
4852
+ /* ==========================================================================
4853
+ Assembly Syntax: Vd32.sf=vmax(Vu32.sf,Vv32.sf)
4854
+ C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmax_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
4855
+ Instruction Type: CVI_VA
4856
+ Execution Slots: SLOT0123
4857
+ ========================================================================== */
4858
+
4859
+ #define Q6_Vsf_vmax_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_sf)(Vu,Vv)
4860
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4861
+
4862
+ #if __HVX_ARCH__ >= 68
4863
+ /* ==========================================================================
4864
+ Assembly Syntax: Vd32.hf=vmin(Vu32.hf,Vv32.hf)
4865
+ C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmin_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
4866
+ Instruction Type: CVI_VA
4867
+ Execution Slots: SLOT0123
4868
+ ========================================================================== */
4869
+
4870
+ #define Q6_Vhf_vmin_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_hf)(Vu,Vv)
4871
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4872
+
4873
+ #if __HVX_ARCH__ >= 68
4874
+ /* ==========================================================================
4875
+ Assembly Syntax: Vd32.sf=vmin(Vu32.sf,Vv32.sf)
4876
+ C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmin_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
4877
+ Instruction Type: CVI_VA
4878
+ Execution Slots: SLOT0123
4879
+ ========================================================================== */
4880
+
4881
+ #define Q6_Vsf_vmin_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_sf)(Vu,Vv)
4882
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4883
+
4884
+ #if __HVX_ARCH__ >= 68
4885
+ /* ==========================================================================
4886
+ Assembly Syntax: Vd32.hf=vmpy(Vu32.hf,Vv32.hf)
4887
+ C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
4888
+ Instruction Type: CVI_VX
4889
+ Execution Slots: SLOT23
4890
+ ========================================================================== */
4891
+
4892
+ #define Q6_Vhf_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_hf)(Vu,Vv)
4893
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4894
+
4895
+ #if __HVX_ARCH__ >= 68
4896
+ /* ==========================================================================
4897
+ Assembly Syntax: Vx32.hf+=vmpy(Vu32.hf,Vv32.hf)
4898
+ C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmpyacc_VhfVhfVhf(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
4899
+ Instruction Type: CVI_VX
4900
+ Execution Slots: SLOT23
4901
+ ========================================================================== */
4902
+
4903
+ #define Q6_Vhf_vmpyacc_VhfVhfVhf(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_hf_acc)(Vx,Vu,Vv)
4904
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4905
+
4906
+ #if __HVX_ARCH__ >= 68
4907
+ /* ==========================================================================
4908
+ Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Vv32.qf16)
4909
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv)
4910
+ Instruction Type: CVI_VX_DV
4911
+ Execution Slots: SLOT23
4912
+ ========================================================================== */
4913
+
4914
+ #define Q6_Vqf16_vmpy_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16)(Vu,Vv)
4915
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4916
+
4917
+ #if __HVX_ARCH__ >= 68
4918
+ /* ==========================================================================
4919
+ Assembly Syntax: Vd32.qf16=vmpy(Vu32.hf,Vv32.hf)
4920
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
4921
+ Instruction Type: CVI_VX_DV
4922
+ Execution Slots: SLOT23
4923
+ ========================================================================== */
4924
+
4925
+ #define Q6_Vqf16_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16_hf)(Vu,Vv)
4926
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4927
+
4928
+ #if __HVX_ARCH__ >= 68
4929
+ /* ==========================================================================
4930
+ Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Vv32.hf)
4931
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv)
4932
+ Instruction Type: CVI_VX_DV
4933
+ Execution Slots: SLOT23
4934
+ ========================================================================== */
4935
+
4936
+ #define Q6_Vqf16_vmpy_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16_mix_hf)(Vu,Vv)
4937
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4938
+
4939
+ #if __HVX_ARCH__ >= 68
4940
+ /* ==========================================================================
4941
+ Assembly Syntax: Vd32.qf32=vmpy(Vu32.qf32,Vv32.qf32)
4942
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv)
4943
+ Instruction Type: CVI_VX_DV
4944
+ Execution Slots: SLOT23
4945
+ ========================================================================== */
4946
+
4947
+ #define Q6_Vqf32_vmpy_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32)(Vu,Vv)
4948
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4949
+
4950
+ #if __HVX_ARCH__ >= 68
4951
+ /* ==========================================================================
4952
+ Assembly Syntax: Vdd32.qf32=vmpy(Vu32.hf,Vv32.hf)
4953
+ C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
4954
+ Instruction Type: CVI_VX_DV
4955
+ Execution Slots: SLOT23
4956
+ ========================================================================== */
4957
+
4958
+ #define Q6_Wqf32_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_hf)(Vu,Vv)
4959
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4960
+
4961
+ #if __HVX_ARCH__ >= 68
4962
+ /* ==========================================================================
4963
+ Assembly Syntax: Vdd32.qf32=vmpy(Vu32.qf16,Vv32.hf)
4964
+ C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv)
4965
+ Instruction Type: CVI_VX_DV
4966
+ Execution Slots: SLOT23
4967
+ ========================================================================== */
4968
+
4969
+ #define Q6_Wqf32_vmpy_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_mix_hf)(Vu,Vv)
4970
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4971
+
4972
+ #if __HVX_ARCH__ >= 68
4973
+ /* ==========================================================================
4974
+ Assembly Syntax: Vdd32.qf32=vmpy(Vu32.qf16,Vv32.qf16)
4975
+ C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv)
4976
+ Instruction Type: CVI_VX_DV
4977
+ Execution Slots: SLOT23
4978
+ ========================================================================== */
4979
+
4980
+ #define Q6_Wqf32_vmpy_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_qf16)(Vu,Vv)
4981
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4982
+
4983
+ #if __HVX_ARCH__ >= 68
4984
+ /* ==========================================================================
4985
+ Assembly Syntax: Vd32.qf32=vmpy(Vu32.sf,Vv32.sf)
4986
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
4987
+ Instruction Type: CVI_VX_DV
4988
+ Execution Slots: SLOT23
4989
+ ========================================================================== */
4990
+
4991
+ #define Q6_Vqf32_vmpy_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_sf)(Vu,Vv)
4992
+ #endif /* __HEXAGON_ARCH___ >= 68 */
4993
+
4994
+ #if __HVX_ARCH__ >= 68
4995
+ /* ==========================================================================
4996
+ Assembly Syntax: Vdd32.sf=vmpy(Vu32.hf,Vv32.hf)
4997
+ C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
4998
+ Instruction Type: CVI_VX_DV
4999
+ Execution Slots: SLOT23
5000
+ ========================================================================== */
5001
+
5002
+ #define Q6_Wsf_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_hf)(Vu,Vv)
5003
+ #endif /* __HEXAGON_ARCH___ >= 68 */
5004
+
5005
+ #if __HVX_ARCH__ >= 68
5006
+ /* ==========================================================================
5007
+ Assembly Syntax: Vxx32.sf+=vmpy(Vu32.hf,Vv32.hf)
5008
+ C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpyacc_WsfVhfVhf(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
5009
+ Instruction Type: CVI_VX_DV
5010
+ Execution Slots: SLOT23
5011
+ ========================================================================== */
5012
+
5013
+ #define Q6_Wsf_vmpyacc_WsfVhfVhf(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_hf_acc)(Vxx,Vu,Vv)
5014
+ #endif /* __HEXAGON_ARCH___ >= 68 */
5015
+
5016
+ #if __HVX_ARCH__ >= 68
5017
+ /* ==========================================================================
5018
+ Assembly Syntax: Vd32.sf=vmpy(Vu32.sf,Vv32.sf)
5019
+ C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmpy_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
5020
+ Instruction Type: CVI_VX_DV
5021
+ Execution Slots: SLOT23
5022
+ ========================================================================== */
5023
+
5024
+ #define Q6_Vsf_vmpy_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_sf)(Vu,Vv)
5025
+ #endif /* __HEXAGON_ARCH___ >= 68 */
5026
+
5027
+ #if __HVX_ARCH__ >= 68
5028
+ /* ==========================================================================
5029
+ Assembly Syntax: Vd32.qf16=vsub(Vu32.hf,Vv32.hf)
5030
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
5031
+ Instruction Type: CVI_VS
5032
+ Execution Slots: SLOT0123
5033
+ ========================================================================== */
5034
+
5035
+ #define Q6_Vqf16_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf)(Vu,Vv)
5036
+ #endif /* __HEXAGON_ARCH___ >= 68 */
5037
+
5038
+ #if __HVX_ARCH__ >= 68
5039
+ /* ==========================================================================
5040
+ Assembly Syntax: Vd32.hf=vsub(Vu32.hf,Vv32.hf)
5041
+ C Intrinsic Prototype: HVX_Vector Q6_Vhf_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
5042
+ Instruction Type: CVI_VX
5043
+ Execution Slots: SLOT23
5044
+ ========================================================================== */
5045
+
5046
+ #define Q6_Vhf_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_hf)(Vu,Vv)
5047
+ #endif /* __HEXAGON_ARCH___ >= 68 */
5048
+
5049
+ #if __HVX_ARCH__ >= 68
5050
+ /* ==========================================================================
5051
+ Assembly Syntax: Vd32.qf16=vsub(Vu32.qf16,Vv32.qf16)
5052
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv)
5053
+ Instruction Type: CVI_VS
5054
+ Execution Slots: SLOT0123
5055
+ ========================================================================== */
5056
+
5057
+ #define Q6_Vqf16_vsub_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf16)(Vu,Vv)
5058
+ #endif /* __HEXAGON_ARCH___ >= 68 */
5059
+
5060
+ #if __HVX_ARCH__ >= 68
5061
+ /* ==========================================================================
5062
+ Assembly Syntax: Vd32.qf16=vsub(Vu32.qf16,Vv32.hf)
5063
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv)
5064
+ Instruction Type: CVI_VS
5065
+ Execution Slots: SLOT0123
5066
+ ========================================================================== */
5067
+
5068
+ #define Q6_Vqf16_vsub_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf16_mix)(Vu,Vv)
5069
+ #endif /* __HEXAGON_ARCH___ >= 68 */
5070
+
5071
+ #if __HVX_ARCH__ >= 68
5072
+ /* ==========================================================================
5073
+ Assembly Syntax: Vd32.qf32=vsub(Vu32.qf32,Vv32.qf32)
5074
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv)
5075
+ Instruction Type: CVI_VS
5076
+ Execution Slots: SLOT0123
5077
+ ========================================================================== */
5078
+
5079
+ #define Q6_Vqf32_vsub_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf32)(Vu,Vv)
5080
+ #endif /* __HEXAGON_ARCH___ >= 68 */
5081
+
5082
+ #if __HVX_ARCH__ >= 68
5083
+ /* ==========================================================================
5084
+ Assembly Syntax: Vd32.qf32=vsub(Vu32.qf32,Vv32.sf)
5085
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_Vqf32Vsf(HVX_Vector Vu, HVX_Vector Vv)
5086
+ Instruction Type: CVI_VS
5087
+ Execution Slots: SLOT0123
5088
+ ========================================================================== */
5089
+
5090
+ #define Q6_Vqf32_vsub_Vqf32Vsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf32_mix)(Vu,Vv)
5091
+ #endif /* __HEXAGON_ARCH___ >= 68 */
5092
+
5093
+ #if __HVX_ARCH__ >= 68
5094
+ /* ==========================================================================
5095
+ Assembly Syntax: Vd32.qf32=vsub(Vu32.sf,Vv32.sf)
5096
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
5097
+ Instruction Type: CVI_VS
5098
+ Execution Slots: SLOT0123
5099
+ ========================================================================== */
5100
+
5101
+ #define Q6_Vqf32_vsub_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf)(Vu,Vv)
5102
+ #endif /* __HEXAGON_ARCH___ >= 68 */
5103
+
5104
+ #if __HVX_ARCH__ >= 68
5105
+ /* ==========================================================================
5106
+ Assembly Syntax: Vdd32.sf=vsub(Vu32.hf,Vv32.hf)
5107
+ C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)
5108
+ Instruction Type: CVI_VX_DV
5109
+ Execution Slots: SLOT23
5110
+ ========================================================================== */
5111
+
5112
+ #define Q6_Wsf_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_hf)(Vu,Vv)
5113
+ #endif /* __HEXAGON_ARCH___ >= 68 */
5114
+
5115
+ #if __HVX_ARCH__ >= 68
5116
+ /* ==========================================================================
5117
+ Assembly Syntax: Vd32.sf=vsub(Vu32.sf,Vv32.sf)
5118
+ C Intrinsic Prototype: HVX_Vector Q6_Vsf_vsub_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)
5119
+ Instruction Type: CVI_VX
5120
+ Execution Slots: SLOT23
5121
+ ========================================================================== */
5122
+
5123
+ #define Q6_Vsf_vsub_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_sf)(Vu,Vv)
5124
+ #endif /* __HEXAGON_ARCH___ >= 68 */
5125
+
5126
+ #if __HVX_ARCH__ >= 69
5127
+ /* ==========================================================================
5128
+ Assembly Syntax: Vd32.ub=vasr(Vuu32.uh,Vv32.ub):rnd:sat
5129
+ C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_WuhVub_rnd_sat(HVX_VectorPair Vuu, HVX_Vector Vv)
5130
+ Instruction Type: CVI_VS
5131
+ Execution Slots: SLOT0123
5132
+ ========================================================================== */
5133
+
5134
+ #define Q6_Vub_vasr_WuhVub_rnd_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvuhubrndsat)(Vuu,Vv)
5135
+ #endif /* __HEXAGON_ARCH___ >= 69 */
5136
+
5137
+ #if __HVX_ARCH__ >= 69
5138
+ /* ==========================================================================
5139
+ Assembly Syntax: Vd32.ub=vasr(Vuu32.uh,Vv32.ub):sat
5140
+ C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_WuhVub_sat(HVX_VectorPair Vuu, HVX_Vector Vv)
5141
+ Instruction Type: CVI_VS
5142
+ Execution Slots: SLOT0123
5143
+ ========================================================================== */
5144
+
5145
+ #define Q6_Vub_vasr_WuhVub_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvuhubsat)(Vuu,Vv)
5146
+ #endif /* __HEXAGON_ARCH___ >= 69 */
5147
+
5148
+ #if __HVX_ARCH__ >= 69
5149
+ /* ==========================================================================
5150
+ Assembly Syntax: Vd32.uh=vasr(Vuu32.w,Vv32.uh):rnd:sat
5151
+ C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_WwVuh_rnd_sat(HVX_VectorPair Vuu, HVX_Vector Vv)
5152
+ Instruction Type: CVI_VS
5153
+ Execution Slots: SLOT0123
5154
+ ========================================================================== */
5155
+
5156
+ #define Q6_Vuh_vasr_WwVuh_rnd_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvwuhrndsat)(Vuu,Vv)
5157
+ #endif /* __HEXAGON_ARCH___ >= 69 */
5158
+
5159
+ #if __HVX_ARCH__ >= 69
5160
+ /* ==========================================================================
5161
+ Assembly Syntax: Vd32.uh=vasr(Vuu32.w,Vv32.uh):sat
5162
+ C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_WwVuh_sat(HVX_VectorPair Vuu, HVX_Vector Vv)
5163
+ Instruction Type: CVI_VS
5164
+ Execution Slots: SLOT0123
5165
+ ========================================================================== */
5166
+
5167
+ #define Q6_Vuh_vasr_WwVuh_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvwuhsat)(Vuu,Vv)
5168
+ #endif /* __HEXAGON_ARCH___ >= 69 */
5169
+
5170
+ #if __HVX_ARCH__ >= 69
5171
+ /* ==========================================================================
5172
+ Assembly Syntax: Vd32.uh=vmpy(Vu32.uh,Vv32.uh):>>16
5173
+ C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmpy_VuhVuh_rs16(HVX_Vector Vu, HVX_Vector Vv)
5174
+ Instruction Type: CVI_VX
5175
+ Execution Slots: SLOT23
5176
+ ========================================================================== */
5177
+
5178
+ #define Q6_Vuh_vmpy_VuhVuh_rs16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhvs)(Vu,Vv)
5179
+ #endif /* __HEXAGON_ARCH___ >= 69 */
5180
+
4390
5181
  #endif /* __HVX__ */
4391
5182
 
4392
5183
  #endif