@nativescript/ios 9.0.0-esm.3 → 9.0.0-napi-v8.0

package/framework/internal/metadata-generator-arm64/bin/lib/clang/17/include/fxsrintrin.h

@@ -1,91 +0,0 @@
-/*===---- fxsrintrin.h - FXSR intrinsic ------------------------------------===
- *
- * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
- * See https://llvm.org/LICENSE.txt for license information.
- * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
- *
- *===-----------------------------------------------------------------------===
- */
-
-#ifndef __IMMINTRIN_H
-#error "Never use <fxsrintrin.h> directly; include <immintrin.h> instead."
-#endif
-
-#ifndef __FXSRINTRIN_H
-#define __FXSRINTRIN_H
-
-#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__,  __target__("fxsr")))
-
-/// Saves the XMM, MMX, MXCSR and x87 FPU registers into a 512-byte
-///    memory region pointed to by the input parameter \a __p.
-///
-/// \headerfile <x86intrin.h>
-///
-/// This intrinsic corresponds to the <c> FXSAVE </c> instruction.
-///
-/// \param __p
-///    A pointer to a 512-byte memory region. The beginning of this memory
-///    region should be aligned on a 16-byte boundary.
-static __inline__ void __DEFAULT_FN_ATTRS
-_fxsave(void *__p)
-{
-  __builtin_ia32_fxsave(__p);
-}
-
-/// Restores the XMM, MMX, MXCSR and x87 FPU registers from the 512-byte
-///    memory region pointed to by the input parameter \a __p. The contents of
-///    this memory region should have been written to by a previous \c _fxsave
-///    or \c _fxsave64 intrinsic.
-///
-/// \headerfile <x86intrin.h>
-///
-/// This intrinsic corresponds to the <c> FXRSTOR </c> instruction.
-///
-/// \param __p
-///    A pointer to a 512-byte memory region. The beginning of this memory
-///    region should be aligned on a 16-byte boundary.
-static __inline__ void __DEFAULT_FN_ATTRS
-_fxrstor(void *__p)
-{
-  __builtin_ia32_fxrstor(__p);
-}
-
-#ifdef __x86_64__
-/// Saves the XMM, MMX, MXCSR and x87 FPU registers into a 512-byte
-///    memory region pointed to by the input parameter \a __p.
-///
-/// \headerfile <x86intrin.h>
-///
-/// This intrinsic corresponds to the <c> FXSAVE64 </c> instruction.
-///
-/// \param __p
-///    A pointer to a 512-byte memory region. The beginning of this memory
-///    region should be aligned on a 16-byte boundary.
-static __inline__ void __DEFAULT_FN_ATTRS
-_fxsave64(void *__p)
-{
-  __builtin_ia32_fxsave64(__p);
-}
-
-/// Restores the XMM, MMX, MXCSR and x87 FPU registers from the 512-byte
-///    memory region pointed to by the input parameter \a __p. The contents of
-///    this memory region should have been written to by a previous \c _fxsave
-///    or \c _fxsave64 intrinsic.
-///
-/// \headerfile <x86intrin.h>
-///
-/// This intrinsic corresponds to the <c> FXRSTOR64 </c> instruction.
-///
-/// \param __p
-///    A pointer to a 512-byte memory region. The beginning of this memory
-///    region should be aligned on a 16-byte boundary.
-static __inline__ void __DEFAULT_FN_ATTRS
-_fxrstor64(void *__p)
-{
-  __builtin_ia32_fxrstor64(__p);
-}
-#endif
-
-#undef __DEFAULT_FN_ATTRS
-
-#endif

package/framework/internal/metadata-generator-arm64/bin/lib/clang/17/include/gfniintrin.h

@@ -1,194 +0,0 @@
-/*===----------------- gfniintrin.h - GFNI intrinsics ----------------------===
- *
- *
- * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
- * See https://llvm.org/LICENSE.txt for license information.
- * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
- *
- *===-----------------------------------------------------------------------===
- */
-#ifndef __IMMINTRIN_H
-#error "Never use <gfniintrin.h> directly; include <immintrin.h> instead."
-#endif
-
-#ifndef __GFNIINTRIN_H
-#define __GFNIINTRIN_H
-
-/* Default attributes for simple form (no masking). */
-#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("gfni"), __min_vector_width__(128)))
-
-/* Default attributes for YMM unmasked form. */
-#define __DEFAULT_FN_ATTRS_Y __attribute__((__always_inline__, __nodebug__, __target__("avx,gfni"), __min_vector_width__(256)))
-
-/* Default attributes for ZMM unmasked forms. */
-#define __DEFAULT_FN_ATTRS_Z __attribute__((__always_inline__, __nodebug__, __target__("avx512f,gfni"), __min_vector_width__(512)))
-/* Default attributes for ZMM masked forms. */
-#define __DEFAULT_FN_ATTRS_Z_MASK __attribute__((__always_inline__, __nodebug__, __target__("avx512bw,gfni"), __min_vector_width__(512)))
-
-/* Default attributes for VLX masked forms. */
-#define __DEFAULT_FN_ATTRS_VL128 __attribute__((__always_inline__, __nodebug__, __target__("avx512bw,avx512vl,gfni"), __min_vector_width__(128)))
-#define __DEFAULT_FN_ATTRS_VL256 __attribute__((__always_inline__, __nodebug__, __target__("avx512bw,avx512vl,gfni"), __min_vector_width__(256)))
-
-#define _mm_gf2p8affineinv_epi64_epi8(A, B, I) \
-  ((__m128i)__builtin_ia32_vgf2p8affineinvqb_v16qi((__v16qi)(__m128i)(A), \
-                                                   (__v16qi)(__m128i)(B), \
-                                                   (char)(I)))
-
-#define _mm_gf2p8affine_epi64_epi8(A, B, I) \
-  ((__m128i)__builtin_ia32_vgf2p8affineqb_v16qi((__v16qi)(__m128i)(A), \
-                                                   (__v16qi)(__m128i)(B), \
-                                                   (char)(I)))
-
-static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_gf2p8mul_epi8(__m128i __A, __m128i __B)
-{
-  return (__m128i) __builtin_ia32_vgf2p8mulb_v16qi((__v16qi) __A,
-              (__v16qi) __B);
-}
-
-#ifdef __AVXINTRIN_H
-#define _mm256_gf2p8affineinv_epi64_epi8(A, B, I) \
-  ((__m256i)__builtin_ia32_vgf2p8affineinvqb_v32qi((__v32qi)(__m256i)(A), \
-                                                   (__v32qi)(__m256i)(B), \
-                                                   (char)(I)))
-
-#define _mm256_gf2p8affine_epi64_epi8(A, B, I) \
-  ((__m256i)__builtin_ia32_vgf2p8affineqb_v32qi((__v32qi)(__m256i)(A), \
-                                                   (__v32qi)(__m256i)(B), \
-                                                   (char)(I)))
-
-static __inline__ __m256i __DEFAULT_FN_ATTRS_Y
-_mm256_gf2p8mul_epi8(__m256i __A, __m256i __B)
-{
-  return (__m256i) __builtin_ia32_vgf2p8mulb_v32qi((__v32qi) __A,
-              (__v32qi) __B);
-}
-#endif /* __AVXINTRIN_H */
-
-#ifdef __AVX512BWINTRIN_H
-#define _mm512_gf2p8affineinv_epi64_epi8(A, B, I) \
-  ((__m512i)__builtin_ia32_vgf2p8affineinvqb_v64qi((__v64qi)(__m512i)(A), \
-                                                   (__v64qi)(__m512i)(B), \
-                                                   (char)(I)))
-
-#define _mm512_mask_gf2p8affineinv_epi64_epi8(S, U, A, B, I) \
-  ((__m512i)__builtin_ia32_selectb_512((__mmask64)(U), \
-         (__v64qi)_mm512_gf2p8affineinv_epi64_epi8(A, B, I), \
-         (__v64qi)(__m512i)(S)))
-
-#define _mm512_maskz_gf2p8affineinv_epi64_epi8(U, A, B, I) \
-  _mm512_mask_gf2p8affineinv_epi64_epi8((__m512i)_mm512_setzero_si512(), \
-         U, A, B, I)
-
-#define _mm512_gf2p8affine_epi64_epi8(A, B, I) \
-  ((__m512i)__builtin_ia32_vgf2p8affineqb_v64qi((__v64qi)(__m512i)(A), \
-                                                   (__v64qi)(__m512i)(B), \
-                                                   (char)(I)))
-
-#define _mm512_mask_gf2p8affine_epi64_epi8(S, U, A, B, I) \
-  ((__m512i)__builtin_ia32_selectb_512((__mmask64)(U), \
-         (__v64qi)_mm512_gf2p8affine_epi64_epi8((A), (B), (I)), \
-         (__v64qi)(__m512i)(S)))
-
-#define _mm512_maskz_gf2p8affine_epi64_epi8(U, A, B, I) \
-  _mm512_mask_gf2p8affine_epi64_epi8((__m512i)_mm512_setzero_si512(), \
-         U, A, B, I)
-
-static __inline__ __m512i __DEFAULT_FN_ATTRS_Z
-_mm512_gf2p8mul_epi8(__m512i __A, __m512i __B)
-{
-  return (__m512i) __builtin_ia32_vgf2p8mulb_v64qi((__v64qi) __A,
-              (__v64qi) __B);
-}
-
-static __inline__ __m512i __DEFAULT_FN_ATTRS_Z_MASK
-_mm512_mask_gf2p8mul_epi8(__m512i __S, __mmask64 __U, __m512i __A, __m512i __B)
-{
-  return (__m512i) __builtin_ia32_selectb_512(__U,
-              (__v64qi) _mm512_gf2p8mul_epi8(__A, __B),
-              (__v64qi) __S);
-}
-
-static __inline__ __m512i __DEFAULT_FN_ATTRS_Z_MASK
-_mm512_maskz_gf2p8mul_epi8(__mmask64 __U, __m512i __A, __m512i __B)
-{
-  return _mm512_mask_gf2p8mul_epi8((__m512i)_mm512_setzero_si512(),
-              __U, __A, __B);
-}
-#endif /* __AVX512BWINTRIN_H */
-
-#ifdef __AVX512VLBWINTRIN_H
-#define _mm_mask_gf2p8affineinv_epi64_epi8(S, U, A, B, I) \
-  ((__m128i)__builtin_ia32_selectb_128((__mmask16)(U), \
-         (__v16qi)_mm_gf2p8affineinv_epi64_epi8(A, B, I), \
-         (__v16qi)(__m128i)(S)))
-
-#define _mm_maskz_gf2p8affineinv_epi64_epi8(U, A, B, I) \
-  _mm_mask_gf2p8affineinv_epi64_epi8((__m128i)_mm_setzero_si128(), \
-         U, A, B, I)
-
-#define _mm256_mask_gf2p8affineinv_epi64_epi8(S, U, A, B, I) \
-  ((__m256i)__builtin_ia32_selectb_256((__mmask32)(U), \
-         (__v32qi)_mm256_gf2p8affineinv_epi64_epi8(A, B, I), \
-         (__v32qi)(__m256i)(S)))
-
-#define _mm256_maskz_gf2p8affineinv_epi64_epi8(U, A, B, I) \
-  _mm256_mask_gf2p8affineinv_epi64_epi8((__m256i)_mm256_setzero_si256(), \
-         U, A, B, I)
-
-#define _mm_mask_gf2p8affine_epi64_epi8(S, U, A, B, I) \
-  ((__m128i)__builtin_ia32_selectb_128((__mmask16)(U), \
-         (__v16qi)_mm_gf2p8affine_epi64_epi8(A, B, I), \
-         (__v16qi)(__m128i)(S)))
-
-#define _mm_maskz_gf2p8affine_epi64_epi8(U, A, B, I) \
-  _mm_mask_gf2p8affine_epi64_epi8((__m128i)_mm_setzero_si128(), U, A, B, I)
-
-#define _mm256_mask_gf2p8affine_epi64_epi8(S, U, A, B, I) \
-  ((__m256i)__builtin_ia32_selectb_256((__mmask32)(U), \
-         (__v32qi)_mm256_gf2p8affine_epi64_epi8(A, B, I), \
-         (__v32qi)(__m256i)(S)))
-
-#define _mm256_maskz_gf2p8affine_epi64_epi8(U, A, B, I) \
-  _mm256_mask_gf2p8affine_epi64_epi8((__m256i)_mm256_setzero_si256(), \
-         U, A, B, I)
-
-static __inline__ __m128i __DEFAULT_FN_ATTRS_VL128
-_mm_mask_gf2p8mul_epi8(__m128i __S, __mmask16 __U, __m128i __A, __m128i __B)
-{
-  return (__m128i) __builtin_ia32_selectb_128(__U,
-              (__v16qi) _mm_gf2p8mul_epi8(__A, __B),
-              (__v16qi) __S);
-}
-
-static __inline__ __m128i __DEFAULT_FN_ATTRS_VL128
-_mm_maskz_gf2p8mul_epi8(__mmask16 __U, __m128i __A, __m128i __B)
-{
-  return _mm_mask_gf2p8mul_epi8((__m128i)_mm_setzero_si128(),
-              __U, __A, __B);
-}
-
-static __inline__ __m256i __DEFAULT_FN_ATTRS_VL256
-_mm256_mask_gf2p8mul_epi8(__m256i __S, __mmask32 __U, __m256i __A, __m256i __B)
-{
-  return (__m256i) __builtin_ia32_selectb_256(__U,
-              (__v32qi) _mm256_gf2p8mul_epi8(__A, __B),
-              (__v32qi) __S);
-}
-
-static __inline__ __m256i __DEFAULT_FN_ATTRS_VL256
-_mm256_maskz_gf2p8mul_epi8(__mmask32 __U, __m256i __A, __m256i __B)
-{
-  return _mm256_mask_gf2p8mul_epi8((__m256i)_mm256_setzero_si256(),
-              __U, __A, __B);
-}
-#endif /* __AVX512VLBWINTRIN_H */
-
-#undef __DEFAULT_FN_ATTRS
-#undef __DEFAULT_FN_ATTRS_Y
-#undef __DEFAULT_FN_ATTRS_Z
-#undef __DEFAULT_FN_ATTRS_VL128
-#undef __DEFAULT_FN_ATTRS_VL256
-
-#endif /* __GFNIINTRIN_H */
-

package/framework/internal/metadata-generator-arm64/bin/lib/clang/17/include/hexagon_circ_brev_intrinsics.h

@@ -1,298 +0,0 @@
-//===----------------------------------------------------------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef _HEXAGON_CIRC_BREV_INTRINSICS_H_
-#define _HEXAGON_CIRC_BREV_INTRINSICS_H_ 1
-
-#include <hexagon_protos.h>
-#include <stdint.h>
-
-/* Circular Load */
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void Q6_circ_load_update_D(Word64 dst, Word64 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_circ_load_update_D(dest,ptr,incr,bufsize,K)  \
-    { ptr = (int64_t *) HEXAGON_circ_ldd (ptr, &(dest), ((((K)+1)<<24)|((bufsize)<<3)), ((incr)*8)); }
-
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void Q6_circ_load_update_W(Word32 dst, Word32 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_circ_load_update_W(dest,ptr,incr,bufsize,K)  \
-    { ptr = (int *) HEXAGON_circ_ldw (ptr, &(dest), (((K)<<24)|((bufsize)<<2)), ((incr)*4)); }
-
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void Q6_circ_load_update_H(Word16 dst, Word16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_circ_load_update_H(dest,ptr,incr,bufsize,K)  \
-    { ptr = (int16_t *) HEXAGON_circ_ldh (ptr, &(dest), ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); }
-
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void Q6_circ_load_update_UH( UWord16 dst,  UWord16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_circ_load_update_UH(dest,ptr,incr,bufsize,K) \
-    { ptr = (uint16_t *) HEXAGON_circ_lduh (ptr, &(dest), ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); }
-
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void Q6_circ_load_update_B(Word8 dst, Word8 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_circ_load_update_B(dest,ptr,incr,bufsize,K)  \
-    { ptr = (int8_t *) HEXAGON_circ_ldb (ptr, &(dest), ((((K)-2)<<24)|(bufsize)), incr); }
-
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void  Q6_circ_load_update_UB(UWord8 dst, UWord8 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_circ_load_update_UB(dest,ptr,incr,bufsize,K) \
-    { ptr = (uint8_t *) HEXAGON_circ_ldub (ptr, &(dest), ((((K)-2)<<24)|(bufsize)), incr); }
-
-/* Circular Store */
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void Q6_circ_store_update_D(Word64 *src, Word64 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_circ_store_update_D(src,ptr,incr,bufsize,K)  \
-    { ptr = (int64_t *) HEXAGON_circ_std (ptr, src, ((((K)+1)<<24)|((bufsize)<<3)), ((incr)*8)); }
-
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void Q6_circ_store_update_W(Word32 *src, Word32 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_circ_store_update_W(src,ptr,incr,bufsize,K)  \
-    { ptr = (int *) HEXAGON_circ_stw (ptr, src, (((K)<<24)|((bufsize)<<2)), ((incr)*4)); }
-
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void Q6_circ_store_update_HL(Word16 *src, Word16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_circ_store_update_HL(src,ptr,incr,bufsize,K) \
-    { ptr = (int16_t *) HEXAGON_circ_sth (ptr, src, ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); }
-
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void Q6_circ_store_update_HH(Word16 *src, Word16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_circ_store_update_HH(src,ptr,incr,bufsize,K) \
-    { ptr = (int16_t *) HEXAGON_circ_sthhi (ptr, src, ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); }
-
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void Q6_circ_store_update_B(Word8 *src, Word8 *ptr, UWord32 I4, UWord32 bufsize,  UWord64 K)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_circ_store_update_B(src,ptr,incr,bufsize,K)  \
-    { ptr = (int8_t *) HEXAGON_circ_stb (ptr, src, ((((K)-2)<<24)|(bufsize)), incr); }
-
-
-/* Bit Reverse Load */
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void Q6_bitrev_load_update_D(Word64 dst, Word64 *ptr, UWord32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_bitrev_load_update_D(dest,ptr,log2bufsize) \
-    { ptr = (int64_t *) HEXAGON_brev_ldd (ptr, &(dest), (1<<(16-((log2bufsize) + 3)))); }
-
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void Q6_bitrev_load_update_W(Word32 dst, Word32 *ptr, UWord32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_bitrev_load_update_W(dest,ptr,log2bufsize) \
-    { ptr = (int *) HEXAGON_brev_ldw (ptr, &(dest), (1<<(16-((log2bufsize) + 2)))); }
-
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void Q6_bitrev_load_update_H(Word16 dst, Word16 *ptr, UWord32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_bitrev_load_update_H(dest,ptr,log2bufsize) \
-    { ptr = (int16_t *) HEXAGON_brev_ldh (ptr, &(dest), (1<<(16-((log2bufsize) + 1)))); }
-
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void Q6_bitrev_load_update_UH(UWord16 dst,  UWord16 *ptr, UWord32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_bitrev_load_update_UH(dest,ptr,log2bufsize) \
-    { ptr = (uint16_t *) HEXAGON_brev_lduh (ptr, &(dest), (1<<(16-((log2bufsize) + 1)))); }
-
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void Q6_bitrev_load_update_B(Word8 dst, Word8 *ptr, UWord32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_bitrev_load_update_B(dest,ptr,log2bufsize) \
-    { ptr = (int8_t *) HEXAGON_brev_ldb (ptr, &(dest), (1<<(16-((log2bufsize))))); }
-
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void Q6_bitrev_load_update_UB(UWord8 dst, UWord8 *ptr, UWord32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_bitrev_load_update_UB(dest,ptr,log2bufsize) \
-    { ptr = (uint8_t *) HEXAGON_brev_ldub (ptr, &(dest), (1<<(16-((log2bufsize))))); }
-
-/* Bit Reverse Store */
-
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void Q6_bitrev_store_update_D(Word64 *src, Word64 *ptr, UWord32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_bitrev_store_update_D(src,ptr,log2bufsize)   \
-    { ptr = (int64_t *) HEXAGON_brev_std (ptr, src, (1<<(16-((log2bufsize) + 3)))); }
-
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void Q6_bitrev_store_update_W(Word32 *src, Word32 *ptr, UWord32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_bitrev_store_update_W(src,ptr,log2bufsize)   \
-    { ptr = (int *) HEXAGON_brev_stw (ptr, src, (1<<(16-((log2bufsize) + 2)))); }
-
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void Q6_bitrev_store_update_HL(Word16 *src, Word16 *ptr, Word32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_bitrev_store_update_HL(src,ptr,log2bufsize)   \
-    { ptr = (int16_t *) HEXAGON_brev_sth (ptr, src, (1<<(16-((log2bufsize) + 1)))); }
-
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void Q6_bitrev_store_update_HH(Word16 *src, Word16 *ptr, UWord32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_bitrev_store_update_HH(src,ptr,log2bufsize)   \
-    { ptr = (int16_t *) HEXAGON_brev_sthhi (ptr, src, (1<<(16-((log2bufsize) + 1)))); }
-
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: void Q6_bitrev_store_update_B(Word8 *src, Word8 *ptr, UWord32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#define Q6_bitrev_store_update_B(src,ptr,log2bufsize)   \
-    { ptr = (int8_t *) HEXAGON_brev_stb (ptr, src, (1<<(16-((log2bufsize))))); }
-
-
-#define HEXAGON_circ_ldd  __builtin_circ_ldd
-#define HEXAGON_circ_ldw  __builtin_circ_ldw
-#define HEXAGON_circ_ldh  __builtin_circ_ldh
-#define HEXAGON_circ_lduh __builtin_circ_lduh
-#define HEXAGON_circ_ldb  __builtin_circ_ldb
-#define HEXAGON_circ_ldub __builtin_circ_ldub
-
-
-#define HEXAGON_circ_std  __builtin_circ_std
-#define HEXAGON_circ_stw  __builtin_circ_stw
-#define HEXAGON_circ_sth  __builtin_circ_sth
-#define HEXAGON_circ_sthhi __builtin_circ_sthhi
-#define HEXAGON_circ_stb  __builtin_circ_stb
-
-
-#define HEXAGON_brev_ldd  __builtin_brev_ldd
-#define HEXAGON_brev_ldw  __builtin_brev_ldw
-#define HEXAGON_brev_ldh  __builtin_brev_ldh
-#define HEXAGON_brev_lduh __builtin_brev_lduh
-#define HEXAGON_brev_ldb  __builtin_brev_ldb
-#define HEXAGON_brev_ldub __builtin_brev_ldub
-
-#define HEXAGON_brev_std  __builtin_brev_std
-#define HEXAGON_brev_stw  __builtin_brev_stw
-#define HEXAGON_brev_sth  __builtin_brev_sth
-#define HEXAGON_brev_sthhi __builtin_brev_sthhi
-#define HEXAGON_brev_stb  __builtin_brev_stb
-
-#ifdef __HVX__
-/* ==========================================================================
-   Assembly Syntax:       if (Qt) vmem(Rt+#0) = Vs
-   C Intrinsic Prototype: void Q6_vmaskedstoreq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs)
-   Instruction Type:      COPROC_VMEM
-   Execution Slots:       SLOT0
-   ========================================================================== */
-
-#define Q6_vmaskedstoreq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstoreq)
-
-/* ==========================================================================
-   Assembly Syntax:       if (!Qt) vmem(Rt+#0) = Vs
-   C Intrinsic Prototype: void Q6_vmaskedstorenq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs)
-   Instruction Type:      COPROC_VMEM
-   Execution Slots:       SLOT0
-   ========================================================================== */
-
-#define Q6_vmaskedstorenq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstorenq)
-
-/* ==========================================================================
-   Assembly Syntax:       if (Qt) vmem(Rt+#0):nt = Vs
-   C Intrinsic Prototype: void Q6_vmaskedstorentq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs)
-   Instruction Type:      COPROC_VMEM
-   Execution Slots:       SLOT0
-   ========================================================================== */
-
-#define Q6_vmaskedstorentq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstorentq)
-
-/* ==========================================================================
-   Assembly Syntax:       if (!Qt) vmem(Rt+#0):nt = Vs
-   C Intrinsic Prototype: void Q6_vmaskedstorentnq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs)
-   Instruction Type:      COPROC_VMEM
-   Execution Slots:       SLOT0
-   ========================================================================== */
-
-#define Q6_vmaskedstorentnq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstorentnq)
-
-#endif
-
-
-#endif  /* #ifndef _HEXAGON_CIRC_BREV_INTRINSICS_H_ */
-
-#ifdef __NOT_DEFINED__
-/*** comment block template  ***/
-/* ==========================================================================
-   Assembly Syntax:       Return=instruction()
-   C Intrinsic Prototype: ReturnType Intrinsic(ParamType Rs, ParamType Rt)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
-   ========================================================================== */
-#endif /***  __NOT_DEFINED__  ***/