@nativescript/ios 9.0.0-esm.2 → 9.0.0-napi-v8.0

package/framework/internal/metadata-generator-arm64/bin/lib/clang/17/include/raointintrin.h

@@ -1,203 +0,0 @@
-/*===----------------------- raointintrin.h - RAOINT ------------------------===
- *
- * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
- * See https://llvm.org/LICENSE.txt for license information.
- * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
- *
- *===-----------------------------------------------------------------------===
- */
-
-#ifndef __X86GPRINTRIN_H
-#error "Never use <raointintrin.h> directly; include <x86gprintrin.h> instead."
-#endif // __X86GPRINTRIN_H
-
-#ifndef __RAOINTINTRIN_H
-#define __RAOINTINTRIN_H
-
-#define __DEFAULT_FN_ATTRS                                                     \
-  __attribute__((__always_inline__, __nodebug__, __target__("raoint")))
-
-/// Atomically add a 32-bit value at memory operand \a __A and a 32-bit \a __B,
-///    and store the result to the same memory location.
-///
-///    This intrinsic should be used for contention or weak ordering. It may
-///    result in bad performance for hot data used by single thread only.
-///
-/// \headerfile <x86intrin.h>
-///
-/// This intrinsic corresponds to the \c AADD instruction.
-///
-/// \param __A
-///    A pointer to a 32-bit memory location.
-/// \param __B
-///    A 32-bit integer value.
-///
-/// \code{.operation}
-/// MEM[__A+31:__A] := MEM[__A+31:__A] + __B[31:0]
-/// \endcode
-static __inline__ void __DEFAULT_FN_ATTRS _aadd_i32(int *__A, int __B) {
-  __builtin_ia32_aadd32((int *)__A, __B);
-}
-
-/// Atomically and a 32-bit value at memory operand \a __A and a 32-bit \a __B,
-///    and store the result to the same memory location.
-///
-///    This intrinsic should be used for contention or weak ordering. It may
-///    result in bad performance for hot data used by single thread only.
-///
-/// \headerfile <x86intrin.h>
-///
-/// This intrinsic corresponds to the \c AAND instruction.
-///
-/// \param __A
-///    A pointer to a 32-bit memory location.
-/// \param __B
-///    A 32-bit integer value.
-///
-/// \code{.operation}
-/// MEM[__A+31:__A] := MEM[__A+31:__A] AND __B[31:0]
-/// \endcode
-static __inline__ void __DEFAULT_FN_ATTRS _aand_i32(int *__A, int __B) {
-  __builtin_ia32_aand32((int *)__A, __B);
-}
-
-/// Atomically or a 32-bit value at memory operand \a __A and a 32-bit \a __B,
-///    and store the result to the same memory location.
-///
-///    This intrinsic should be used for contention or weak ordering. It may
-///    result in bad performance for hot data used by single thread only.
-///
-/// \headerfile <x86intrin.h>
-///
-/// This intrinsic corresponds to the \c AOR instruction.
-///
-/// \param __A
-///    A pointer to a 32-bit memory location.
-/// \param __B
-///    A 32-bit integer value.
-///
-/// \code{.operation}
-/// MEM[__A+31:__A] := MEM[__A+31:__A] OR __B[31:0]
-/// \endcode
-static __inline__ void __DEFAULT_FN_ATTRS _aor_i32(int *__A, int __B) {
-  __builtin_ia32_aor32((int *)__A, __B);
-}
-
-/// Atomically xor a 32-bit value at memory operand \a __A and a 32-bit \a __B,
-///    and store the result to the same memory location.
-///
-///    This intrinsic should be used for contention or weak ordering. It may
-///    result in bad performance for hot data used by single thread only.
-///
-/// \headerfile <x86intrin.h>
-///
-/// This intrinsic corresponds to the \c AXOR instruction.
-///
-/// \param __A
-///    A pointer to a 32-bit memory location.
-/// \param __B
-///    A 32-bit integer value.
-///
-/// \code{.operation}
-/// MEM[__A+31:__A] := MEM[__A+31:__A] XOR __B[31:0]
-/// \endcode
-static __inline__ void __DEFAULT_FN_ATTRS _axor_i32(int *__A, int __B) {
-  __builtin_ia32_axor32((int *)__A, __B);
-}
-
-#ifdef __x86_64__
-/// Atomically add a 64-bit value at memory operand \a __A and a 64-bit \a __B,
-///    and store the result to the same memory location.
-///
-///    This intrinsic should be used for contention or weak ordering. It may
-///    result in bad performance for hot data used by single thread only.
-///
-/// \headerfile <x86intrin.h>
-///
-/// This intrinsic corresponds to the \c AADD instruction.
-///
-/// \param __A
-///    A pointer to a 64-bit memory location.
-/// \param __B
-///    A 64-bit integer value.
-///
-/// \code{.operation}
-/// MEM[__A+63:__A] := MEM[__A+63:__A] + __B[63:0]
-/// \endcode
-static __inline__ void __DEFAULT_FN_ATTRS _aadd_i64(long long *__A,
-                                                    long long __B) {
-  __builtin_ia32_aadd64((long long *)__A, __B);
-}
-
-/// Atomically and a 64-bit value at memory operand \a __A and a 64-bit \a __B,
-///    and store the result to the same memory location.
-///
-///    This intrinsic should be used for contention or weak ordering. It may
-///    result in bad performance for hot data used by single thread only.
-///
-/// \headerfile <x86intrin.h>
-///
-/// This intrinsic corresponds to the \c AAND instruction.
-///
-/// \param __A
-///    A pointer to a 64-bit memory location.
-/// \param __B
-///    A 64-bit integer value.
-///
-/// \code{.operation}
-/// MEM[__A+63:__A] := MEM[__A+63:__A] AND __B[63:0]
-/// \endcode
-static __inline__ void __DEFAULT_FN_ATTRS _aand_i64(long long *__A,
-                                                    long long __B) {
-  __builtin_ia32_aand64((long long *)__A, __B);
-}
-
-/// Atomically or a 64-bit value at memory operand \a __A and a 64-bit \a __B,
-///    and store the result to the same memory location.
-///
-///    This intrinsic should be used for contention or weak ordering. It may
-///    result in bad performance for hot data used by single thread only.
-///
-/// \headerfile <x86intrin.h>
-///
-/// This intrinsic corresponds to the \c AOR instruction.
-///
-/// \param __A
-///    A pointer to a 64-bit memory location.
-/// \param __B
-///    A 64-bit integer value.
-///
-/// \code{.operation}
-/// MEM[__A+63:__A] := MEM[__A+63:__A] OR __B[63:0]
-/// \endcode
-static __inline__ void __DEFAULT_FN_ATTRS _aor_i64(long long *__A,
-                                                   long long __B) {
-  __builtin_ia32_aor64((long long *)__A, __B);
-}
-
-/// Atomically xor a 64-bit value at memory operand \a __A and a 64-bit \a __B,
-///    and store the result to the same memory location.
-///
-///    This intrinsic should be used for contention or weak ordering. It may
-///    result in bad performance for hot data used by single thread only.
-///
-/// \headerfile <x86intrin.h>
-///
-/// This intrinsic corresponds to the \c AXOR instruction.
-///
-/// \param __A
-///    A pointer to a 64-bit memory location.
-/// \param __B
-///    A 64-bit integer value.
-///
-/// \code{.operation}
-/// MEM[__A+63:__A] := MEM[__A+63:__A] XOR __B[63:0]
-/// \endcode
-static __inline__ void __DEFAULT_FN_ATTRS _axor_i64(long long *__A,
-                                                    long long __B) {
-  __builtin_ia32_axor64((long long *)__A, __B);
-}
-#endif // __x86_64__
-
-#undef __DEFAULT_FN_ATTRS
-#endif // __RAOINTINTRIN_H

package/framework/internal/metadata-generator-arm64/bin/lib/clang/17/include/rdpruintrin.h

@@ -1,57 +0,0 @@
-/*===---- rdpruintrin.h - RDPRU intrinsics ---------------------------------===
- *
- * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
- * See https://llvm.org/LICENSE.txt for license information.
- * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
- *
- *===-----------------------------------------------------------------------===
- */
-
-#if !defined __X86INTRIN_H
-#error "Never use <rdpruintrin.h> directly; include <x86intrin.h> instead."
-#endif
-
-#ifndef __RDPRUINTRIN_H
-#define __RDPRUINTRIN_H
-
-/* Define the default attributes for the functions in this file. */
-#define __DEFAULT_FN_ATTRS \
-  __attribute__((__always_inline__, __nodebug__,  __target__("rdpru")))
-
-
-/// Reads the content of a processor register.
-///
-/// \headerfile <x86intrin.h>
-///
-/// This intrinsic corresponds to the <c> RDPRU </c> instruction.
-///
-/// \param reg_id
-///    A processor register identifier.
-static __inline__ unsigned long long __DEFAULT_FN_ATTRS
-__rdpru (int reg_id)
-{
-  return __builtin_ia32_rdpru(reg_id);
-}
-
-#define __RDPRU_MPERF 0
-#define __RDPRU_APERF 1
-
-/// Reads the content of processor register MPERF.
-///
-/// \headerfile <x86intrin.h>
-///
-/// This intrinsic generates instruction <c> RDPRU </c> to read the value of
-/// register MPERF.
-#define __mperf() __builtin_ia32_rdpru(__RDPRU_MPERF)
-
-/// Reads the content of processor register APERF.
-///
-/// \headerfile <x86intrin.h>
-///
-/// This intrinsic generates instruction <c> RDPRU </c> to read the value of
-/// register APERF.
-#define __aperf() __builtin_ia32_rdpru(__RDPRU_APERF)
-
-#undef __DEFAULT_FN_ATTRS
-
-#endif /* __RDPRUINTRIN_H */

package/framework/internal/metadata-generator-arm64/bin/lib/clang/17/include/rdseedintrin.h

@@ -1,105 +0,0 @@
-/*===---- rdseedintrin.h - RDSEED intrinsics -------------------------------===
- *
- * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
- * See https://llvm.org/LICENSE.txt for license information.
- * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
- *
- *===-----------------------------------------------------------------------===
- */
-
-#ifndef __IMMINTRIN_H
-#error "Never use <rdseedintrin.h> directly; include <immintrin.h> instead."
-#endif
-
-#ifndef __RDSEEDINTRIN_H
-#define __RDSEEDINTRIN_H
-
-/* Define the default attributes for the functions in this file. */
-#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("rdseed")))
-
-/// Stores a hardware-generated 16-bit random value in the memory at \a __p.
-///
-///    The random number generator complies with NIST SP800-90B and SP800-90C.
-///
-/// \code{.operation}
-/// IF HW_NRND_GEN.ready == 1
-///   Store16(__p, HW_NRND_GEN.data)
-///   result := 1
-/// ELSE
-///   Store16(__p, 0)
-///   result := 0
-/// END
-/// \endcode
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the \c RDSEED instruction.
-///
-/// \param __p
-///    Pointer to memory for storing the 16-bit random number.
-/// \returns 1 if a random number was generated, 0 if not.
-static __inline__ int __DEFAULT_FN_ATTRS
-_rdseed16_step(unsigned short *__p)
-{
-  return (int) __builtin_ia32_rdseed16_step(__p);
-}
-
-/// Stores a hardware-generated 32-bit random value in the memory at \a __p.
-///
-///    The random number generator complies with NIST SP800-90B and SP800-90C.
-///
-/// \code{.operation}
-/// IF HW_NRND_GEN.ready == 1
-///   Store32(__p, HW_NRND_GEN.data)
-///   result := 1
-/// ELSE
-///   Store32(__p, 0)
-///   result := 0
-/// END
-/// \endcode
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the \c RDSEED instruction.
-///
-/// \param __p
-///    Pointer to memory for storing the 32-bit random number.
-/// \returns 1 if a random number was generated, 0 if not.
-static __inline__ int __DEFAULT_FN_ATTRS
-_rdseed32_step(unsigned int *__p)
-{
-  return (int) __builtin_ia32_rdseed32_step(__p);
-}
-
-#ifdef __x86_64__
-/// Stores a hardware-generated 64-bit random value in the memory at \a __p.
-///
-///    The random number generator complies with NIST SP800-90B and SP800-90C.
-///
-/// \code{.operation}
-/// IF HW_NRND_GEN.ready == 1
-///   Store64(__p, HW_NRND_GEN.data)
-///   result := 1
-/// ELSE
-///   Store64(__p, 0)
-///   result := 0
-/// END
-/// \endcode
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the \c RDSEED instruction.
-///
-/// \param __p
-///    Pointer to memory for storing the 64-bit random number.
-/// \returns 1 if a random number was generated, 0 if not.
-static __inline__ int __DEFAULT_FN_ATTRS
-_rdseed64_step(unsigned long long *__p)
-{
-  return (int) __builtin_ia32_rdseed64_step(__p);
-}
-#endif
-
-#undef __DEFAULT_FN_ATTRS
-
-#endif /* __RDSEEDINTRIN_H */

package/framework/internal/metadata-generator-arm64/bin/lib/clang/17/include/riscv_ntlh.h

@@ -1,28 +0,0 @@
-/*===---- riscv_ntlh.h - RISC-V NTLH intrinsics ----------------------------===
- *
- * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
- * See https://llvm.org/LICENSE.txt for license information.
- * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
- *
- *===-----------------------------------------------------------------------===
- */
-
-#ifndef __RISCV_NTLH_H
-#define __RISCV_NTLH_H
-
-#ifndef __riscv_zihintntl
-#error "NTLH intrinsics require the NTLH extension."
-#endif
-
-enum {
-  __RISCV_NTLH_INNERMOST_PRIVATE = 2,
-  __RISCV_NTLH_ALL_PRIVATE,
-  __RISCV_NTLH_INNERMOST_SHARED,
-  __RISCV_NTLH_ALL
-};
-
-#define __riscv_ntl_load(PTR, DOMAIN) __builtin_riscv_ntl_load((PTR), (DOMAIN))
-#define __riscv_ntl_store(PTR, VAL, DOMAIN)                                    \
-  __builtin_riscv_ntl_store((PTR), (VAL), (DOMAIN))
-
-#endif