@nativescript/ios 8.8.7-sap.0 → 8.9.0-napi-v8.0

package/framework/internal/metadata-generator-arm64/bin/lib/clang/17/include/sha512intrin.h

@@ -1,200 +0,0 @@
-/*===--------------- sha512intrin.h - SHA512 intrinsics -----------------===
- *
- * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
- * See https://llvm.org/LICENSE.txt for license information.
- * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
- *
- *===-----------------------------------------------------------------------===
- */
-
-#ifndef __IMMINTRIN_H
-#error "Never use <sha512intrin.h> directly; include <immintrin.h> instead."
-#endif // __IMMINTRIN_H
-
-#ifndef __SHA512INTRIN_H
-#define __SHA512INTRIN_H
-
-#define __DEFAULT_FN_ATTRS256                                                  \
-  __attribute__((__always_inline__, __nodebug__, __target__("sha512"),         \
-                 __min_vector_width__(256)))
-
-/// This intrinisc is one of the two SHA512 message scheduling instructions.
-///    The intrinsic performs an intermediate calculation for the next four
-///    SHA512 message qwords. The calculated results are stored in \a dst.
-///
-/// \headerfile <immintrin.h>
-///
-/// \code
-/// __m256i _mm256_sha512msg1_epi64(__m256i __A, __m128i __B)
-/// \endcode
-///
-/// This intrinsic corresponds to the \c VSHA512MSG1 instruction.
-///
-/// \param __A
-///    A 256-bit vector of [4 x long long].
-/// \param __B
-///    A 128-bit vector of [2 x long long].
-/// \returns
-///    A 256-bit vector of [4 x long long].
-///
-/// \code{.operation}
-/// DEFINE ROR64(qword, n) {
-/// 	count := n % 64
-/// 	dest := (qword >> count) | (qword << (64 - count))
-/// 	RETURN dest
-/// }
-/// DEFINE SHR64(qword, n) {
-/// 	RETURN qword >> n
-/// }
-/// DEFINE s0(qword):
-/// 	RETURN ROR64(qword,1) ^ ROR64(qword, 8) ^ SHR64(qword, 7)
-/// }
-/// W[4] := __B.qword[0]
-/// W[3] := __A.qword[3]
-/// W[2] := __A.qword[2]
-/// W[1] := __A.qword[1]
-/// W[0] := __A.qword[0]
-/// dst.qword[3] := W[3] + s0(W[4])
-/// dst.qword[2] := W[2] + s0(W[3])
-/// dst.qword[1] := W[1] + s0(W[2])
-/// dst.qword[0] := W[0] + s0(W[1])
-/// dst[MAX:256] := 0
-/// \endcode
-static __inline__ __m256i __DEFAULT_FN_ATTRS256
-_mm256_sha512msg1_epi64(__m256i __A, __m128i __B) {
-  return (__m256i)__builtin_ia32_vsha512msg1((__v4du)__A, (__v2du)__B);
-}
-
-/// This intrinisc is one of the two SHA512 message scheduling instructions.
-///    The intrinsic performs the final calculation for the next four SHA512
-///    message qwords. The calculated results are stored in \a dst.
-///
-/// \headerfile <immintrin.h>
-///
-/// \code
-/// __m256i _mm256_sha512msg2_epi64(__m256i __A, __m256i __B)
-/// \endcode
-///
-/// This intrinsic corresponds to the \c VSHA512MSG2 instruction.
-///
-/// \param __A
-///    A 256-bit vector of [4 x long long].
-/// \param __B
-///    A 256-bit vector of [4 x long long].
-/// \returns
-///    A 256-bit vector of [4 x long long].
-///
-/// \code{.operation}
-/// DEFINE ROR64(qword, n) {
-/// 	count := n % 64
-/// 	dest := (qword >> count) | (qword << (64 - count))
-/// 	RETURN dest
-/// }
-/// DEFINE SHR64(qword, n) {
-/// 	RETURN qword >> n
-/// }
-/// DEFINE s1(qword) {
-/// 	RETURN ROR64(qword,19) ^ ROR64(qword, 61) ^ SHR64(qword, 6)
-/// }
-/// W[14] := __B.qword[2]
-/// W[15] := __B.qword[3]
-/// W[16] := __A.qword[0] + s1(W[14])
-/// W[17] := __A.qword[1] + s1(W[15])
-/// W[18] := __A.qword[2] + s1(W[16])
-/// W[19] := __A.qword[3] + s1(W[17])
-/// dst.qword[3] := W[19]
-/// dst.qword[2] := W[18]
-/// dst.qword[1] := W[17]
-/// dst.qword[0] := W[16]
-/// dst[MAX:256] := 0
-/// \endcode
-static __inline__ __m256i __DEFAULT_FN_ATTRS256
-_mm256_sha512msg2_epi64(__m256i __A, __m256i __B) {
-  return (__m256i)__builtin_ia32_vsha512msg2((__v4du)__A, (__v4du)__B);
-}
-
-/// This intrinisc performs two rounds of SHA512 operation using initial SHA512
-///    state (C,D,G,H) from \a __A, an initial SHA512 state (A,B,E,F) from
-///    \a __A, and a pre-computed sum of the next two round message qwords and
-///    the corresponding round constants from \a __C (only the two lower qwords
-///    of the third operand). The updated SHA512 state (A,B,E,F) is written to
-///    \a __A, and \a __A can be used as the updated state (C,D,G,H) in later
-///    rounds.
-///
-/// \headerfile <immintrin.h>
-///
-/// \code
-/// __m256i _mm256_sha512rnds2_epi64(__m256i __A, __m256i __B, __m128i __C)
-/// \endcode
-///
-/// This intrinsic corresponds to the \c VSHA512RNDS2 instruction.
-///
-/// \param __A
-///    A 256-bit vector of [4 x long long].
-/// \param __B
-///    A 256-bit vector of [4 x long long].
-/// \param __C
-///    A 128-bit vector of [2 x long long].
-/// \returns
-///    A 256-bit vector of [4 x long long].
-///
-/// \code{.operation}
-/// DEFINE ROR64(qword, n) {
-/// 	count := n % 64
-/// 	dest := (qword >> count) | (qword << (64 - count))
-/// 	RETURN dest
-/// }
-/// DEFINE SHR64(qword, n) {
-/// 	RETURN qword >> n
-/// }
-/// DEFINE cap_sigma0(qword) {
-/// 	RETURN ROR64(qword,28) ^ ROR64(qword, 34) ^ ROR64(qword, 39)
-/// }
-/// DEFINE cap_sigma1(qword) {
-/// 	RETURN ROR64(qword,14) ^ ROR64(qword, 18) ^ ROR64(qword, 41)
-/// }
-/// DEFINE MAJ(a,b,c) {
-/// 	RETURN (a & b) ^ (a & c) ^ (b & c)
-/// }
-/// DEFINE CH(e,f,g) {
-/// 	RETURN (e & f) ^ (g & ~e)
-/// }
-/// A[0] := __B.qword[3]
-/// B[0] := __B.qword[2]
-/// C[0] := __C.qword[3]
-/// D[0] := __C.qword[2]
-/// E[0] := __B.qword[1]
-/// F[0] := __B.qword[0]
-/// G[0] := __C.qword[1]
-/// H[0] := __C.qword[0]
-/// WK[0]:= __A.qword[0]
-/// WK[1]:= __A.qword[1]
-/// FOR i := 0 to 1:
-/// 	A[i+1] := CH(E[i], F[i], G[i]) +
-/// 	cap_sigma1(E[i]) + WK[i] + H[i] +
-/// 	MAJ(A[i], B[i], C[i]) +
-/// 	cap_sigma0(A[i])
-/// 	B[i+1] := A[i]
-/// 	C[i+1] := B[i]
-/// 	D[i+1] := C[i]
-/// 	E[i+1] := CH(E[i], F[i], G[i]) +
-/// 	cap_sigma1(E[i]) + WK[i] + H[i] + D[i]
-/// 	F[i+1] := E[i]
-/// 	G[i+1] := F[i]
-/// 	H[i+1] := G[i]
-/// ENDFOR
-/// dst.qword[3] := A[2]
-/// dst.qword[2] := B[2]
-/// dst.qword[1] := E[2]
-/// dst.qword[0] := F[2]
-/// dst[MAX:256] := 0
-/// \endcode
-static __inline__ __m256i __DEFAULT_FN_ATTRS256
-_mm256_sha512rnds2_epi64(__m256i __A, __m256i __B, __m128i __C) {
-  return (__m256i)__builtin_ia32_vsha512rnds2((__v4du)__A, (__v4du)__B,
-                                              (__v2du)__C);
-}
-
-#undef __DEFAULT_FN_ATTRS256
-
-#endif // __SHA512INTRIN_H

package/framework/internal/metadata-generator-arm64/bin/lib/clang/17/include/shaintrin.h

@@ -1,189 +0,0 @@
-/*===---- shaintrin.h - SHA intrinsics -------------------------------------===
- *
- * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
- * See https://llvm.org/LICENSE.txt for license information.
- * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
- *
- *===-----------------------------------------------------------------------===
- */
-
-#ifndef __IMMINTRIN_H
-#error "Never use <shaintrin.h> directly; include <immintrin.h> instead."
-#endif
-
-#ifndef __SHAINTRIN_H
-#define __SHAINTRIN_H
-
-/* Define the default attributes for the functions in this file. */
-#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("sha"), __min_vector_width__(128)))
-
-/// Performs four iterations of the inner loop of the SHA-1 message digest
-///    algorithm using the starting SHA-1 state (A, B, C, D) from the 128-bit
-///    vector of [4 x i32] in \a V1 and the next four 32-bit elements of the
-///    message from the 128-bit vector of [4 x i32] in \a V2. Note that the
-///    SHA-1 state variable E must have already been added to \a V2
-///    (\c _mm_sha1nexte_epu32() can perform this step). Returns the updated
-///    SHA-1 state (A, B, C, D) as a 128-bit vector of [4 x i32].
-///
-///    The SHA-1 algorithm has an inner loop of 80 iterations, twenty each
-///    with a different combining function and rounding constant. This
-///    intrinsic performs four iterations using a combining function and
-///    rounding constant selected by \a M[1:0].
-///
-/// \headerfile <immintrin.h>
-///
-/// \code
-/// __m128i _mm_sha1rnds4_epu32(__m128i V1, __m128i V2, const int M);
-/// \endcode
-///
-/// This intrinsic corresponds to the \c SHA1RNDS4 instruction.
-///
-/// \param V1
-///    A 128-bit vector of [4 x i32] containing the initial SHA-1 state.
-/// \param V2
-///    A 128-bit vector of [4 x i32] containing the next four elements of
-///    the message, plus SHA-1 state variable E.
-/// \param M
-///    An immediate value where bits [1:0] select among four possible
-///    combining functions and rounding constants (not specified here).
-/// \returns A 128-bit vector of [4 x i32] containing the updated SHA-1 state.
-#define _mm_sha1rnds4_epu32(V1, V2, M) \
-  __builtin_ia32_sha1rnds4((__v4si)(__m128i)(V1), (__v4si)(__m128i)(V2), (M))
-
-/// Calculates the SHA-1 state variable E from the SHA-1 state variables in
-///    the 128-bit vector of [4 x i32] in \a __X, adds that to the next set of
-///    four message elements in the 128-bit vector of [4 x i32] in \a __Y, and
-///    returns the result.
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the \c SHA1NEXTE instruction.
-///
-/// \param __X
-///    A 128-bit vector of [4 x i32] containing the current SHA-1 state.
-/// \param __Y
-///    A 128-bit vector of [4 x i32] containing the next four elements of the
-///    message.
-/// \returns A 128-bit vector of [4 x i32] containing the updated SHA-1
-///    values.
-static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_sha1nexte_epu32(__m128i __X, __m128i __Y)
-{
-  return (__m128i)__builtin_ia32_sha1nexte((__v4si)__X, (__v4si)__Y);
-}
-
-/// Performs an intermediate calculation for deriving the next four SHA-1
-///    message elements using previous message elements from the 128-bit
-///    vectors of [4 x i32] in \a __X and \a __Y, and returns the result.
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the \c SHA1MSG1 instruction.
-///
-/// \param __X
-///    A 128-bit vector of [4 x i32] containing previous message elements.
-/// \param __Y
-///    A 128-bit vector of [4 x i32] containing previous message elements.
-/// \returns A 128-bit vector of [4 x i32] containing the derived SHA-1
-///    elements.
-static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_sha1msg1_epu32(__m128i __X, __m128i __Y)
-{
-  return (__m128i)__builtin_ia32_sha1msg1((__v4si)__X, (__v4si)__Y);
-}
-
-/// Performs the final calculation for deriving the next four SHA-1 message
-///    elements using previous message elements from the 128-bit vectors of
-///    [4 x i32] in \a __X and \a __Y, and returns the result.
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the \c SHA1MSG2 instruction.
-///
-/// \param __X
-///    A 128-bit vector of [4 x i32] containing an intermediate result.
-/// \param __Y
-///    A 128-bit vector of [4 x i32] containing previous message values.
-/// \returns A 128-bit vector of [4 x i32] containing the updated SHA-1
-///    values.
-static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_sha1msg2_epu32(__m128i __X, __m128i __Y)
-{
-  return (__m128i)__builtin_ia32_sha1msg2((__v4si)__X, (__v4si)__Y);
-}
-
-/// Performs two rounds of SHA-256 operation using the following inputs: a
-///    starting SHA-256 state (C, D, G, H) from the 128-bit vector of
-///    [4 x i32] in \a __X; a starting SHA-256 state (A, B, E, F) from the
-///    128-bit vector of [4 x i32] in \a __Y; and a pre-computed sum of the
-///    next two message elements (unsigned 32-bit integers) and corresponding
-///    rounding constants from the 128-bit vector of [4 x i32] in \a __Z.
-///    Returns the updated SHA-256 state (A, B, E, F) as a 128-bit vector of
-///    [4 x i32].
-///
-///    The SHA-256 algorithm has a core loop of 64 iterations. This intrinsic
-///    performs two of those iterations.
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the \c SHA256RNDS2 instruction.
-///
-/// \param __X
-///    A 128-bit vector of [4 x i32] containing part of the initial SHA-256
-///    state.
-/// \param __Y
-///    A 128-bit vector of [4 x i32] containing part of the initial SHA-256
-///    state.
-/// \param __Z
-///    A 128-bit vector of [4 x i32] containing additional input to the
-///    SHA-256 operation.
-/// \returns A 128-bit vector of [4 x i32] containing the updated SHA-1 state.
-static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_sha256rnds2_epu32(__m128i __X, __m128i __Y, __m128i __Z)
-{
-  return (__m128i)__builtin_ia32_sha256rnds2((__v4si)__X, (__v4si)__Y, (__v4si)__Z);
-}
-
-/// Performs an intermediate calculation for deriving the next four SHA-256
-///    message elements using previous message elements from the 128-bit
-///    vectors of [4 x i32] in \a __X and \a __Y, and returns the result.
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the \c SHA256MSG1 instruction.
-///
-/// \param __X
-///    A 128-bit vector of [4 x i32] containing previous message elements.
-/// \param __Y
-///    A 128-bit vector of [4 x i32] containing previous message elements.
-/// \returns A 128-bit vector of [4 x i32] containing the updated SHA-256
-///    values.
-static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_sha256msg1_epu32(__m128i __X, __m128i __Y)
-{
-  return (__m128i)__builtin_ia32_sha256msg1((__v4si)__X, (__v4si)__Y);
-}
-
-/// Performs the final calculation for deriving the next four SHA-256 message
-///    elements using previous message elements from the 128-bit vectors of
-///    [4 x i32] in \a __X and \a __Y, and returns the result.
-///
-/// \headerfile <immintrin.h>
-///
-/// This intrinsic corresponds to the \c SHA256MSG2 instruction.
-///
-/// \param __X
-///    A 128-bit vector of [4 x i32] containing an intermediate result.
-/// \param __Y
-///    A 128-bit vector of [4 x i32] containing previous message values.
-/// \returns A 128-bit vector of [4 x i32] containing the updated SHA-256
-///    values.
-static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_sha256msg2_epu32(__m128i __X, __m128i __Y)
-{
-  return (__m128i)__builtin_ia32_sha256msg2((__v4si)__X, (__v4si)__Y);
-}
-
-#undef __DEFAULT_FN_ATTRS
-
-#endif /* __SHAINTRIN_H */

package/framework/internal/metadata-generator-arm64/bin/lib/clang/17/include/sifive_vector.h

@@ -1,16 +0,0 @@
-//===----- sifive_vector.h - SiFive Vector definitions --------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef _SIFIVE_VECTOR_H_
-#define _SIFIVE_VECTOR_H_
-
-#include "riscv_vector.h"
-
-#pragma clang riscv intrinsic sifive_vector
-
-#endif //_SIFIVE_VECTOR_H_

package/framework/internal/metadata-generator-arm64/bin/lib/clang/17/include/sm3intrin.h

@@ -1,238 +0,0 @@
-/*===-------------------- sm3intrin.h - SM3 intrinsics ---------------------===
- *
- * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
- * See https://llvm.org/LICENSE.txt for license information.
- * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
- *
- *===-----------------------------------------------------------------------===
- */
-
-#ifndef __IMMINTRIN_H
-#error "Never use <sm3intrin.h> directly; include <immintrin.h> instead."
-#endif // __IMMINTRIN_H
-
-#ifndef __SM3INTRIN_H
-#define __SM3INTRIN_H
-
-#define __DEFAULT_FN_ATTRS128                                                  \
-  __attribute__((__always_inline__, __nodebug__, __target__("sm3"),            \
-                 __min_vector_width__(128)))
-
-/// This intrinisc is one of the two SM3 message scheduling intrinsics. The
-///    intrinsic performs an initial calculation for the next four SM3 message
-///    words. The calculated results are stored in \a dst.
-///
-/// \headerfile <immintrin.h>
-///
-/// \code
-/// __m128i _mm_sm3msg1_epi32(__m128i __A, __m128i __B, __m128i __C)
-/// \endcode
-///
-/// This intrinsic corresponds to the \c VSM3MSG1 instruction.
-///
-/// \param __A
-///    A 128-bit vector of [4 x int].
-/// \param __B
-///    A 128-bit vector of [4 x int].
-/// \param __C
-///    A 128-bit vector of [4 x int].
-/// \returns
-///    A 128-bit vector of [4 x int].
-///
-/// \code{.operation}
-/// DEFINE ROL32(dword, n) {
-/// 	count := n % 32
-/// 	dest := (dword << count) | (dword >> (32 - count))
-/// 	RETURN dest
-/// }
-/// DEFINE P1(x) {
-/// 	RETURN x ^ ROL32(x, 15) ^ ROL32(x, 23)
-/// }
-/// W[0] := __C.dword[0]
-/// W[1] := __C.dword[1]
-/// W[2] := __C.dword[2]
-/// W[3] := __C.dword[3]
-/// W[7] := __A.dword[0]
-/// W[8] := __A.dword[1]
-/// W[9] := __A.dword[2]
-/// W[10] := __A.dword[3]
-/// W[13] := __B.dword[0]
-/// W[14] := __B.dword[1]
-/// W[15] := __B.dword[2]
-/// TMP0 := W[7] ^ W[0] ^ ROL32(W[13], 15)
-/// TMP1 := W[8] ^ W[1] ^ ROL32(W[14], 15)
-/// TMP2 := W[9] ^ W[2] ^ ROL32(W[15], 15)
-/// TMP3 := W[10] ^ W[3]
-/// dst.dword[0] := P1(TMP0)
-/// dst.dword[1] := P1(TMP1)
-/// dst.dword[2] := P1(TMP2)
-/// dst.dword[3] := P1(TMP3)
-/// dst[MAX:128] := 0
-/// \endcode
-static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_sm3msg1_epi32(__m128i __A,
-                                                                  __m128i __B,
-                                                                  __m128i __C) {
-  return (__m128i)__builtin_ia32_vsm3msg1((__v4su)__A, (__v4su)__B,
-                                          (__v4su)__C);
-}
-
-/// This intrinisc is one of the two SM3 message scheduling intrinsics. The
-///    intrinsic performs the final calculation for the next four SM3 message
-///    words. The calculated results are stored in \a dst.
-///
-/// \headerfile <immintrin.h>
-///
-/// \code
-/// __m128i _mm_sm3msg2_epi32(__m128i __A, __m128i __B, __m128i __C)
-/// \endcode
-///
-/// This intrinsic corresponds to the \c VSM3MSG2 instruction.
-///
-/// \param __A
-///    A 128-bit vector of [4 x int].
-/// \param __B
-///    A 128-bit vector of [4 x int].
-/// \param __C
-///    A 128-bit vector of [4 x int].
-/// \returns
-///    A 128-bit vector of [4 x int].
-///
-/// \code{.operation}
-/// DEFINE ROL32(dword, n) {
-/// 	count := n % 32
-/// 	dest := (dword << count) | (dword >> (32-count))
-/// 	RETURN dest
-/// }
-/// WTMP[0] := __A.dword[0]
-/// WTMP[1] := __A.dword[1]
-/// WTMP[2] := __A.dword[2]
-/// WTMP[3] := __A.dword[3]
-/// W[3] := __B.dword[0]
-/// W[4] := __B.dword[1]
-/// W[5] := __B.dword[2]
-/// W[6] := __B.dword[3]
-/// W[10] := __C.dword[0]
-/// W[11] := __C.dword[1]
-/// W[12] := __C.dword[2]
-/// W[13] := __C.dword[3]
-/// W[16] := ROL32(W[3], 7) ^ W[10] ^ WTMP[0]
-/// W[17] := ROL32(W[4], 7) ^ W[11] ^ WTMP[1]
-/// W[18] := ROL32(W[5], 7) ^ W[12] ^ WTMP[2]
-/// W[19] := ROL32(W[6], 7) ^ W[13] ^ WTMP[3]
-/// W[19] := W[19] ^ ROL32(W[16], 6) ^ ROL32(W[16], 15) ^ ROL32(W[16], 30)
-/// dst.dword[0] := W[16]
-/// dst.dword[1] := W[17]
-/// dst.dword[2] := W[18]
-/// dst.dword[3] := W[19]
-/// dst[MAX:128] := 0
-/// \endcode
-static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_sm3msg2_epi32(__m128i __A,
-                                                                  __m128i __B,
-                                                                  __m128i __C) {
-  return (__m128i)__builtin_ia32_vsm3msg2((__v4su)__A, (__v4su)__B,
-                                          (__v4su)__C);
-}
-
-/// This intrinsic performs two rounds of SM3 operation using initial SM3 state
-///    (C, D, G, H) from \a __A, an initial SM3 states (A, B, E, F)
-///    from \a __B and a pre-computed words from the \a __C. \a __A with
-///    initial SM3 state of (C, D, G, H) assumes input of non-rotated left
-///    variables from previous state. The updated SM3 state (A, B, E, F) is
-///    written to \a __A. The \a imm8 should contain the even round number
-///    for the first of the two rounds computed by this instruction. The
-///    computation masks the \a imm8 value by AND’ing it with 0x3E so that only
-///    even round numbers from 0 through 62 are used for this operation. The
-///    calculated results are stored in \a dst.
-///
-/// \headerfile <immintrin.h>
-///
-/// \code
-/// __m128i _mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C, const int
-/// imm8) \endcode
-///
-/// This intrinsic corresponds to the \c VSM3RNDS2 instruction.
-///
-/// \param __A
-///    A 128-bit vector of [4 x int].
-/// \param __B
-///    A 128-bit vector of [4 x int].
-/// \param __C
-///    A 128-bit vector of [4 x int].
-/// \param imm8
-///    A 8-bit constant integer.
-/// \returns
-///    A 128-bit vector of [4 x int].
-///
-/// \code{.operation}
-/// DEFINE ROL32(dword, n) {
-/// 	count := n % 32
-/// 	dest := (dword << count) | (dword >> (32-count))
-/// 	RETURN dest
-/// }
-/// DEFINE P0(dword) {
-/// 	RETURN dword ^ ROL32(dword, 9) ^ ROL32(dword, 17)
-/// }
-/// DEFINE FF(x,y,z, round){
-/// 	IF round < 16
-/// 		RETURN (x ^ y ^ z)
-/// 	ELSE
-/// 		RETURN (x & y) | (x & z) | (y & z)
-/// 	FI
-/// }
-/// DEFINE GG(x, y, z, round){
-///   IF round < 16
-///   	RETURN (x ^ y ^ z)
-///   ELSE
-///   	RETURN (x & y) | (~x & z)
-///   FI
-/// }
-/// A[0] := __B.dword[3]
-/// B[0] := __B.dword[2]
-/// C[0] := __A.dword[3]
-/// D[0] := __A.dword[2]
-/// E[0] := __B.dword[1]
-/// F[0] := __B.dword[0]
-/// G[0] := __A.dword[1]
-/// H[0] := __A.dword[0]
-/// W[0] := __C.dword[0]
-/// W[1] := __C.dword[1]
-/// W[4] := __C.dword[2]
-/// W[5] := __C.dword[3]
-/// C[0] := ROL32(C[0], 9)
-/// D[0] := ROL32(D[0], 9)
-/// G[0] := ROL32(G[0], 19)
-/// H[0] := ROL32(H[0], 19)
-/// ROUND := __D & 0x3E
-/// IF ROUND < 16
-/// 	CONST := 0x79CC4519
-/// ELSE
-/// 	CONST := 0x7A879D8A
-/// FI
-/// CONST := ROL32(CONST,ROUND)
-/// FOR i:= 0 to 1
-/// 	S1 := ROL32((ROL32(A[i], 12) + E[i] + CONST), 7)
-/// 	S2 := S1 ^ ROL32(A[i], 12)
-/// 	T1 := FF(A[i], B[i], C[i], ROUND) + D[i] + S2 + (W[i] ^ W[i+4])
-/// 	T2 := GG(E[i], F[i], G[i], ROUND) + H[i] + S1 + W[i]
-/// 	D[i+1] := C[i]
-/// 	C[i+1] := ROL32(B[i],9)
-/// 	B[i+1] := A[i]
-/// 	A[i+1] := T1
-/// 	H[i+1] := G[i]
-/// 	G[i+1] := ROL32(F[i], 19)
-/// 	F[i+1] := E[i]
-/// 	E[i+1] := P0(T2)
-/// 	CONST := ROL32(CONST, 1)
-/// ENDFOR
-/// dst.dword[3] := A[2]
-/// dst.dword[2] := B[2]
-/// dst.dword[1] := E[2]
-/// dst.dword[0] := F[2]
-/// dst[MAX:128] := 0
-/// \endcode
-#define _mm_sm3rnds2_epi32(A, B, C, D)                                         \
-  (__m128i) __builtin_ia32_vsm3rnds2((__v4su)A, (__v4su)B, (__v4su)C, (int)D)
-
-#undef __DEFAULT_FN_ATTRS128
-
-#endif // __SM3INTRIN_H