@nataliapc/mcp-openmsx 1.1.14 → 1.1.15

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (12) hide show
  1. package/README.md +16 -2
  2. package/dist/server.js +143 -63
  3. package/dist/utils.js +44 -5
  4. package/package.json +4 -2
  5. package/resources/audio/MGSC111.txt +669 -0
  6. package/resources/audio/opl4tech.txt +688 -0
  7. package/resources/audio/toc.json +10 -3
  8. package/resources/processors/toc.json +4 -4
  9. package/resources/processors/z80_detailed_instruction_set.md +80 -68
  10. package/resources/sdcc/sdccman.lyx +81574 -0
  11. package/resources/sdcc/toc.json +77 -0
  12. /package/resources/processors/{Z80_R800_instruction_set.md → z80_r800_instruction_set.md} +0 -0
package/resources/audio/toc.json CHANGED
@@ -13,7 +13,7 @@
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  "description": "Technical documentation for Konami's SCC (Sound Creative Chip) used in MSX cartridges. The SCC provides 5-channel wavetable synthesis with custom waveforms, offering enhanced audio capabilities beyond the standard PSG. Commonly found in Konami game cartridges like Gradius series, providing richer sound effects and music."
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  },
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  {
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- "title": "Konami SCC+ Sound Chip",
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+ "title": "Konami SCCI Sound Chip",
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  "uri": "http://bifi.msxnet.org/msxnet/tech/soundcartridge",
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  "description": "Technical documentation for Konami's enhanced SCC+ (Sound Creative Chip Plus) found in later MSX sound cartridges. Improved version of the original SCC providing enhanced wavetable synthesis capabilities, additional sound channels, and better audio quality. Used in advanced Konami cartridges and dedicated sound cartridges for expanded audio functionality."
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  },
@@ -23,8 +23,15 @@
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  "description": "Complete technical documentation for MSX-MIDI interface covering hardware configuration, MIDI data communication using 8251 IC, baud rate generator with 8253/8254 timer IC, I/O port assignments (0E8H, 0E9H), internal vs external cartridge implementations, and BASIC extensions. Available only for MSX turbo R and later systems with 16K ROM containing MIDI functionality."
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  },
25
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  {
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- "title": "MGSDRV MML 1.1",
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- "uri": "https://mus.msx.click/index.php?title=MGSDRV_MML_11",
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+ "title": "Moonsound Technical Documentation",
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+ "uri": "msxdocs://audio/opl4tech",
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+ "external_url": "https://www.msxarchive.nl/pub/msx/docs/programming/opl4tech.txt",
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+ "description": "Comprehensive technical documentation for the MoonSound MSX cartridge and its Yamaha OPL4 (YMF278B) chip. Covers hardware components, I/O ports, register maps, CPU interface, PCM and FM synthesis, memory access, envelopes, mixing, and status flags. Includes practical notes for MSX programmers, register tables, and usage tips for both Z80 and R800 CPUs. Useful for developers working with advanced MSX audio hardware and music software."
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+ },
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+ {
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+ "title": "MGSDRV MML 1.11",
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+ "uri": "msxdocs://audio/MGSC111",
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+ "external_url": "https://www.gigamix.jp/mgsdrv/MGSC111.TXT",
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  "description": "Complete documentation for MGSC MML compiler version 1.11 by Ain (1992-93) that converts MML (Music Macro Language) text files to MGS formatted play data for MGSDRV. Covers control functions, OPLL modes (FM 9 sound/FM 6+rhythm), machine vendor codes (SONY, Panasonic, SANYO), macro definitions, tone definitions, tempo control, and compilation options including real-time playback and debugging features."
29
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  }
30
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  ]
package/resources/processors/toc.json CHANGED
@@ -3,19 +3,19 @@
3
3
  "description": "Technical Info about the Z80, R800, and others processors, including detailed instruction sets, undocumented instructions, and timing information.",
4
4
  "toc": [
5
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  {
6
- "title": "Z80 Detailed Instruction Set (Z80 Heaven)",
7
- "uri": "msxdocs://processors/Z80_detailed_instruction_set",
6
+ "title": "Z80 Detailed Instruction Set",
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+ "uri": "msxdocs://processors/z80_detailed_instruction_set",
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  "external_url": "http://z80-heaven.wikidot.com/instructions-set",
9
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  "description": "This document is a comprehensive reference for the Z80 processor instruction set, organized alphabetically from ADC to XOR, featuring over 80 different instructions with detailed syntax, allowed operands, flag effects (C, N, S, Z, P/V, H), practical use cases, and clock cycles (T-States) for each variant. Each instruction is documented with specific assembly code examples, describing arithmetic operations (ADD, SUB, ADC, SBC), logical operations (AND, OR, XOR), comparison operations (CP, CPI, CPD), bit manipulation (BIT, SET, RES), flow control (JP, JR, CALL, RET, DJNZ), data transfer (LD, LDD, LDI, PUSH, POP), rotation/shifting (RL, RR, SLA, SRA), and system control (HALT, DI, EI, NOP). Provides precise technical context about registers (A, B, C, D, E, H, L, IX, IY, SP), addressing modes (immediate, direct, indirect, indexed), and the exact semantics of each operation, being especially valuable for generating Z80 assembly code, debugging MSX programs, or explaining processor behavior in retro systems like MSX, Amstrad CPC, or ZX Spectrum."
10
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  },
11
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  {
12
12
  "title": "Z80 / R800 Instruction Set",
13
- "uri": "msxdocs://processors/Z80_R800_instruction_set",
13
+ "uri": "msxdocs://processors/z80_r800_instruction_set",
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  "external_url": "https://map.grauw.nl/resources/z80instr.php",
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  "description": "This comprehensive instruction set reference provides a complete tabular listing of all Z80 processor instructions plus R800-specific extensions (MULUB/MULUW multiplication instructions), including documented and undocumented opcodes with precise timing data for MSX systems. It details instruction timing across four scenarios (Z80, Z80+M1 waits, R800, R800+waits), hexadecimal opcodes, instruction sizes, and MSX-specific timing considerations including M1 wait states, memory access patterns, I/O timing, and R800 internal/external memory performance characteristics. Essential for MSX assembly programming, emulator development, performance optimization, cycle-accurate timing calculations, and understanding the behavioral differences between Z80 and R800 processors in MSX environments."
16
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  },
17
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  {
18
- "title": "The Undocumented Z80 Documented (Maintained by Jan Wilmans).",
18
+ "title": "The Undocumented Z80 Documented",
19
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  "uri": "msxdocs://processors/z80-undocumented",
20
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  "external_url": "http://bifi.msxnet.org/msxnet/tech/",
21
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  "description": "Provides a comprehensive technical reference for Z80 microprocessor instructions, focusing on both officially documented and undocumented instruction sets. It serves as an authoritative guide for Z80 assembly programming, particularly relevant for MSX computer development."
package/resources/processors/z80_detailed_instruction_set.md CHANGED
@@ -2,7 +2,20 @@
2
2
 
3
3
  Source: [Z80 Heaven](http://z80-heaven.wikidot.com/instructions-set)
4
4
 
5
+ Instructions index:
6
+
7
+ |||||||||||
8
+ |:-:|:-:|:-:|:-:|:-:|:-:|:-:|:-:|:-:|:-:|
9
+ | [ADC](#adc) | [ADD](#add) | [AND](#and) | [BIT](#bit) | [CALL](#call) | [CCF](#ccf) | [CP](#cp) | [CPD](#cpd) | [CPDR](#cpdr) | [CPI](#cpi) |
10
+ | [CPIR](#cpir) | [CPL](#cpl) | [DAA](#daa) | [DEC](#dec) | [DI](#di) | [DJNZ](#djnz) | [EI](#ei) | [EX](#ex) | [EXX](#exx) | [HALT](#halt) |
11
+ | [IM](#im) | [IN](#in) | [INC](#inc) | [IND](#ind) | [INDR](#indr) | [INI](#ini) | [INIR](#inir) | [JP](#jp) | [JR](#jr) | [LD](#ld) |
12
+ | [LDD](#ldd) | [LDDR](#lddr) | [LDI](#ldi) | [LDIR](#ldir) | [NEG](#neg) | [NOP](#nop) | [OR](#or) | [OTDR](#otdr) | [OTIR](#otir) | [OUT](#out) |
13
+ | [OUTD](#outd) | [OUTI](#outi) | [POP](#pop) | [PUSH](#push) | [RES](#res) | [RET](#ret) | [RETI](#reti) | [RETN](#retn) | [RL](#rl) | [RLA](#rla) |
14
+ | [RLC](#rlc) | [RLCA](#rlca) | [RLD](#rld) | [RR](#rr) | [RRA](#rra) | [RRC](#rrc) | [RRCA](#rrca) | [RRD](#rrd) | [RST](#rst) | [SBC](#sbc) |
15
+ | [SCF](#scf) | [SET](#set) | [SLA](#sla) | [SLL/SL1](#sllsl1) | [SRA](#sra) | [SRL](#srl) | [SUB](#sub) | [XOR](#xor) |||
16
+
5
17
  ---
18
+
6
19
  ## ADC
7
20
  The sum of the two operands plus the carry flag (0 or 1) is calculated, and the result is written back into the first operand.
8
21
 
@@ -52,7 +65,7 @@ Multiple precision adding
52
65
  ### See also
53
66
  [ADD](#add), [DAA](#daa), [DEC](#dec), [INC](#inc), [SBC](#sbc), [SUB](#sub)
54
67
 
55
- ---
68
+
56
69
  ## ADD
57
70
  The values of the two operands are added together, and the result is written back to the first one.
58
71
 
@@ -120,7 +133,7 @@ Obviously used to add two numbers together. However, you can add 16-bit numbers
120
133
  ### See Also
121
134
  [ADC](#adc), [DAA](#daa), [DEC](#dec), [INC](#inc), [SBC](#sbc), [SUB](#sub)
122
135
 
123
- ---
136
+
124
137
  ## AND
125
138
  `AND` is an instruction that takes an 8-bit input an compares it with the accumulator. It checks to see if both are set. If either one is reset, the resulting bit in the accumulator is zero.
126
139
 
@@ -167,7 +180,7 @@ The most important use of `AND` is in bit-masking. For more information on bit-m
167
180
  ### See Also
168
181
  [BIT](#bit), [CCF](#ccf), [CPL](#cpl), [OR](#or), [RES](#res), [SCF](#scf), [SET](#set) ,[XOR](#xor)
169
182
 
170
- ---
183
+
171
184
  ## BIT
172
185
  Tests if the specified bit is set.
173
186
 
@@ -206,7 +219,7 @@ Opposite of the n<sup>th</sup> bit is written into the `Z` flag. `C` is preserve
206
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  ### See Also
207
220
  [AND](#and), [CCF](#ccf), [CP](#cp), [CPD](#cpd), [CPDR](#cpdr), [CPI](#cpi), [CPIR](#cpir), [CPL](#cpl), [OR](#or), [RES](#res), [SCF](#scf), [SET](#set), [XOR](#xor)
208
221
 
209
- ---
222
+
210
223
  ## CALL
211
224
  Pushes the address after the `CALL` instruction (`PC`+3) onto the stack and jumps to the label. Can also take conditions.
212
225
 
@@ -245,7 +258,7 @@ The most common use of `CALL` is to create routines that can be used multiple ti
245
258
  ### See Also
246
259
  [BIT](#bit), [CP](#cp), [CPD](#cpd), [CPDR](#cpdr), [CPI](#cpi), [CPIR](#cpir), [DJNZ](#djnz), [JP](#jp), [JR](#jr), [RET](#ret)
247
260
 
248
- ---
261
+
249
262
  ## CCF
250
263
  Inverts the carry flag.
251
264
 
@@ -261,7 +274,7 @@ Carry flag inverted. Also inverts `H` and clears `N`. Rest of the flags are pres
261
274
  ### See Also
262
275
  [SCF](#scf)
263
276
 
264
- ---
277
+
265
278
  ## CP
266
279
  CP is a subtraction from A that doesn't update A, only the flags it would have set/reset if it really was subtracted.
267
280
 
@@ -318,7 +331,7 @@ If A >= N, then `S` and `P/V` are the same.
318
331
  ### See also
319
332
  [BIT](#bit), [CALL](#call), [CPD](#cpd), [CPDR](#cpdr), [CPI](#cpi), [CPIR](#cpir), [JP](#jp), [JR](#jr), [RET](#ret)
320
333
 
321
- ---
334
+
322
335
  ## CPD
323
336
  Multiple instructions combined into one. `CPD` does these things in this order:
324
337
 
@@ -340,7 +353,7 @@ See [`CPDR`](#cpdr) for potential uses.
340
353
  ### See Also
341
354
  [BIT](#bit), [CALL](#call), [CP](#cp), [CPDR](#cpdr), [CPI](#cpi), [CPIR](#cpir), [JP](#jp), [JR](#jr)
342
355
 
343
- ---
356
+
344
357
  ## CPDR
345
358
  Repeats `CPD` until either:
346
359
 
@@ -372,7 +385,7 @@ _Note: if you used CPIR it would find the first occurrence of 124 in the valid m
372
385
  ### See Also
373
386
  [BIT](#bit), [CALL](#call), [CP](#cp), [CPD](#cpd), [CPI](#cpi), [CPIR](#cpir), [JP](#jp), [JR](#jr)
374
387
 
375
- ---
388
+
376
389
  ## CPI
377
390
  Multiple instructions combined into one. `CPI` does these things in this order:
378
391
 
@@ -397,7 +410,7 @@ See [`CPIR`](#cpir) for one example use.
397
410
  ### See Also
398
411
  [BIT](#bit), [CALL](#call), [CP](#cp), [CPD](#cpd), [CPDR](#cpdr), [CPIR](#cpir), [JP](#jp), [JR](#jr)
399
412
 
400
- ---
413
+
401
414
  ## CPIR
402
415
  Repeats `CPI` until either:
403
416
 
@@ -429,7 +442,7 @@ _Note: if you used CPDR it would find the last occurrence of 124 in the valid me
429
442
  ### See Also
430
443
  [BIT](#bit), [CALL](#call), [CP](#cp), [CPD](#cpd), [CPDR](#cpdr), [CPI](#cpi), [JP](#jp), [JR](#jr)
431
444
 
432
- ---
445
+
433
446
  ## CPL
434
447
  CPL inverts all bits of A.
435
448
 
@@ -449,7 +462,7 @@ Also, `CPL` \ `INC A` returns the same value that `NEG` does.
449
462
  ### See Also
450
463
  [NEG](#neg), [XOR](#xor)
451
464
 
452
- ---
465
+
453
466
  ## DAA
454
467
  When this instruction is executed, the `A` register is BCD corrected using the contents of the flags. The exact process is the following: if the least significant four bits of `A` contain a non-BCD digit (i. e. it is greater than 9) or the `H` flag is set, then $06 is added to the register. Then the four most significant bits are checked. If this more significant digit also happens to be greater than 9 or the `C` flag is set, then $60 is added.
455
468
 
@@ -465,7 +478,7 @@ If the second addition was needed, the `C` flag is set after execution, otherwis
465
478
  ### See Also
466
479
  [ADC](#adc), [ADD](#add), [DEC](#dec), [INC](#inc), [SBC](#sbc), [SUB](#sub)
467
480
 
468
- ---
481
+
469
482
  ## DEC
470
483
  Decreases operand by one.
471
484
 
@@ -518,7 +531,7 @@ No flags altered.
518
531
  ### See Also
519
532
  [ADC](#adc), [ADD](#add), [DAA](#daa), [INC](#inc), [SBC](#sbc), [SUB](#sub)
520
533
 
521
- ---
534
+
522
535
  ## DI
523
536
  Disables the interrupts (both mode 1 and mode 2).
524
537
 
@@ -539,7 +552,7 @@ Useful if you want to use the `IY` register or shadow registers, which are modif
539
552
  ### See Also
540
553
  [EI](#ei), [HALT](#halt), [IM](#im), [RETI](#reti), [RETN](#retn), [RST](#rst)
541
554
 
542
- ---
555
+
543
556
  ## DJNZ
544
557
  Decreases `B` and jumps to a label if not zero. Note that `DJNZ` does a relative jump, so it can only jump between 128 bytes back/ahead.
545
558
 
@@ -559,7 +572,7 @@ Preserves all flags.
559
572
  ### See Also
560
573
  [CALL](#call), [JP](#jp), [JR](#jr)
561
574
 
562
- ---
575
+
563
576
  ## EI
564
577
  Enables the interrupts.
565
578
 
@@ -578,8 +591,7 @@ Can either be set to interrupt mode 1 (OS interrupts) or interrupt mode 2 using
578
591
  ### See Also
579
592
  [DI](#di), [HALT](#halt), [IM](#im), [RETI](#reti), [RETN](#retn), [RST](#rst)
580
593
 
581
- ---
582
- ## EX
594
+
583
595
  ## EX
584
596
  Exchanges two 16-bit values.
585
597
 
@@ -611,7 +623,7 @@ Flags are preserved.
611
623
  ### See Also
612
624
  [EXX](#exx)
613
625
 
614
- ---
626
+
615
627
  ## EXX
616
628
  Exchanges `BC`, `DE`, and `HL` with shadow registers `BC'`, `DE'`, and `HL'`.
617
629
 
@@ -630,7 +642,7 @@ Most useful in interrupts as an alternative to saving those registers on the sta
630
642
  ### See Also
631
643
  [DI](#di), [EI](#ei), [EX](#ex), [HALT](#halt), [IM](#im), [RETI](#reti), [RETN](#retn)
632
644
 
633
- ---
645
+
634
646
  ## HALT
635
647
  Suspends all actions until the next interrupt.
636
648
 
@@ -651,7 +663,7 @@ Exactly what it says: if you need a delay, halt will provide a split second dela
651
663
  ### See Also
652
664
  [DI](#di), [EI](#ei), [NOP](#nop)
653
665
 
654
- ---
666
+
655
667
  ## IM
656
668
  Sets the interrupt mode.
657
669
 
@@ -682,7 +694,7 @@ The most important use of `IM` is to allow for the programmer to create their ow
682
694
  ### See Also
683
695
  [DI](#di), [EI](#ei), [RETI](#reti), [RETN](#retn), [RST](#rst)
684
696
 
685
- ---
697
+
686
698
  ## IN
687
699
  Reads a value from a hardware port.
688
700
 
@@ -720,7 +732,7 @@ The undocumented command `IN (C)` reads from the port and affects flags, but doe
720
732
  ### See Also
721
733
  [IND](#ind), [INDR](#indr), [INI](#ini), [INIR](#inir), [OUT](#out), [OUTD](#outd), [OTDR](#otdr), [OUTI](#outi), [OTIR](#otir)
722
734
 
723
- ---
735
+
724
736
  ## INC
725
737
  Increases operand by 1.
726
738
 
@@ -773,7 +785,7 @@ No flags altered.
773
785
  ### See Also
774
786
  [ADC](#adc), [ADD](#add), [DAA](#daa), [DEC](#dec), [SBC](#sbc), [SUB](#sub)
775
787
 
776
- ---
788
+
777
789
  ## IND
778
790
  Reads the `(C)` port and writes the result to `(HL)`, then decrements `HL` and decrements `B`.
779
791
 
@@ -789,7 +801,7 @@ Reads the `(C)` port and writes the result to `(HL)`, then decrements `HL` and d
789
801
  ### See Also
790
802
  [IN](#in), [INI](#ini), [INDR](#indr), [INIR](#inir), [OTDR](#otdr), [OTIR](#otir), [OUT](#out), [OUTD](#outd), [OUTI](#outi)
791
803
 
792
- ---
804
+
793
805
  ## INDR
794
806
  Reads the `(C)` port and writes the result to `(HL)`. `HL` and `B` are decremented. Repeats until `B` = 0.
795
807
 
@@ -808,7 +820,7 @@ Reads the `(C)` port and writes the result to `(HL)`. `HL` and `B` are decrement
808
820
  ### See Also
809
821
  [IN](#in), [IND](#ind), [INI](#ini), [INIR](#inir), [OUT](#out), [OUTD](#outd), [OTDR](#otdr), [OUTI](#outi), [OTIR](#otir)
810
822
 
811
- ---
823
+
812
824
  ## INI
813
825
  Reads the `(C)` port and writes the result to `(HL)`, then increments `HL` and decrements `B`.
814
826
 
@@ -824,7 +836,7 @@ Reads the `(C)` port and writes the result to `(HL)`, then increments `HL` and d
824
836
  ### See Also
825
837
  [IN](#in), [IND](#ind), [INDR](#indr), [INIR](#inir), [OTDR](#otdr), [OTIR](#otir), [OUT](#out), [OUTD](#outd), [OUTI](#outi)
826
838
 
827
- ---
839
+
828
840
  ## INIR
829
841
  Reads from the `(C)` port, then writes to `(HL)`. `HL` is incremented and `B` is decremented. Repeats until `B` = 0.
830
842
 
@@ -841,7 +853,7 @@ Reads from the `(C)` port, then writes to `(HL)`. `HL` is incremented and `B` is
841
853
  ### See Also
842
854
  [IN](#in), [IND](#ind), [INDR](#indr), [INI](#ini), [OUT](#out), [OUTD](#outd), [OTDR](#otdr), [OUTI](#outi), [OTIR](#otir)
843
855
 
844
- ---
856
+
845
857
  ## JP
846
858
  Absolute jumps to the address. Can be conditional or unconditional. `JP` takes one more byte than `JR`, but is also slightly faster, so decide whether speed or size is more important before choosing `JP` or `JR`. `JP (HL)`, `JP (IX)`, and `JP (IY)` are unconditional and are the fastest jumps, and do not take more bytes than other jumps.
847
859
 
@@ -886,7 +898,7 @@ All flags preserved.
886
898
  ### See Also
887
899
  [BIT](#bit), [CALL](#call), [CP](#cp), [CPD](#cpd), [CPDR](#cpdr), [CPI](#cpi), [CPIR](#cpir), [DJNZ](#djnz), [JR](#jr)
888
900
 
889
- ---
901
+
890
902
  ## JR
891
903
  Relative jumps to the address. This means that it can only jump between 128 bytes ahead or behind. Can be conditional or unconditional. `JR` takes up one less byte than `JP`, but is also slower. Weigh the needs of the code at the time before choosing one over the other (speed vs. size).
892
904
 
@@ -915,7 +927,7 @@ All flags preserved.
915
927
  ### See Also
916
928
  [BIT](#bit), [CALL](#call), [CP](#cp), [CPD](#cpd), [CPDR](#cpdr), [CPI](#cpi), [CPIR](#cpir), [DJNZ](#djnz), [JP](#jp)
917
929
 
918
- ---
930
+
919
931
  ## LD
920
932
  The `LD` instruction is used to put the value from one place into another place.
921
933
 
@@ -930,7 +942,7 @@ puts `M` into `N`.
930
942
  If x, it means allowed. If empty, it means not allowed.
931
943
 
932
944
  | | A | B | C | D | E | H | L | I | R | IXH | IXL | IYH | IYL | BC | DE | HL | SP | IX | IY | (BC) | (DE) | (HL) | (IX+N) | (IY+N) | N | NN | (NN) |
933
- |-------|---|---|---|---|---|---|---|---|---|-----|-----|-----|-----|----|----|----|----|----|----|------|------|------|--------|--------|---|----|----- |
945
+ |-||||||||||--|--|--|--|-|-|-|-|-|-||||--|--||-|-- |
934
946
  | A | x | x | x | x | x | x | x | x | x | x | x | x | x | | | | | | | x | x | x | x | x | x | | x |
935
947
  | B | x | x | x | x | x | x | x | | | x | x | x | x | | | | | | | | | x | x | x | x | | |
936
948
  | C | x | x | x | x | x | x | x | | | x | x | x | x | | | | | | | | | x | x | x | x | | |
@@ -1008,7 +1020,7 @@ Use to load numbers into operands. They can either be numbers used in the code (
1008
1020
  ### See Also
1009
1021
  [LDD](#ldd), [LDDR](#lddr), [LDI](#ldi), [LDIR](#ldir)
1010
1022
 
1011
- ---
1023
+
1012
1024
  ## LDD
1013
1025
  Does a sort of `LD (DE),(HL)`, then decrements `DE`, `HL`, and `BC`.
1014
1026
 
@@ -1046,7 +1058,7 @@ Copying over sections of data.
1046
1058
  ### See Also
1047
1059
  [LD](#ld), [LDD](#ldd), [LDI](#ldi), [LDIR](#ldir)
1048
1060
 
1049
- ---
1061
+
1050
1062
  ## LDI
1051
1063
  Performs a `LD (DE),(HL)`, then increments `DE` and `HL`, and decrements `BC`.
1052
1064
 
@@ -1065,7 +1077,7 @@ Copying data.
1065
1077
  ### See Also
1066
1078
  [LD](#ld), [LDD](#ldd), [LDDR](#lddr), [LDIR](#ldir)
1067
1079
 
1068
- ---
1080
+
1069
1081
  ## LDIR
1070
1082
  Repeats `LDI` (`LD (DE),(HL)`, then increments `DE`, `HL`, and decrements `BC`) until `BC`=0. Note that if `BC`=0 before this instruction is called, it will loop around until `BC`=0 again.
1071
1083
 
@@ -1085,7 +1097,7 @@ Copying sections of data.
1085
1097
  ### See Also
1086
1098
  [LD](#ld), [LDD](#ldd), [LDDR](#lddr), [LDI](#ldi)
1087
1099
 
1088
- ---
1100
+
1089
1101
  ## NEG
1090
1102
  `NEG` negates the accumulator.
1091
1103
 
@@ -1104,7 +1116,7 @@ This command literally subtracts `A` from 0. This explains what "modified by def
1104
1116
  ### See Also
1105
1117
  [CPL](#cpl), [SUB](#sub)
1106
1118
 
1107
- ---
1119
+
1108
1120
  ## NOP
1109
1121
  `NOP` does nothing for 4 clock cycles.
1110
1122
 
@@ -1123,7 +1135,7 @@ Useful for a short time waster (for example, it's common to put clock cycles bet
1123
1135
  ### See Also
1124
1136
  [HALT](#halt)
1125
1137
 
1126
- ---
1138
+
1127
1139
  ## OR
1128
1140
  `OR` is an instruction that takes an 8-bit input an compare sit with the accumulator. It checks to see if anything is set, and if neither are set, it results in a zero.
1129
1141
 
@@ -1170,7 +1182,7 @@ Used in bit-masking. For more information see here.
1170
1182
  ### See Also
1171
1183
  [AND](#and), [BIT](#bit), [CCF](#ccf), [CPL](#cpl), [RES](#res), [SCF](#scf), [SET](#set), [XOR](#xor)
1172
1184
 
1173
- ---
1185
+
1174
1186
  ## OTDR
1175
1187
  Reads from `(HL)` and writes to the `(C)` port. `HL` and `B` are then decremented. Repeats until `B` = 0.
1176
1188
 
@@ -1187,7 +1199,7 @@ Reads from `(HL)` and writes to the `(C)` port. `HL` and `B` are then decremente
1187
1199
  ### See Also
1188
1200
  [IN](#in), [IND](#ind), [INDR](#indr), [INI](#ini), [INIR](#inir), [OUT](#out), [OUTD](#outd), [OUTI](#outi), [OTIR](#otir)
1189
1201
 
1190
- ---
1202
+
1191
1203
  ## OTIR
1192
1204
  Reads from `(HL)` and writes to the `(C)` port. `HL` is incremented and `B` is decremented. Repeats until `B` = 0.
1193
1205
 
@@ -1204,7 +1216,7 @@ Reads from `(HL)` and writes to the `(C)` port. `HL` is incremented and `B` is d
1204
1216
  ### See Also
1205
1217
  [IN](#in), [IND](#ind), [INDR](#indr), [INI](#ini), [INIR](#inir), [OUT](#out), [OUTD](#outd), [OTDR](#otdr), [OUTI](#outi)
1206
1218
 
1207
- ---
1219
+
1208
1220
  ## OUT
1209
1221
  Writes the value of the second operand into the port given by the first operand.
1210
1222
 
@@ -1236,7 +1248,7 @@ All flags preserved
1236
1248
  ### See Also
1237
1249
  [IN](#in), [IND](#ind), [INDR](#indr), [INI](#ini), [INIR](#inir), [OUTD](#outd), [OTDR](#otdr), [OUTI](#outi), [OTIR](#otir)
1238
1250
 
1239
- ---
1251
+
1240
1252
  ## OUTD
1241
1253
  Writes the value from `(HL)` to the `(C)` port, then decrements `B` and `HL`.
1242
1254
 
@@ -1252,7 +1264,7 @@ Writes the value from `(HL)` to the `(C)` port, then decrements `B` and `HL`.
1252
1264
  ### See Also
1253
1265
  [IN](#in), [IND](#ind), [INDR](#indr), [INI](#ini), [INIR](#inir), [OUT](#out), [OTDR](#otdr), [OUTI](#outi), [OTIR](#otir)
1254
1266
 
1255
- ---
1267
+
1256
1268
  ## OUTI
1257
1269
  Reads from `(HL)` and writes to the `(C)` port. `HL` is then incremented, and `B` is decremented.
1258
1270
 
@@ -1270,7 +1282,7 @@ Reads from `(HL)` and writes to the `(C)` port. `HL` is then incremented, and `B
1270
1282
  ### See Also
1271
1283
  [IN](#in), [IND](#ind), [INDR](#indr), [INI](#ini), [INIR](#inir), [OUT](#out), [OUTD](#outd), [OTDR](#otdr), [OTIR](#otir)
1272
1284
 
1273
- ---
1285
+
1274
1286
  ## POP
1275
1287
  Copies the two bytes from `(SP)` into the operand, then increases `SP` by 2.
1276
1288
 
@@ -1301,7 +1313,7 @@ Used for retrieving values saved on the stack. Also used when you want to load a
1301
1313
  ### See Also
1302
1314
  [PUSH](#push)
1303
1315
 
1304
- ---
1316
+
1305
1317
  ## PUSH
1306
1318
  Copies the operand into `(SP)`, then decrements `SP` by 2.
1307
1319
 
@@ -1332,7 +1344,7 @@ Used for saving register values onto the stack. Also used when you want to load
1332
1344
  ### See Also
1333
1345
  [POP](#pop)
1334
1346
 
1335
- ---
1347
+
1336
1348
  ## RES
1337
1349
  Resets the specified bit to zero.
1338
1350
 
@@ -1367,7 +1379,7 @@ Flags are preserved.
1367
1379
  ### See Also
1368
1380
  [AND](#and), [BIT](#bit), [CCF](#ccf), [CPL](#cpl), [OR](#or), [SCF](#scf), [SET](#set), [XOR](#xor)
1369
1381
 
1370
- ---
1382
+
1371
1383
  ## RET
1372
1384
  Pops the top of the stack into the program counter. Note that `RET` can be either conditional or unconditional.
1373
1385
 
@@ -1401,7 +1413,7 @@ Preserves all flags.
1401
1413
  ### See Also
1402
1414
  [BIT](#bit), [CALL](#call), [CP](#cp), [CPD](#cpd), [CPDR](#cpdr), [CPI](#cpi), [CPIR](#cpir), [RETI](#reti), [RETN](#retn)
1403
1415
 
1404
- ---
1416
+
1405
1417
  ## RETI
1406
1418
  Returns from an interrupt routine. Note: `RETI` cannot use return conditions.
1407
1419
 
@@ -1417,7 +1429,7 @@ All flags unaffected.
1417
1429
  ### See Also
1418
1430
  [DI](#di), [EI](#ei), [IM](#im), [RET](#ret), [RETN](#retn), [RST](#rst)
1419
1431
 
1420
- ---
1432
+
1421
1433
  ## RETN
1422
1434
  Returns from the non-maskable interrupt (NMI). Cannot take return conditions.
1423
1435
 
@@ -1433,7 +1445,7 @@ All flags unaffected.
1433
1445
  ### See Also
1434
1446
  [DI](#di), [EI](#ei), [IM](#im), [RET](#ret), [RETI](#reti), [RST](#rst)
1435
1447
 
1436
- ---
1448
+
1437
1449
  ## RL
1438
1450
  9-bit rotation to the left. The register's bits are shifted left. The carry value is put into 0<sup>th</sup> bit of the register, and the leaving 7th bit is put into the carry.
1439
1451
 
@@ -1466,7 +1478,7 @@ All flags unaffected.
1466
1478
  ### See Also
1467
1479
  [RLA](#rla), [RLC](#rlc), [RLCA](#rlca), [RLD](#rld), [RR](#rr), [RRA](#rra), [RRC](#rrc), [RRCA](#rrca), [RRD](#rrd), [SLA](#sla), [SLL/SL1](#sllsl1), [SRA](#sra), [SRL](#srl)
1468
1480
 
1469
- ---
1481
+
1470
1482
  ## RLA
1471
1483
  Performs an `RL A`, but is much faster and `S`, `Z`, and `P/V` flags are preserved.
1472
1484
 
@@ -1482,7 +1494,7 @@ Performs an `RL A`, but is much faster and `S`, `Z`, and `P/V` flags are preserv
1482
1494
  ### See Also
1483
1495
  [RL](#rl), [RLC](#rlc), [RLCA](#rlca), [RLD](#rld), [RR](#rr), [RRA](#rra), [RRC](#rrc), [RRCA](#rrca), [RRD](#rrd), [SLA](#sla), [SLL/SL1](#sllsl1), [SRA](#sra), [SRL](#srl)
1484
1496
 
1485
- ---
1497
+
1486
1498
  ## RLC
1487
1499
  8-bit rotation to the left. The bit leaving on the left is copied into the carry, and to bit 0.
1488
1500
 
@@ -1515,7 +1527,7 @@ Performs an `RL A`, but is much faster and `S`, `Z`, and `P/V` flags are preserv
1515
1527
  ### See Also
1516
1528
  [RL](#rl), [RLA](#rla), [RLCA](#rlca), [RLD](#rld), [RR](#rr), [RRA](#rra), [RRC](#rrc), [RRCA](#rrca), [RRD](#rrd), [SLA](#sla), [SLL/SL1](#sllsl1), [SRA](#sra), [SRL](#srl)
1517
1529
 
1518
- ---
1530
+
1519
1531
  ## RLCA
1520
1532
  Performs `RLC A` much quicker, and modifies the flags differently.
1521
1533
 
@@ -1531,7 +1543,7 @@ Performs `RLC A` much quicker, and modifies the flags differently.
1531
1543
  ### See Also
1532
1544
  [RL](#rl), [RLA](#rla), [RLC](#rlc), [RLD](#rld), [RR](#rr), [RRA](#rra), [RRC](#rrc), [RRCA](#rrca), [RRD](#rrd), [SLA](#sla), [SLL/SL1](#sllsl1), [SRA](#sra), [SRL](#srl)
1533
1545
 
1534
- ---
1546
+
1535
1547
  ## RLD
1536
1548
  Performs a 4-bit leftward rotation of the 12-bit number whose 4 most significant bits are the 4 least significant bits of A, and its 8 least significant bits are in (HL).
1537
1549
 
@@ -1554,7 +1566,7 @@ The `H` and `N` flags are reset, `P/V` is parity, `C` is preserved, and `S` and
1554
1566
  ### See Also
1555
1567
  [RL](#rl), [RLA](#rla), [RLC](#rlc), [RLCA](#rlca), [RR](#rr), [RRA](#rra), [RRC](#rrc), [RRCA](#rrca), [RRD](#rrd), [SLA](#sla), [SLL/SL1](#sllsl1), [SRA](#sra), [SRL](#srl)
1556
1568
 
1557
- ---
1569
+
1558
1570
  ## RR
1559
1571
  9-bit rotation to the right. The carry is copied into bit 7, and the bit leaving on the right is copied into the carry.
1560
1572
 
@@ -1587,7 +1599,7 @@ Carry becomes the bit leaving on the right, `H` and `N` flags are reset, `P/V` i
1587
1599
  ### See Also
1588
1600
  [RL](#rl), [RLA](#rla), [RLC](#rlc), [RLCA](#rlca), [RLD](#rld), [RRA](#rra), [RRC](#rrc), [RRCA](#rrca), [RRD](#rrd), [SLA](#sla), [SLL/SL1](#sllsl1), [SRA](#sra), [SRL](#srl)
1589
1601
 
1590
- ---
1602
+
1591
1603
  ## RRA
1592
1604
  Performs an `RR A`, but is much faster and `P/V`, `S`, and `Z` flags are preserved.
1593
1605
 
@@ -1603,7 +1615,7 @@ The carry becomes the bit leaving on the right, `H` and `N` flags are reset, `P/
1603
1615
  ### See Also
1604
1616
  [RL](#rl), [RLA](#rla), [RLC](#rlc), [RLCA](#rlca), [RLD](#rld), [RR](#rr), [RRC](#rrc), [RRCA](#rrca), [RRD](#rrd), [SLA](#sla), [SLL/SL1](#sllsl1), [SRA](#sra), [SRL](#srl)
1605
1617
 
1606
- ---
1618
+
1607
1619
  ## RRC
1608
1620
  8-bit rotation to the right. The bit leaving on the right is copied into the carry, and into bit 7.
1609
1621
 
@@ -1653,7 +1665,7 @@ The carry becomes the value leaving on the right, `H` and `N` are reset, `P/V`,
1653
1665
  ### See Also
1654
1666
  [RL](#rl), [RLA](#rla), [RLC](#rlc), [RLCA](#rlca), [RLD](#rld), [RR](#rr), [RRA](#rra), [RRC](#rrc), [RRD](#rrd), [SLA](#sla), [SLL/SL1](#sllsl1), [SRA](#sra), [SRL](#srl)
1655
1667
 
1656
- ---
1668
+
1657
1669
  ## RRD
1658
1670
  Performs a 4-bit rightward rotation of the 12-bit number whose 4 most significant bits are the 4 least significant bits of `A`, and its 8 least significant bits are in `(HL)`.
1659
1671
 
@@ -1676,7 +1688,7 @@ The `H` and `N` flags are reset, `P/V` is parity, `C` is preserved, and `S` and
1676
1688
  ### See Also
1677
1689
  [RL](#rl), [RLA](#rla), [RLC](#rlc), [RLCA](#rlca), [RLD](#rld), [RR](#rr), [RRA](#rra), [RRC](#rrc), [RRCA](#rrca), [SLA](#sla), [SLL/SL1](#sllsl1), [SRA](#sra), [SRL](#srl)
1678
1690
 
1679
- ---
1691
+
1680
1692
  ## RST
1681
1693
  The current `PC` value plus three is pushed onto the stack. The MSB is loaded with $00 and the LSB is loaded with `imm8`.
1682
1694
 
@@ -1702,7 +1714,7 @@ All flags unaffected.
1702
1714
  ### See Also
1703
1715
  [DI](#di), [EI](#ei), [IM](#im), [RET](#ret), [RETI](#reti), [RETN](#retn)
1704
1716
 
1705
- ---
1717
+
1706
1718
  ## SBC
1707
1719
  Sum of second operand and carry flag is subtracted from the first operand. Results are written into the first operand.
1708
1720
 
@@ -1753,7 +1765,7 @@ Multiple precision subtraction
1753
1765
  ### See Also
1754
1766
  [ADC](#adc), [ADD](#add), [DAA](#daa), [DEC](#dec), [INC](#inc), [SUB](#sub)
1755
1767
 
1756
- ---
1768
+
1757
1769
  ## SCF
1758
1770
  Sets carry flag.
1759
1771
 
@@ -1769,7 +1781,7 @@ Carry flag set, `H` and `N` cleared, rest are preserved.
1769
1781
  ### See Also
1770
1782
  [CCF](#ccf)
1771
1783
 
1772
- ---
1784
+
1773
1785
  ## SET
1774
1786
  Sets the specified bit.
1775
1787
 
@@ -1804,7 +1816,7 @@ All flags preserved.
1804
1816
  ### See Also
1805
1817
  [AND](#and), [BIT](#bit), [CCF](#ccf), [CPL](#cpl), [OR](#or), [RES](#res), [SCF](#scf), [XOR](#xor)
1806
1818
 
1807
- ---
1819
+
1808
1820
  ## SLA
1809
1821
  An arithmetic shift left 1 bit position is performed on the contents of register `r`. The contents of bit 7 are copied to the carry flag. Bit 0 is the least-significant bit.
1810
1822
 
@@ -1837,7 +1849,7 @@ An arithmetic shift left 1 bit position is performed on the contents of register
1837
1849
  ### See Also
1838
1850
  [RL](#rl), [RLA](#rla), [RLC](#rlc), [RLCA](#rlca), [RLD](#rld), [RR](#rr), [RRA](#rra), [RRC](#rrc), [RRCA](#rrca), [RRD](#rrd), [SLL/SL1](#sllsl1), [SRA](#sra), [SRL](#srl)
1839
1851
 
1840
- ---
1852
+
1841
1853
  ## SLL/SL1
1842
1854
  An "undocumented" instruction. Functions like `SLA`, except a 1 is inserted into the low bit.
1843
1855
 
@@ -1870,7 +1882,7 @@ An "undocumented" instruction. Functions like `SLA`, except a 1 is inserted into
1870
1882
  ### See Also
1871
1883
  [RL](#rl), [RLA](#rla), [RLC](#rlc), [RLCA](#rlca), [RLD](#rld), [RR](#rr), [RRA](#rra), [RRC](#rrc), [RRCA](#rrca), [RRD](#rrd), [SLA](#sla), [SRA](#sra), [SRL](#srl)
1872
1884
 
1873
- ---
1885
+
1874
1886
  ## SRA
1875
1887
  Arithmetic shift right 1 bit, bit 0 goes to carry flag, bit 7 remains unchanged.
1876
1888
 
@@ -1903,7 +1915,7 @@ Arithmetic shift right 1 bit, bit 0 goes to carry flag, bit 7 remains unchanged.
1903
1915
  ### See Also
1904
1916
  [RL](#rl), [RLA](#rla), [RLC](#rlc), [RLCA](#rlca), [RLD](#rld), [RR](#rr), [RRA](#rra), [RRC](#rrc), [RRCA](#rrca), [RRD](#rrd), [SLA](#sla), [SLL/SL1](#sllsl1), [SRL](#srl)
1905
1917
 
1906
- ---
1918
+
1907
1919
  ## SRL
1908
1920
  Like `SRA`, except a 0 is put into bit 7. The bits are all shifted right, with bit 0 put into the carry flag.
1909
1921
 
@@ -1936,7 +1948,7 @@ Like `SRA`, except a 0 is put into bit 7. The bits are all shifted right, with b
1936
1948
  ### See Also
1937
1949
  [RL](#rl), [RLA](#rla), [RLC](#rlc), [RLCA](#rlca), [RLD](#rld), [RR](#rr), [RRA](#rra), [RRC](#rrc), [RRCA](#rrca), [RRD](#rrd), [SLA](#sla), [SLL/SL1](#sllsl1), [SRA](#sra)
1938
1950
 
1939
- ---
1951
+
1940
1952
  ## SUB
1941
1953
  `SUB` stands for subtract but only takes one input. It subtracts the input from the accumulator and writes back to it.
1942
1954
 
@@ -1975,7 +1987,7 @@ Allows you to subtract two 8 bit integers. Useful in if you have an offset and w
1975
1987
  ### See Also
1976
1988
  [ADC](#adc), [ADD](#add), [DAA](#daa), [DEC](#dec), [INC](#inc), [SBC](#sbc)
1977
1989
 
1978
- ---
1990
+
1979
1991
  ## XOR
1980
1992
  `XOR` is an instruction that takes one 8-bit input and compares it with the accumulator. `XOR` is similar to `OR`, except for one thing: only 1 of the 2 test bits can be set or else it will result in a zero. The final answer is stored to the accumulator.
1981
1993
 
@@ -2022,4 +2034,4 @@ XORing numbers is used a lot to invert sprites and such. It is also very useful
2022
2034
  ### See Also
2023
2035
  [AND](#and), [BIT](#bit), [CCF](#ccf), [CPL](#cpl), [OR](#or), [RES](#res), [SCF](#scf), [SET](#set)
2024
2036
 
2025
- ---
2037
+ ---