@modular-circuit/transpiler 0.2.10 → 0.2.12

package/dist/index.d.mts

@@ -1,6 +1,7 @@
 import { VECTOR2, At, Color, ConnectionGraph, NL_NetList, BOX2 } from '@modular-circuit/electronics-model';
 import { SCHEMATIC, PIN_DISPLAY_OPT, LIB_SYMBOL, Drawing, PIN_DEFINITION, SCH_LABEL, SCH_SYMBOL, SCH_LINE, PIN_INSTANCE, SCH_SHEET, SCH_SHEET_PIN, Effects, Justify, SCH_FIELD, Fill, Stroke, Project, IR_Graph, DesignBlockContent, ModuleResolver, ModuleCircuit } from '@modular-circuit/ir';
 import { CG_SCHEMATIC, CONNECTION_GRAPH_BUILDER_CTX } from '@modular-circuit/perc';
+import { NetlistTranspiler } from '@modular-circuit/genai';
 
 declare function get_sch_default_drawing_sheet(): string;
 
@@ -43,6 +44,10 @@ declare class SCHEMATIC_PRINTER {
 interface ConvertGraphToKiCadInput extends Omit<CONNECTION_GRAPH_BUILDER_CTX, 'dependencies'> {
     project: Project;
     schematics: Record<string, IR_Graph>;
+    /**
+     * If provided and there is ResolvedAbstractBlock in the schematics, the netlist in ResolvedAbstractBlock will be converted to kicad_sch
+     */
+    netlist_transpiler?: NetlistTranspiler;
 }
 interface ConnectionGraphMap {
     connection_graph: ConnectionGraph;
@@ -401,9 +406,6 @@ declare function collect_sub_sheets_by_id(module_ids: string[], module_resolver:
     design_blocks: DesignBlockContent[];
 }>;
 
-declare const fmt_to_valid_filename: (name: string) => string;
-declare const fmt_module_place_holder_sch_name: (mod_name: string) => string;
-
 declare const gen_empty_sch: (name: string) => Promise<string>;
 
 declare const gen_lib_gnd: (value: string) => LIB_SYMBOL;
@@ -414,4 +416,4 @@ declare const gen_sch_gnd: (value: string, pwr_number: number, port_id: string,
 
 declare const gen_sch_vcc: (value: string, pwr_number: number, port_id: string, position: VECTOR2) => SCH_SYMBOL;
 
-export { BLOCK_PIN_GAP, BLOCK_PIN_TB_MARGIN, type BlockLabelPadding, type BlockSize, type BoxGeometry, type ConnectionGraphMap, type ConvertGraphToKiCadContext, type ConvertGraphToKiCadInput, FONT_SIZE, GRID_SIZE, GraphConverter, KICAD_SCH_FRAME, KiCadProjectArchive, type LabelPadding, Layout, NetListConverter, type NetlistProject, type NetlistToKicadContext, SCHEMATIC_PRINTER, StringFormatter, WIRE_PADDING, collect_sub_sheets, collect_sub_sheets_by_id, convert_graph_to_design_block, convert_graph_to_kicad_project, convert_graph_to_sheets, filterNullOrUndefined, fmt_module_place_holder_sch_name, fmt_to_valid_filename, gen_empty_sch, gen_lib_gnd, gen_lib_vcc, gen_sch_gnd, gen_sch_vcc, get_power_pos, get_sch_default_drawing_sheet, tab };
+export { BLOCK_PIN_GAP, BLOCK_PIN_TB_MARGIN, type BlockLabelPadding, type BlockSize, type BoxGeometry, type ConnectionGraphMap, type ConvertGraphToKiCadContext, type ConvertGraphToKiCadInput, FONT_SIZE, GRID_SIZE, GraphConverter, KICAD_SCH_FRAME, KiCadProjectArchive, type LabelPadding, Layout, NetListConverter, type NetlistProject, type NetlistToKicadContext, SCHEMATIC_PRINTER, StringFormatter, WIRE_PADDING, collect_sub_sheets, collect_sub_sheets_by_id, convert_graph_to_design_block, convert_graph_to_kicad_project, convert_graph_to_sheets, filterNullOrUndefined, gen_empty_sch, gen_lib_gnd, gen_lib_vcc, gen_sch_gnd, gen_sch_vcc, get_power_pos, get_sch_default_drawing_sheet, tab };

package/dist/index.d.ts

@@ -1,6 +1,7 @@
 import { VECTOR2, At, Color, ConnectionGraph, NL_NetList, BOX2 } from '@modular-circuit/electronics-model';
 import { SCHEMATIC, PIN_DISPLAY_OPT, LIB_SYMBOL, Drawing, PIN_DEFINITION, SCH_LABEL, SCH_SYMBOL, SCH_LINE, PIN_INSTANCE, SCH_SHEET, SCH_SHEET_PIN, Effects, Justify, SCH_FIELD, Fill, Stroke, Project, IR_Graph, DesignBlockContent, ModuleResolver, ModuleCircuit } from '@modular-circuit/ir';
 import { CG_SCHEMATIC, CONNECTION_GRAPH_BUILDER_CTX } from '@modular-circuit/perc';
+import { NetlistTranspiler } from '@modular-circuit/genai';
 
 declare function get_sch_default_drawing_sheet(): string;
 
@@ -43,6 +44,10 @@ declare class SCHEMATIC_PRINTER {
 interface ConvertGraphToKiCadInput extends Omit<CONNECTION_GRAPH_BUILDER_CTX, 'dependencies'> {
     project: Project;
     schematics: Record<string, IR_Graph>;
+    /**
+     * If provided and there is ResolvedAbstractBlock in the schematics, the netlist in ResolvedAbstractBlock will be converted to kicad_sch
+     */
+    netlist_transpiler?: NetlistTranspiler;
 }
 interface ConnectionGraphMap {
     connection_graph: ConnectionGraph;
@@ -401,9 +406,6 @@ declare function collect_sub_sheets_by_id(module_ids: string[], module_resolver:
     design_blocks: DesignBlockContent[];
 }>;
 
-declare const fmt_to_valid_filename: (name: string) => string;
-declare const fmt_module_place_holder_sch_name: (mod_name: string) => string;
-
 declare const gen_empty_sch: (name: string) => Promise<string>;
 
 declare const gen_lib_gnd: (value: string) => LIB_SYMBOL;
@@ -414,4 +416,4 @@ declare const gen_sch_gnd: (value: string, pwr_number: number, port_id: string,
 
 declare const gen_sch_vcc: (value: string, pwr_number: number, port_id: string, position: VECTOR2) => SCH_SYMBOL;
 
-export { BLOCK_PIN_GAP, BLOCK_PIN_TB_MARGIN, type BlockLabelPadding, type BlockSize, type BoxGeometry, type ConnectionGraphMap, type ConvertGraphToKiCadContext, type ConvertGraphToKiCadInput, FONT_SIZE, GRID_SIZE, GraphConverter, KICAD_SCH_FRAME, KiCadProjectArchive, type LabelPadding, Layout, NetListConverter, type NetlistProject, type NetlistToKicadContext, SCHEMATIC_PRINTER, StringFormatter, WIRE_PADDING, collect_sub_sheets, collect_sub_sheets_by_id, convert_graph_to_design_block, convert_graph_to_kicad_project, convert_graph_to_sheets, filterNullOrUndefined, fmt_module_place_holder_sch_name, fmt_to_valid_filename, gen_empty_sch, gen_lib_gnd, gen_lib_vcc, gen_sch_gnd, gen_sch_vcc, get_power_pos, get_sch_default_drawing_sheet, tab };
+export { BLOCK_PIN_GAP, BLOCK_PIN_TB_MARGIN, type BlockLabelPadding, type BlockSize, type BoxGeometry, type ConnectionGraphMap, type ConvertGraphToKiCadContext, type ConvertGraphToKiCadInput, FONT_SIZE, GRID_SIZE, GraphConverter, KICAD_SCH_FRAME, KiCadProjectArchive, type LabelPadding, Layout, NetListConverter, type NetlistProject, type NetlistToKicadContext, SCHEMATIC_PRINTER, StringFormatter, WIRE_PADDING, collect_sub_sheets, collect_sub_sheets_by_id, convert_graph_to_design_block, convert_graph_to_kicad_project, convert_graph_to_sheets, filterNullOrUndefined, gen_empty_sch, gen_lib_gnd, gen_lib_vcc, gen_sch_gnd, gen_sch_vcc, get_power_pos, get_sch_default_drawing_sheet, tab };

package/dist/index.js

@@ -92,8 +92,6 @@ __export(index_exports, {
   convert_graph_to_kicad_project: () => convert_graph_to_kicad_project,
   convert_graph_to_sheets: () => convert_graph_to_sheets,
   filterNullOrUndefined: () => filterNullOrUndefined,
-  fmt_module_place_holder_sch_name: () => fmt_module_place_holder_sch_name,
-  fmt_to_valid_filename: () => fmt_to_valid_filename,
   gen_empty_sch: () => gen_empty_sch,
   gen_lib_gnd: () => gen_lib_gnd,
   gen_lib_vcc: () => gen_lib_vcc,
@@ -263,12 +261,6 @@ async function collect_sub_sheets_by_id(module_ids, module_resolver) {
   return { sheets, module_main_sheet, modules, design_blocks };
 }
 
-// src/utils/fmt_to_valid_filename.ts
-var fmt_to_valid_filename = (name) => {
-  return name.replace(/[\\/:*?"<>|]/g, "_").trim();
-};
-var fmt_module_place_holder_sch_name = (mod_name) => `placeholder_${fmt_to_valid_filename(mod_name)}.kicad_sch`;
-
 // src/utils/gen_empty_sch.ts
 var import_utils3 = require("@modular-circuit/utils");
 var gen_empty_sch = async (name) => {
@@ -2608,16 +2600,24 @@ var import_perc = require("@modular-circuit/perc");
 var import_utils16 = require("@modular-circuit/utils");
 async function do_convert_graph_to_kicad_project(ctx) {
   const module_ids = [];
+  const generated_sheets = {};
   for (const sch of Object.values(ctx.schematics)) {
     for (const mod of sch.blocks ?? []) {
-      if (!(0, import_ir5.block_is_abstract)(mod) && (0, import_ir5.block_is_associated_with_concrete_module)(mod.type)) {
-        module_ids.push(mod.type);
+      if (!(0, import_ir5.block_is_abstract)(mod)) {
+        if ((0, import_ir5.block_is_associated_with_concrete_module)(mod.type)) module_ids.push(mod.type);
+      } else {
+        if (ctx.netlist_transpiler && (0, import_ir5.block_is_resolved_abstract)(mod)) {
+          const sheet_file_name = (0, import_utils16.fmt_abstract_sch_name)(mod);
+          const netlist2 = mod.netlist;
+          generated_sheets[sheet_file_name] = await ctx.netlist_transpiler.convert_netlist_to_kicad(netlist2);
+        }
       }
     }
   }
   const { sheets } = {
     ...await collect_sub_sheets(ctx.project.dependencies, ctx.module_resolver),
-    ...await collect_sub_sheets_by_id(module_ids, ctx.module_resolver)
+    ...await collect_sub_sheets_by_id(module_ids, ctx.module_resolver),
+    ...{ sheets: generated_sheets }
   };
   const netlist = new GraphConverter({
     ...ctx
@@ -2626,7 +2626,7 @@ async function do_convert_graph_to_kicad_project(ctx) {
     for (const sheet of sch.sheet_symbols) {
       const original_st_fn = sheet.sheet_file_name;
       if (!(original_st_fn in sheets)) {
-        const placeholder_fn = fmt_module_place_holder_sch_name(sheet.sheet_name);
+        const placeholder_fn = (0, import_utils16.fmt_module_place_holder_sch_name)(sheet.sheet_name);
         sheet.sheet_file_name = placeholder_fn;
         sheets[placeholder_fn] = await gen_empty_sch(placeholder_fn);
       }
@@ -3097,8 +3097,6 @@ async function convert_graph_to_kicad_project(ctx) {
   convert_graph_to_kicad_project,
   convert_graph_to_sheets,
   filterNullOrUndefined,
-  fmt_module_place_holder_sch_name,
-  fmt_to_valid_filename,
   gen_empty_sch,
   gen_lib_gnd,
   gen_lib_vcc,

package/dist/index.mjs

@@ -217,12 +217,6 @@ async function collect_sub_sheets_by_id(module_ids, module_resolver) {
   return { sheets, module_main_sheet, modules, design_blocks };
 }
 
-// src/utils/fmt_to_valid_filename.ts
-var fmt_to_valid_filename = (name) => {
-  return name.replace(/[\\/:*?"<>|]/g, "_").trim();
-};
-var fmt_module_place_holder_sch_name = (mod_name) => `placeholder_${fmt_to_valid_filename(mod_name)}.kicad_sch`;
-
 // src/utils/gen_empty_sch.ts
 import { gen_uuid } from "@modular-circuit/utils";
 var gen_empty_sch = async (name) => {
@@ -2574,22 +2568,35 @@ var NetListConverter = class {
 import {
   MODULAR_CIRCUIT_SCH_EXT as MODULAR_CIRCUIT_SCH_EXT2,
   block_is_abstract,
-  block_is_associated_with_concrete_module
+  block_is_associated_with_concrete_module,
+  block_is_resolved_abstract
 } from "@modular-circuit/ir";
 import { build_connection_graph } from "@modular-circuit/perc";
-import { KiCadSchematicFileExtension as KiCadSchematicFileExtension3 } from "@modular-circuit/utils";
+import {
+  fmt_abstract_sch_name,
+  fmt_module_place_holder_sch_name,
+  KiCadSchematicFileExtension as KiCadSchematicFileExtension3
+} from "@modular-circuit/utils";
 async function do_convert_graph_to_kicad_project(ctx) {
   const module_ids = [];
+  const generated_sheets = {};
   for (const sch of Object.values(ctx.schematics)) {
     for (const mod of sch.blocks ?? []) {
-      if (!block_is_abstract(mod) && block_is_associated_with_concrete_module(mod.type)) {
-        module_ids.push(mod.type);
+      if (!block_is_abstract(mod)) {
+        if (block_is_associated_with_concrete_module(mod.type)) module_ids.push(mod.type);
+      } else {
+        if (ctx.netlist_transpiler && block_is_resolved_abstract(mod)) {
+          const sheet_file_name = fmt_abstract_sch_name(mod);
+          const netlist2 = mod.netlist;
+          generated_sheets[sheet_file_name] = await ctx.netlist_transpiler.convert_netlist_to_kicad(netlist2);
+        }
       }
     }
   }
   const { sheets } = {
     ...await collect_sub_sheets(ctx.project.dependencies, ctx.module_resolver),
-    ...await collect_sub_sheets_by_id(module_ids, ctx.module_resolver)
+    ...await collect_sub_sheets_by_id(module_ids, ctx.module_resolver),
+    ...{ sheets: generated_sheets }
   };
   const netlist = new GraphConverter({
     ...ctx
@@ -3073,8 +3080,6 @@ export {
   convert_graph_to_kicad_project,
   convert_graph_to_sheets,
   filterNullOrUndefined,
-  fmt_module_place_holder_sch_name,
-  fmt_to_valid_filename,
   gen_empty_sch,
   gen_lib_gnd,
   gen_lib_vcc,

package/package.json

@@ -1,6 +1,6 @@
 {
   "name": "@modular-circuit/transpiler",
-  "version": "0.2.10",
+  "version": "0.2.12",
   "description": "Intermediate representation of the modular circuit",
   "main": "./dist/index.js",
   "module": "./dist/index.mjs",
@@ -29,10 +29,11 @@
     "elkjs": "^0.11.0",
     "js-base64": "^3.7.7",
     "jszip": "^3.10.1",
-    "@modular-circuit/ir": "0.2.10",
-    "@modular-circuit/electronics-model": "0.2.12",
-    "@modular-circuit/perc": "0.2.18",
-    "@modular-circuit/utils": "0.2.10"
+    "@modular-circuit/electronics-model": "0.2.14",
+    "@modular-circuit/ir": "0.2.12",
+    "@modular-circuit/utils": "0.2.12",
+    "@modular-circuit/genai": "0.1.10",
+    "@modular-circuit/perc": "0.2.20"
   },
   "scripts": {
     "clean": "rimraf dist",