@modular-circuit/transpiler 0.1.8 → 0.1.10
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/dist/index.d.mts +7 -12
- package/dist/index.d.ts +7 -12
- package/dist/index.js +30 -4
- package/dist/index.mjs +28 -4
- package/package.json +3 -3
package/dist/index.d.mts
CHANGED
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@@ -1,5 +1,5 @@
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1
1
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import { VECTOR2, At, Color, ConnectionGraph, NL_NetList, BOX2 } from '@modular-circuit/electronics-model';
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2
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-
import { SCHEMATIC, PIN_DISPLAY_OPT, LIB_SYMBOL, Drawing, PIN_DEFINITION, SCH_LABEL, SCH_SYMBOL, SCH_LINE, PIN_INSTANCE, SCH_SHEET, SCH_SHEET_PIN, Effects, Justify, SCH_FIELD, Fill, Stroke, Project, IR_Graph, ModuleResolver, ModuleCircuit } from '@modular-circuit/ir';
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import { SCHEMATIC, PIN_DISPLAY_OPT, LIB_SYMBOL, Drawing, PIN_DEFINITION, SCH_LABEL, SCH_SYMBOL, SCH_LINE, PIN_INSTANCE, SCH_SHEET, SCH_SHEET_PIN, Effects, Justify, SCH_FIELD, Fill, Stroke, Project, IR_Graph, DesignBlockContent, ModuleResolver, ModuleCircuit } from '@modular-circuit/ir';
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import { CG_SCHEMATIC, CONNECTION_GRAPH_BUILDER_CTX } from '@modular-circuit/perc';
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declare function get_sch_default_drawing_sheet(): string;
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@@ -128,8 +128,12 @@ declare class NetListConverter {
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private convert_net_label;
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}
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+
declare function convert_graph_to_sheets(ctx: ConvertGraphToKiCadInput): Promise<Record<string, string>>;
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declare function convert_graph_to_kicad_project(ctx: ConvertGraphToKiCadInput): Promise<Blob>;
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declare function convert_graph_to_design_block(ctx: ConvertGraphToKiCadInput): Promise<DesignBlockContent>;
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declare const KiCadSymbolLibFileExtension = "kicad_sym";
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declare const SchematicSymbolFileExtension = "sym";
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declare const LegacySymbolLibFileExtension = "lib";
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@@ -463,20 +467,11 @@ declare class StringFormatter {
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append_quote(str: string): void;
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}
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-
interface NamedContent {
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filename: string;
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content: string;
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}
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interface DesignBlock {
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main_sch: string;
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sheets: NamedContent[];
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pcb?: NamedContent;
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-
}
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declare function collect_sub_sheets_by_id(module_ids: string[], module_resolver: ModuleResolver): Promise<{
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sheets: Record<string, string>;
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module_main_sheet: Record<string, string>;
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modules: Record<string, ModuleCircuit>;
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-
design_blocks:
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design_blocks: DesignBlockContent[];
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}>;
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declare const gen_lib_gnd: (value: string) => LIB_SYMBOL;
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@@ -487,4 +482,4 @@ declare const gen_sch_gnd: (value: string, pwr_number: number, port_id: string,
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declare const gen_sch_vcc: (value: string, pwr_number: number, port_id: string, position: VECTOR2) => SCH_SYMBOL;
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-
export { AllegroNetlistFileExtension, AltiumFootprintLibPathExtension, ArchiveFileExtension, BLOCK_PIN_GAP, BLOCK_PIN_TB_MARGIN, type BlockLabelPadding, type BlockSize, type BoxGeometry, CadstarFootprintLibPathExtension, CadstarNetlistFileExtension, CadstarPartsLibraryFileExtension, CadstarPcbFileExtension, CadstarSchematicFileExtension, type ConnectionGraphMap, type ConvertGraphToKiCadContext, type ConvertGraphToKiCadInput, CsvFileExtension, DEFAULT_PAPER_SIZE, DatabaseLibraryFileExtension,
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+
export { AllegroNetlistFileExtension, AltiumFootprintLibPathExtension, ArchiveFileExtension, BLOCK_PIN_GAP, BLOCK_PIN_TB_MARGIN, type BlockLabelPadding, type BlockSize, type BoxGeometry, CadstarFootprintLibPathExtension, CadstarNetlistFileExtension, CadstarPartsLibraryFileExtension, CadstarPcbFileExtension, CadstarSchematicFileExtension, type ConnectionGraphMap, type ConvertGraphToKiCadContext, type ConvertGraphToKiCadInput, CsvFileExtension, DEFAULT_PAPER_SIZE, DatabaseLibraryFileExtension, DesignRulesFileExtension, DrawingSheetFileExtension, DrillFileExtension, EagleFootprintLibPathExtension, EaglePcbFileExtension, EquFileExtension, FONT_SIZE, FootprintAssignmentFileExtension, FootprintPlaceFileExtension, GENERATOR_NAME, GENERATOR_VERSION, GRID_SIZE, GedaPcbFootprintLibFileExtension, GerberFileExtension, GerberFileExtensionsRegex, GerberJobFileExtension, GltfBinaryFileExtension, GraphConverter, HTTPLibraryFileExtension, HotkeyFileExtension, HtmlFileExtension, Ipc2581FileExtension, IpcD356FileExtension, JpegFileExtension, JsonFileExtension, KICAD_SCH_FRAME, KiCadFootprintFileExtension, KiCadFootprintLibPathExtension, KiCadPcbFileExtension, KiCadProjectArchive, KiCadSchematicFileExtension, KiCadSymbolLibFileExtension, type LabelPadding, Layout, LegacyFootprintLibPathExtension, LegacyPcbFileExtension, LegacyProjectFileExtension, LegacySchematicFileExtension, LegacySymbolDocumentFileExtension, LegacySymbolLibFileExtension, MacrosFileExtension, MarkdownFileExtension, NetListConverter, NetlistFileExtension, type NetlistProject, type NetlistToKicadContext, OrCadPcb2NetlistFileExtension, PAPER, PAPER_SIZE, PdfFileExtension, PngFileExtension, ProjectFileExtension, ProjectLocalSettingsFileExtension, ReportFileExtension, SCHEMATIC_PRINTER, SCH_VERSION, SVGFileExtension, SchematicSymbolFileExtension, type Size, SpecctraDsnFileExtension, SpecctraSessionFileExtension, SpiceFileExtension, StepFileAbrvExtension, StepFileExtension, StringFormatter, TextFileExtension, VrmlFileExtension, WIRE_PADDING, WorkbookFileExtension, XmlFileExtension, collect_sub_sheets, collect_sub_sheets_by_id, convert_graph_to_design_block, convert_graph_to_kicad_project, convert_graph_to_sheets, filterNullOrUndefined, gen_lib_gnd, gen_lib_vcc, gen_sch_gnd, gen_sch_vcc, get_power_pos, get_sch_default_drawing_sheet, tab };
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package/dist/index.d.ts
CHANGED
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@@ -1,5 +1,5 @@
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1
1
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import { VECTOR2, At, Color, ConnectionGraph, NL_NetList, BOX2 } from '@modular-circuit/electronics-model';
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2
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-
import { SCHEMATIC, PIN_DISPLAY_OPT, LIB_SYMBOL, Drawing, PIN_DEFINITION, SCH_LABEL, SCH_SYMBOL, SCH_LINE, PIN_INSTANCE, SCH_SHEET, SCH_SHEET_PIN, Effects, Justify, SCH_FIELD, Fill, Stroke, Project, IR_Graph, ModuleResolver, ModuleCircuit } from '@modular-circuit/ir';
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2
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+
import { SCHEMATIC, PIN_DISPLAY_OPT, LIB_SYMBOL, Drawing, PIN_DEFINITION, SCH_LABEL, SCH_SYMBOL, SCH_LINE, PIN_INSTANCE, SCH_SHEET, SCH_SHEET_PIN, Effects, Justify, SCH_FIELD, Fill, Stroke, Project, IR_Graph, DesignBlockContent, ModuleResolver, ModuleCircuit } from '@modular-circuit/ir';
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import { CG_SCHEMATIC, CONNECTION_GRAPH_BUILDER_CTX } from '@modular-circuit/perc';
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4
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declare function get_sch_default_drawing_sheet(): string;
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@@ -128,8 +128,12 @@ declare class NetListConverter {
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private convert_net_label;
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}
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+
declare function convert_graph_to_sheets(ctx: ConvertGraphToKiCadInput): Promise<Record<string, string>>;
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+
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declare function convert_graph_to_kicad_project(ctx: ConvertGraphToKiCadInput): Promise<Blob>;
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declare function convert_graph_to_design_block(ctx: ConvertGraphToKiCadInput): Promise<DesignBlockContent>;
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+
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declare const KiCadSymbolLibFileExtension = "kicad_sym";
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declare const SchematicSymbolFileExtension = "sym";
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declare const LegacySymbolLibFileExtension = "lib";
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@@ -463,20 +467,11 @@ declare class StringFormatter {
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append_quote(str: string): void;
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}
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interface NamedContent {
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filename: string;
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content: string;
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}
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interface DesignBlock {
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main_sch: string;
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sheets: NamedContent[];
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pcb?: NamedContent;
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}
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declare function collect_sub_sheets_by_id(module_ids: string[], module_resolver: ModuleResolver): Promise<{
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sheets: Record<string, string>;
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module_main_sheet: Record<string, string>;
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modules: Record<string, ModuleCircuit>;
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design_blocks:
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design_blocks: DesignBlockContent[];
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}>;
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declare const gen_lib_gnd: (value: string) => LIB_SYMBOL;
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@@ -487,4 +482,4 @@ declare const gen_sch_gnd: (value: string, pwr_number: number, port_id: string,
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declare const gen_sch_vcc: (value: string, pwr_number: number, port_id: string, position: VECTOR2) => SCH_SYMBOL;
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490
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-
export { AllegroNetlistFileExtension, AltiumFootprintLibPathExtension, ArchiveFileExtension, BLOCK_PIN_GAP, BLOCK_PIN_TB_MARGIN, type BlockLabelPadding, type BlockSize, type BoxGeometry, CadstarFootprintLibPathExtension, CadstarNetlistFileExtension, CadstarPartsLibraryFileExtension, CadstarPcbFileExtension, CadstarSchematicFileExtension, type ConnectionGraphMap, type ConvertGraphToKiCadContext, type ConvertGraphToKiCadInput, CsvFileExtension, DEFAULT_PAPER_SIZE, DatabaseLibraryFileExtension,
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485
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+
export { AllegroNetlistFileExtension, AltiumFootprintLibPathExtension, ArchiveFileExtension, BLOCK_PIN_GAP, BLOCK_PIN_TB_MARGIN, type BlockLabelPadding, type BlockSize, type BoxGeometry, CadstarFootprintLibPathExtension, CadstarNetlistFileExtension, CadstarPartsLibraryFileExtension, CadstarPcbFileExtension, CadstarSchematicFileExtension, type ConnectionGraphMap, type ConvertGraphToKiCadContext, type ConvertGraphToKiCadInput, CsvFileExtension, DEFAULT_PAPER_SIZE, DatabaseLibraryFileExtension, DesignRulesFileExtension, DrawingSheetFileExtension, DrillFileExtension, EagleFootprintLibPathExtension, EaglePcbFileExtension, EquFileExtension, FONT_SIZE, FootprintAssignmentFileExtension, FootprintPlaceFileExtension, GENERATOR_NAME, GENERATOR_VERSION, GRID_SIZE, GedaPcbFootprintLibFileExtension, GerberFileExtension, GerberFileExtensionsRegex, GerberJobFileExtension, GltfBinaryFileExtension, GraphConverter, HTTPLibraryFileExtension, HotkeyFileExtension, HtmlFileExtension, Ipc2581FileExtension, IpcD356FileExtension, JpegFileExtension, JsonFileExtension, KICAD_SCH_FRAME, KiCadFootprintFileExtension, KiCadFootprintLibPathExtension, KiCadPcbFileExtension, KiCadProjectArchive, KiCadSchematicFileExtension, KiCadSymbolLibFileExtension, type LabelPadding, Layout, LegacyFootprintLibPathExtension, LegacyPcbFileExtension, LegacyProjectFileExtension, LegacySchematicFileExtension, LegacySymbolDocumentFileExtension, LegacySymbolLibFileExtension, MacrosFileExtension, MarkdownFileExtension, NetListConverter, NetlistFileExtension, type NetlistProject, type NetlistToKicadContext, OrCadPcb2NetlistFileExtension, PAPER, PAPER_SIZE, PdfFileExtension, PngFileExtension, ProjectFileExtension, ProjectLocalSettingsFileExtension, ReportFileExtension, SCHEMATIC_PRINTER, SCH_VERSION, SVGFileExtension, SchematicSymbolFileExtension, type Size, SpecctraDsnFileExtension, SpecctraSessionFileExtension, SpiceFileExtension, StepFileAbrvExtension, StepFileExtension, StringFormatter, TextFileExtension, VrmlFileExtension, WIRE_PADDING, WorkbookFileExtension, XmlFileExtension, collect_sub_sheets, collect_sub_sheets_by_id, convert_graph_to_design_block, convert_graph_to_kicad_project, convert_graph_to_sheets, filterNullOrUndefined, gen_lib_gnd, gen_lib_vcc, gen_sch_gnd, gen_sch_vcc, get_power_pos, get_sch_default_drawing_sheet, tab };
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package/dist/index.js
CHANGED
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@@ -155,7 +155,9 @@ __export(index_exports, {
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XmlFileExtension: () => XmlFileExtension,
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collect_sub_sheets: () => collect_sub_sheets,
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collect_sub_sheets_by_id: () => collect_sub_sheets_by_id,
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convert_graph_to_design_block: () => convert_graph_to_design_block,
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convert_graph_to_kicad_project: () => convert_graph_to_kicad_project,
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convert_graph_to_sheets: () => convert_graph_to_sheets,
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filterNullOrUndefined: () => filterNullOrUndefined,
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gen_lib_gnd: () => gen_lib_gnd,
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gen_lib_vcc: () => gen_lib_vcc,
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@@ -313,8 +315,10 @@ async function collect_sub_sheets_by_id(module_ids, module_resolver) {
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module_main_sheet[k] = module_circuit.main;
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modules[k] = module_circuit;
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const design_block = {
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root: module_circuit.main,
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schematics: [],
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pcb: null,
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components: []
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};
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console.log(`Fetching ZIP archive for module ${id} from ${zip_archive_url.toString()}`);
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const zip_archive = await fetch(zip_archive_url).then((res) => res.arrayBuffer());
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@@ -327,10 +331,10 @@ async function collect_sub_sheets_by_id(module_ids, module_resolver) {
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continue;
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}
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sheets[filename] = content;
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design_block.
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design_block.schematics.push({ filename, content });
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} else if (name.endsWith(import_utils2.KICAD_PCB_FILE_EXT)) {
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const filename = (0, import_utils2.remove_filename_path_prefix)(name);
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design_block.pcb = { filename, content };
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design_block.pcb = { pcb: { filename, content } };
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}
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}
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design_blocks.push(design_block);
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@@ -2986,6 +2990,26 @@ async function convert_graph_to_kicad_project(ctx) {
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});
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return kicad_project.toZip();
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}
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// src/builder/graph_to_kicad/convert_graph_to_design_block.ts
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async function convert_graph_to_design_block(ctx) {
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const sheets = await convert_graph_to_sheets(ctx);
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2997
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const kicad_project = new KiCadProjectArchive(ctx.project.name, {
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...sheets
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});
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const design_block = {
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3001
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root: kicad_project.main_sch_name,
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pcb: null,
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components: [],
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schematics: Object.entries(sheets).map(([filename, content]) => {
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return {
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filename,
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content
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};
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})
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};
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return design_block;
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}
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// Annotate the CommonJS export names for ESM import in node:
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0 && (module.exports = {
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AllegroNetlistFileExtension,
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@@ -3069,7 +3093,9 @@ async function convert_graph_to_kicad_project(ctx) {
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XmlFileExtension,
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collect_sub_sheets,
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collect_sub_sheets_by_id,
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convert_graph_to_design_block,
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convert_graph_to_kicad_project,
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convert_graph_to_sheets,
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filterNullOrUndefined,
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gen_lib_gnd,
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gen_lib_vcc,
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package/dist/index.mjs
CHANGED
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@@ -200,8 +200,10 @@ async function collect_sub_sheets_by_id(module_ids, module_resolver) {
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module_main_sheet[k] = module_circuit.main;
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modules[k] = module_circuit;
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const design_block = {
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-
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-
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root: module_circuit.main,
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schematics: [],
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pcb: null,
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components: []
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};
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console.log(`Fetching ZIP archive for module ${id} from ${zip_archive_url.toString()}`);
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const zip_archive = await fetch(zip_archive_url).then((res) => res.arrayBuffer());
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@@ -214,10 +216,10 @@ async function collect_sub_sheets_by_id(module_ids, module_resolver) {
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continue;
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}
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sheets[filename] = content;
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design_block.
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design_block.schematics.push({ filename, content });
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} else if (name.endsWith(KICAD_PCB_FILE_EXT)) {
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const filename = remove_filename_path_prefix2(name);
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design_block.pcb = { filename, content };
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design_block.pcb = { pcb: { filename, content } };
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}
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}
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design_blocks.push(design_block);
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@@ -2887,6 +2889,26 @@ async function convert_graph_to_kicad_project(ctx) {
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});
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return kicad_project.toZip();
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}
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+
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+
// src/builder/graph_to_kicad/convert_graph_to_design_block.ts
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2894
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+
async function convert_graph_to_design_block(ctx) {
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2895
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+
const sheets = await convert_graph_to_sheets(ctx);
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2896
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+
const kicad_project = new KiCadProjectArchive(ctx.project.name, {
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2897
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...sheets
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});
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const design_block = {
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2900
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root: kicad_project.main_sch_name,
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2901
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+
pcb: null,
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2902
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components: [],
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2903
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schematics: Object.entries(sheets).map(([filename, content]) => {
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2904
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return {
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2905
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filename,
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content
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2907
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};
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2908
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})
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2909
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};
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2910
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return design_block;
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2911
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+
}
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2890
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export {
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2891
2913
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AllegroNetlistFileExtension,
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2892
2914
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AltiumFootprintLibPathExtension,
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@@ -2969,7 +2991,9 @@ export {
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2969
2991
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XmlFileExtension,
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2970
2992
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collect_sub_sheets,
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2971
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collect_sub_sheets_by_id,
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2994
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+
convert_graph_to_design_block,
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2972
2995
|
convert_graph_to_kicad_project,
|
|
2996
|
+
convert_graph_to_sheets,
|
|
2973
2997
|
filterNullOrUndefined,
|
|
2974
2998
|
gen_lib_gnd,
|
|
2975
2999
|
gen_lib_vcc,
|
package/package.json
CHANGED
|
@@ -1,6 +1,6 @@
|
|
|
1
1
|
{
|
|
2
2
|
"name": "@modular-circuit/transpiler",
|
|
3
|
-
"version": "0.1.
|
|
3
|
+
"version": "0.1.10",
|
|
4
4
|
"description": "Intermediate representation of the modular circuit",
|
|
5
5
|
"main": "./dist/index.js",
|
|
6
6
|
"module": "./dist/index.mjs",
|
|
@@ -31,8 +31,8 @@
|
|
|
31
31
|
"jszip": "^3.10.1",
|
|
32
32
|
"@modular-circuit/electronics-model": "0.1.1",
|
|
33
33
|
"@modular-circuit/ir": "0.1.3",
|
|
34
|
-
"@modular-circuit/
|
|
35
|
-
"@modular-circuit/
|
|
34
|
+
"@modular-circuit/utils": "0.1.2",
|
|
35
|
+
"@modular-circuit/perc": "0.1.4"
|
|
36
36
|
},
|
|
37
37
|
"scripts": {
|
|
38
38
|
"clean": "rimraf dist",
|