@modular-circuit/transpiler 0.0.109 → 0.1.0

package/dist/index.d.ts

@@ -0,0 +1,479 @@
+import { VECTOR2, At, Color, ConnectionGraph, NL_NetList, BOX2 } from '@modular-circuit/electronics-model';
+import { SCHEMATIC, PIN_DISPLAY_OPT, LIB_SYMBOL, Drawing, PIN_DEFINITION, SCH_LABEL, SCH_SYMBOL, SCH_LINE, PIN_INSTANCE, SCH_SHEET, SCH_SHEET_PIN, Effects, Justify, SCH_FIELD, Fill, Stroke, Project, IR_Graph, ModuleResolver, ModuleCircuit } from '@modular-circuit/ir';
+import { CG_SCHEMATIC, CONNECTION_GRAPH_BUILDER_CTX } from '@modular-circuit/perc';
+
+declare function get_sch_default_drawing_sheet(): string;
+
+declare class SCHEMATIC_PRINTER {
+    schematic(sch: SCHEMATIC): string;
+    power(power?: boolean): "" | "(power)";
+    pin_display_opt(opt?: {
+        pin_numbers?: PIN_DISPLAY_OPT;
+        pin_names?: PIN_DISPLAY_OPT;
+    }): string | undefined;
+    lib_symbol(lib_symbol: LIB_SYMBOL): string;
+    lib_children(libs?: LIB_SYMBOL[]): string;
+    pts(points: VECTOR2[]): string;
+    drawings(draws?: Drawing[]): string | undefined;
+    drawing(draw: Drawing): string;
+    pin_defs(defs?: PIN_DEFINITION[]): string | undefined;
+    pin_def(def: PIN_DEFINITION): string;
+    label(label: SCH_LABEL): string;
+    unit(c?: number): string;
+    sch_symbol(sch_symbol: SCH_SYMBOL): string;
+    wire(w: SCH_LINE): string;
+    lib_id(id?: string | null): string | undefined;
+    sch_symbol_pin(pin: PIN_INSTANCE): string;
+    sch_sheet(sheet: SCH_SHEET): string;
+    sch_sheet_pin(sheet_pin: SCH_SHEET_PIN): string;
+    at(pos: At): string;
+    uuid(id: string): string;
+    effects(e: Effects): string;
+    justify(justify?: Justify): string | undefined;
+    booleans(it: unknown): string | undefined;
+    fields(fields?: SCH_FIELD[]): string | undefined;
+    field(field: SCH_FIELD): string;
+    fill(f?: Partial<Fill>): string | undefined;
+    size(s: VECTOR2): string;
+    fields_autoplaced(): string;
+    stroke(s?: Stroke): string | undefined;
+    color(c?: Color): string | undefined;
+}
+
+interface ConvertGraphToKiCadInput extends Omit<CONNECTION_GRAPH_BUILDER_CTX, 'dependencies'> {
+    project: Project;
+    schematics: Record<string, IR_Graph>;
+}
+interface ConnectionGraphMap {
+    connection_graph: ConnectionGraph;
+    cg_schematics: Record<string, CG_SCHEMATIC>;
+}
+type ConvertGraphToKiCadContext = ConvertGraphToKiCadInput & ConnectionGraphMap;
+
+declare class GraphConverter {
+    private ctx;
+    constructor(ctx: ConnectionGraphMap);
+    convert_to_netlist(): NL_NetList;
+}
+
+interface NetlistProject {
+    author: string;
+    name: string;
+}
+interface NetlistToKicadContext {
+    project: NetlistProject;
+    netlist: NL_NetList;
+}
+
+declare const GRID_SIZE: number;
+declare const FONT_SIZE: number;
+declare function get_power_pos(pwr_number: number): {
+    x: number;
+    y: number;
+};
+declare const BLOCK_PIN_GAP: number;
+declare const BLOCK_PIN_TB_MARGIN: number;
+declare const WIRE_PADDING: number;
+interface LabelPadding {
+    l_side: number;
+    r_side: number;
+}
+interface BlockLabelPadding {
+    internal: LabelPadding;
+    outer: LabelPadding;
+    total_pin_num: number;
+}
+interface BoxGeometry {
+    box: BOX2;
+    bounding_box: BOX2;
+}
+interface BlockSize {
+    size: VECTOR2;
+    bounding_size: VECTOR2;
+    factor: BlockLabelPadding;
+    l_margin: number;
+    r_margin: number;
+}
+declare class Layout {
+    private block_geo;
+    private elk;
+    add_block(id: string, factor: BlockLabelPadding): void;
+    finalize(): Promise<Record<string, BOX2>>;
+    private calc_block_size;
+}
+
+declare class NetListConverter {
+    private ctx;
+    private block_calc;
+    private sheet_pwr_count;
+    private net_name;
+    private wires;
+    constructor(ctx: NetlistToKicadContext);
+    pin_is_connected(id: string): boolean;
+    get_pin_net_name(id: string): string;
+    convert_to_kicad(): Promise<Record<string, SCHEMATIC>>;
+    /**
+     * Convert a schematic to a kicad schematic
+     * @param name The name of the graph ,also the file name of the converted schematic
+     * @param schematic For net label , it will be reflected by the net name,
+     * no need to handle them before the other types of label are introduced, e.g. global or hierarchical
+     * @returns
+     */
+    private convert_sch;
+    private convert_hierarchical_label;
+    private convert_pwr_symbol;
+    private get_sheet_symbol_lb_padding;
+    private convert_sheet_symbol;
+    private convert_sheet_pin;
+    private convert_net_label;
+}
+
+declare function convert_graph_to_kicad_project(ctx: ConvertGraphToKiCadInput): Promise<Blob>;
+
+declare const KiCadSymbolLibFileExtension = "kicad_sym";
+declare const SchematicSymbolFileExtension = "sym";
+declare const LegacySymbolLibFileExtension = "lib";
+declare const LegacySymbolDocumentFileExtension = "dcm";
+declare const VrmlFileExtension = "wrl";
+declare const ProjectFileExtension = "kicad_pro";
+declare const LegacyProjectFileExtension = "pro";
+declare const ProjectLocalSettingsFileExtension = "kicad_prl";
+declare const LegacySchematicFileExtension = "sch";
+declare const CadstarSchematicFileExtension = "csa";
+declare const CadstarPartsLibraryFileExtension = "lib";
+declare const KiCadSchematicFileExtension = "kicad_sch";
+declare const SpiceFileExtension = "cir";
+declare const CadstarNetlistFileExtension = "frp";
+declare const OrCadPcb2NetlistFileExtension = "net";
+declare const NetlistFileExtension = "net";
+declare const AllegroNetlistFileExtension = "txt";
+declare const FootprintAssignmentFileExtension = "cmp";
+declare const GerberFileExtension = "gbr";
+declare const GerberJobFileExtension = "gbrjob";
+declare const HtmlFileExtension = "html";
+declare const EquFileExtension = "equ";
+declare const HotkeyFileExtension = "hotkeys";
+declare const DatabaseLibraryFileExtension = "kicad_dbl";
+declare const HTTPLibraryFileExtension = "kicad_httplib";
+declare const ArchiveFileExtension = "zip";
+declare const LegacyPcbFileExtension = "brd";
+declare const EaglePcbFileExtension = "brd";
+declare const CadstarPcbFileExtension = "cpa";
+declare const KiCadPcbFileExtension = "kicad_pcb";
+declare const DrawingSheetFileExtension = "kicad_wks";
+declare const DesignRulesFileExtension = "kicad_dru";
+declare const PdfFileExtension = "pdf";
+declare const MacrosFileExtension = "mcr";
+declare const DrillFileExtension = "drl";
+declare const SVGFileExtension = "svg";
+declare const ReportFileExtension = "rpt";
+declare const FootprintPlaceFileExtension = "pos";
+declare const KiCadFootprintLibPathExtension = "pretty";
+declare const LegacyFootprintLibPathExtension = "mod";
+declare const AltiumFootprintLibPathExtension = "PcbLib";
+declare const CadstarFootprintLibPathExtension = "cpa";
+declare const EagleFootprintLibPathExtension = "lbr";
+declare const GedaPcbFootprintLibFileExtension = "fp";
+declare const KiCadFootprintFileExtension = "kicad_mod";
+declare const SpecctraDsnFileExtension = "dsn";
+declare const SpecctraSessionFileExtension = "ses";
+declare const IpcD356FileExtension = "d356";
+declare const Ipc2581FileExtension = "xml";
+declare const WorkbookFileExtension = "wbk";
+declare const PngFileExtension = "png";
+declare const JpegFileExtension = "jpg";
+declare const TextFileExtension = "txt";
+declare const MarkdownFileExtension = "md";
+declare const CsvFileExtension = "csv";
+declare const XmlFileExtension = "xml";
+declare const JsonFileExtension = "json";
+declare const StepFileExtension = "step";
+declare const StepFileAbrvExtension = "stp";
+declare const GltfBinaryFileExtension = "glb";
+declare const GerberFileExtensionsRegex: RegExp;
+
+declare const KICAD_SCH_FRAME: string;
+declare class KiCadProjectArchive {
+    project_name: string;
+    sheets: Record<string, string>;
+    kicad_sym?: string;
+    fp_lib_table?: string;
+    layout_frame?: string;
+    pcb?: string;
+    sym_lib_table?: string;
+    get sch_frame(): string;
+    get kicad_prl(): {
+        board: {
+            active_layer: number;
+            active_layer_preset: string;
+            auto_track_width: boolean;
+            hidden_netclasses: never[];
+            hidden_nets: never[];
+            high_contrast_mode: number;
+            net_color_mode: number;
+            opacity: {
+                images: number;
+                pads: number;
+                tracks: number;
+                vias: number;
+                zones: number;
+            };
+            selection_filter: {
+                dimensions: boolean;
+                footprints: boolean;
+                graphics: boolean;
+                keepouts: boolean;
+                lockedItems: boolean;
+                otherItems: boolean;
+                pads: boolean;
+                text: boolean;
+                tracks: boolean;
+                vias: boolean;
+                zones: boolean;
+            };
+            visible_items: number[];
+            visible_layers: string;
+            zone_display_mode: number;
+        };
+        git: {
+            repo_password: string;
+            repo_type: string;
+            repo_username: string;
+            ssh_key: string;
+        };
+        meta: {
+            filename: string;
+            version: number;
+        };
+        project: {
+            files: never[];
+        };
+    };
+    get kicad_pro(): {
+        board: {
+            '3dviewports': never[];
+            ipc2581: {
+                dist: string;
+                distpn: string;
+                internal_id: string;
+                mfg: string;
+                mpn: string;
+            };
+            layer_presets: never[];
+            viewports: never[];
+        };
+        boards: never[];
+        cvpcb: {
+            equivalence_files: never[];
+        };
+        erc: {
+            erc_exclusions: never[];
+            meta: {
+                version: number;
+            };
+            pin_map: number[][];
+            rule_severities: {
+                bus_definition_conflict: string;
+                bus_entry_needed: string;
+                bus_to_bus_conflict: string;
+                bus_to_net_conflict: string;
+                conflicting_netclasses: string;
+                different_unit_footprint: string;
+                different_unit_net: string;
+                duplicate_reference: string;
+                duplicate_sheet_names: string;
+                endpoint_off_grid: string;
+                extra_units: string;
+                global_label_dangling: string;
+                hier_label_mismatch: string;
+                label_dangling: string;
+                lib_symbol_issues: string;
+                missing_bidi_pin: string;
+                missing_input_pin: string;
+                missing_power_pin: string;
+                missing_unit: string;
+                multiple_net_names: string;
+                net_not_bus_member: string;
+                no_connect_connected: string;
+                no_connect_dangling: string;
+                pin_not_connected: string;
+                pin_not_driven: string;
+                pin_to_pin: string;
+                power_pin_not_driven: string;
+                similar_labels: string;
+                simulation_model_issue: string;
+                unannotated: string;
+                unit_value_mismatch: string;
+                unresolved_variable: string;
+                wire_dangling: string;
+            };
+        };
+        libraries: {
+            pinned_footprint_libs: never[];
+            pinned_symbol_libs: never[];
+        };
+        meta: {
+            filename: string;
+            version: number;
+        };
+        net_settings: {
+            classes: {
+                bus_width: number;
+                clearance: number;
+                diff_pair_gap: number;
+                diff_pair_via_gap: number;
+                diff_pair_width: number;
+                line_style: number;
+                microvia_diameter: number;
+                microvia_drill: number;
+                name: string;
+                pcb_color: string;
+                schematic_color: string;
+                track_width: number;
+                via_diameter: number;
+                via_drill: number;
+                wire_width: number;
+            }[];
+            meta: {
+                version: number;
+            };
+            net_colors: null;
+            netclass_assignments: null;
+            netclass_patterns: never[];
+        };
+        pcbnew: {
+            last_paths: {
+                gencad: string;
+                idf: string;
+                netlist: string;
+                plot: string;
+                pos_files: string;
+                specctra_dsn: string;
+                step: string;
+                svg: string;
+                vrml: string;
+            };
+        };
+        schematic: {
+            annotate_start_num: number;
+            bom_export_filename: string;
+            bom_fmt_presets: never[];
+            bom_fmt_settings: {
+                field_delimiter: string;
+                keep_line_breaks: boolean;
+                keep_tabs: boolean;
+                name: string;
+                ref_delimiter: string;
+                ref_range_delimiter: string;
+                string_delimiter: string;
+            };
+            bom_presets: never[];
+            bom_settings: {
+                exclude_dnp: boolean;
+                fields_ordered: {
+                    group_by: boolean;
+                    label: string;
+                    name: string;
+                    show: boolean;
+                }[];
+                filter_string: string;
+                group_symbols: boolean;
+                name: string;
+                sort_asc: boolean;
+                sort_field: string;
+            };
+            connection_grid_size: number;
+            drawing: {
+                dashed_lines_dash_length_ratio: number;
+                dashed_lines_gap_length_ratio: number;
+                default_line_thickness: number;
+                default_text_size: number;
+                field_names: never[];
+                intersheets_ref_own_page: boolean;
+                intersheets_ref_prefix: string;
+                intersheets_ref_short: boolean;
+                intersheets_ref_show: boolean;
+                intersheets_ref_suffix: string;
+                junction_size_choice: number;
+                label_size_ratio: number;
+                operating_point_overlay_i_precision: number;
+                operating_point_overlay_i_range: string;
+                operating_point_overlay_v_precision: number;
+                operating_point_overlay_v_range: string;
+                overbar_offset_ratio: number;
+                pin_symbol_size: number;
+                text_offset_ratio: number;
+            };
+            legacy_lib_dir: string;
+            legacy_lib_list: never[];
+            meta: {
+                version: number;
+            };
+            net_format_name: string;
+            page_layout_descr_file: string;
+            plot_directory: string;
+            spice_current_sheet_as_root: boolean;
+            spice_external_command: string;
+            spice_model_current_sheet_as_root: boolean;
+            spice_save_all_currents: boolean;
+            spice_save_all_dissipations: boolean;
+            spice_save_all_voltages: boolean;
+            subpart_first_id: number;
+            subpart_id_separator: number;
+        };
+        sheets: never[];
+        text_variables: {};
+    };
+    constructor(project_name: string, sheets: Record<string, string>);
+    get_project_directive_file_name(ext: string): string;
+    toZip(): Promise<Blob>;
+}
+
+declare function collect_sub_sheets(dependencies: Record<string, string>, module_resolver: ModuleResolver): Promise<{
+    sheets: Record<string, string>;
+    module_main_sheet: Record<string, string>;
+    modules: Record<string, ModuleCircuit>;
+}>;
+
+interface Size {
+    height: number;
+    width: number;
+}
+declare const PAPER_SIZE: Record<string, Size>;
+declare const DEFAULT_PAPER_SIZE: Size;
+declare const GENERATOR_NAME = "modular_circuit";
+declare const SCH_VERSION = 20231120;
+declare const PAPER = "A4";
+declare const GENERATOR_VERSION = "8.0";
+
+declare function filterNullOrUndefined(originalMethod: unknown, _context: ClassMethodDecoratorContext): (this: unknown, ...args: unknown[]) => any;
+
+declare const tab = "\t";
+declare class StringFormatter {
+    private intend;
+    private content;
+    constructor(intend?: number);
+    toString(): string;
+    get intend_level(): number;
+    enter_scope(): void;
+    exit_scope(): void;
+    append(str: string): void;
+    append_line(str: string): void;
+    append_quote(str: string): void;
+}
+
+declare function collect_sub_sheets_by_id(module_ids: string[], module_resolver: ModuleResolver): Promise<{
+    sheets: Record<string, string>;
+    module_main_sheet: Record<string, string>;
+    modules: Record<string, ModuleCircuit>;
+}>;
+
+declare const gen_lib_gnd: (value: string) => LIB_SYMBOL;
+
+declare const gen_lib_vcc: (value: string) => LIB_SYMBOL;
+
+declare const gen_sch_gnd: (value: string, pwr_number: number, port_id: string, position: VECTOR2) => SCH_SYMBOL;
+
+declare const gen_sch_vcc: (value: string, pwr_number: number, port_id: string, position: VECTOR2) => SCH_SYMBOL;
+
+export { AllegroNetlistFileExtension, AltiumFootprintLibPathExtension, ArchiveFileExtension, BLOCK_PIN_GAP, BLOCK_PIN_TB_MARGIN, type BlockLabelPadding, type BlockSize, type BoxGeometry, CadstarFootprintLibPathExtension, CadstarNetlistFileExtension, CadstarPartsLibraryFileExtension, CadstarPcbFileExtension, CadstarSchematicFileExtension, type ConnectionGraphMap, type ConvertGraphToKiCadContext, type ConvertGraphToKiCadInput, CsvFileExtension, DEFAULT_PAPER_SIZE, DatabaseLibraryFileExtension, DesignRulesFileExtension, DrawingSheetFileExtension, DrillFileExtension, EagleFootprintLibPathExtension, EaglePcbFileExtension, EquFileExtension, FONT_SIZE, FootprintAssignmentFileExtension, FootprintPlaceFileExtension, GENERATOR_NAME, GENERATOR_VERSION, GRID_SIZE, GedaPcbFootprintLibFileExtension, GerberFileExtension, GerberFileExtensionsRegex, GerberJobFileExtension, GltfBinaryFileExtension, GraphConverter, HTTPLibraryFileExtension, HotkeyFileExtension, HtmlFileExtension, Ipc2581FileExtension, IpcD356FileExtension, JpegFileExtension, JsonFileExtension, KICAD_SCH_FRAME, KiCadFootprintFileExtension, KiCadFootprintLibPathExtension, KiCadPcbFileExtension, KiCadProjectArchive, KiCadSchematicFileExtension, KiCadSymbolLibFileExtension, type LabelPadding, Layout, LegacyFootprintLibPathExtension, LegacyPcbFileExtension, LegacyProjectFileExtension, LegacySchematicFileExtension, LegacySymbolDocumentFileExtension, LegacySymbolLibFileExtension, MacrosFileExtension, MarkdownFileExtension, NetListConverter, NetlistFileExtension, type NetlistProject, type NetlistToKicadContext, OrCadPcb2NetlistFileExtension, PAPER, PAPER_SIZE, PdfFileExtension, PngFileExtension, ProjectFileExtension, ProjectLocalSettingsFileExtension, ReportFileExtension, SCHEMATIC_PRINTER, SCH_VERSION, SVGFileExtension, SchematicSymbolFileExtension, type Size, SpecctraDsnFileExtension, SpecctraSessionFileExtension, SpiceFileExtension, StepFileAbrvExtension, StepFileExtension, StringFormatter, TextFileExtension, VrmlFileExtension, WIRE_PADDING, WorkbookFileExtension, XmlFileExtension, collect_sub_sheets, collect_sub_sheets_by_id, convert_graph_to_kicad_project, filterNullOrUndefined, gen_lib_gnd, gen_lib_vcc, gen_sch_gnd, gen_sch_vcc, get_power_pos, get_sch_default_drawing_sheet, tab };