@modular-circuit/perc 0.1.3 → 0.1.5

package/dist/index.d.mts

@@ -1,5 +1,5 @@
 import * as _modular_circuit_electronics_model from '@modular-circuit/electronics-model';
-import { VECTOR2, BOX2, ELECTRICAL_NODE, ELECTRICAL_PINTYPE, ConnectionSubgraph, ConnectionNodeMap, GS_SCH_SHEET_PATH, ConnectionGraph, CG_SHEET, NL_PowerSymbol, PowerShape, PowerSymbolPort, Connection, ConnectionNode, DigitalBidirBundle } from '@modular-circuit/electronics-model';
+import { VECTOR2, BOX2, ELECTRICAL_NODE, ELECTRICAL_PINTYPE, ConnectionSubgraph, ConnectionNodeMap, GS_SCH_SHEET_PATH, ConnectionGraph, CG_SHEET, NL_PowerSymbol, DigitalBidirBundle, PowerShape, PowerSymbolPort, Connection, ConnectionNode } from '@modular-circuit/electronics-model';
 import { SCH_ITEM, ModuleResolver, ModuleCircuit, IR_Graph } from '@modular-circuit/ir';
 import { PowerBase } from '@modular-circuit/ir/build/graph/pwr_base';
 import { CC_Visitor } from '@modular-circuit/utils';
@@ -431,12 +431,23 @@ interface CG_SCHEMATIC {
     sheets: CG_SHEET[];
     powers: NL_PowerSymbol[];
 }
+interface BundleInfo {
+    bundle: DigitalBidirBundle;
+    block_name: string;
+    circuit?: ModuleCircuit;
+}
 declare class IR_GRAPH_CONVERTER implements GRAPH_CONVERTER {
     private readonly circuits;
     private graph;
     private connection_node_map;
     private schematics;
+    private bundle_consumed_port_count;
+    private bundles;
     private reporter_context;
+    get_bundle_consumed_port_count(): {
+        bundle_consumed_port_count: Record<string, number>;
+        bundles: Record<string, BundleInfo>;
+    };
     get_report_context(): ERC_REPORTER_CONTEXT;
     constructor(circuits: Record<string, ModuleCircuit>);
     convert_to_graph(designs: Record<string, IR_Graph>): true | Error[];
@@ -453,23 +464,17 @@ declare class ConnectionGraphsBuilder implements CC_Visitor {
     private readonly connection_node_map;
     private net_count;
     private connection_graph;
-    private bundle_consumed_port_count;
-    private bundles;
     constructor(connection_node_map: ConnectionNodeMap);
     end_visit_component(cc: string[]): void;
     resolve_net_drive(nodes: ConnectionNode[], sub_graph: ConnectionSubgraph): void;
     get_connection_graph(): ConnectionGraph;
-    get_bundle_consumed_port_count(): {
-        bundle_consumed_port_count: Record<string, number>;
-        bundles: Record<string, DigitalBidirBundle>;
-    };
 }
 declare function build_connection_graph(ctx: CONNECTION_GRAPH_BUILDER_CTX): Promise<{
     connection_graph: ConnectionGraph;
     cg_schematics: Record<string, CG_SCHEMATIC>;
     bundle_consume_status: {
         bundle_consumed_port_count: Record<string, number>;
-        bundles: Record<string, DigitalBidirBundle>;
+        bundles: Record<string, BundleInfo>;
     };
     pin_name_table: Record<string, string>;
     pin_module_name_table: Record<string, string>;
@@ -484,10 +489,10 @@ declare function graph_ecr(ctx: Omit<ERC_INPUT, 'schematics'> & {
     cg_schematics: Record<string, CG_SCHEMATIC>;
     bundle_consume_status: {
         bundle_consumed_port_count: Record<string, number>;
-        bundles: Record<string, _modular_circuit_electronics_model.DigitalBidirBundle>;
+        bundles: Record<string, BundleInfo>;
     };
     pin_name_table: Record<string, string>;
     pin_module_name_table: Record<string, string>;
 }>;
 
-export { type ADT_AdjacencyList, type ADT_Graph, type CG_SCHEMATIC, CONNECTIONS_COUNT_EXCEEDS_BUNDLE_LIMIT, type CONNECTION_GRAPH_BUILDER_CTX, ConnectionGraphsBuilder, DEFAULT_ERC_SETTING, DEFAULT_PIN_MAP, DEFAULT_PP_ERROR_SEVERITY, DEFAULT_SEVERITY, DrivenPinTypes, DrivingPinTypes, ERCE_DRIVER_CONFLICT, ERCE_PIN_NOT_CONNECTED, ERCE_PIN_TO_PIN_ERROR, ERCE_T, ERCE_UNANNOTATED, type ERC_CONTEXT, type ERC_INPUT, type ERC_ITEM, type ERC_REPORT, type ERC_REPORTER_CONTEXT, ERC_SETTING, ERC_TESTER, type GRAPH_CONVERTER, IR_GRAPH_CONVERTER, MakerType, type MarkerBase, NetlistTester, PIN_COMPATIBILITY_MATRIX_TESTER, PIN_ERROR, type PIN_TO_PIN_TEST_CONTEXT, PP_DUPLICATED_SOURCES, PP_ERROR, PP_ILLEGAL_CONNECTION, PP_IMPEDANCE_SIGNAL_INTEGRITY, PP_INAPPROPRIATE_FUNC, PP_INCOMPATIBLE_DIGITAL_THRESHOLDS, PP_INCOMPATIBLE_SIGNAL_LEVELS, PP_INCOMPATIBLE_VOLTAGE_LEVELS, PP_INSUFFICIENT_DRIVER, PP_NOT_DRIVEN, PP_OVERCURRENT, PP_OVER_DRIVEN, PP_REQUIRES_CONNECTED_SOURCE_OR_BIDIR, PP_SIGNAL_LEVELS_NOT_CONTAINED_WITHIN_VOLTAGE, type ParameterPropagationTestContext, ParameterPropagationTester, PowerDrivingPinTypes, type RC_ITEM, type REPORT_ITEM, type SCH_ERC_ITEM, type SCH_MARKER, SEVERITY, build_connection_graph, fmt_erc_item_description, get_erc_severity, graph_ecr };
+export { type ADT_AdjacencyList, type ADT_Graph, type BundleInfo, type CG_SCHEMATIC, CONNECTIONS_COUNT_EXCEEDS_BUNDLE_LIMIT, type CONNECTION_GRAPH_BUILDER_CTX, ConnectionGraphsBuilder, DEFAULT_ERC_SETTING, DEFAULT_PIN_MAP, DEFAULT_PP_ERROR_SEVERITY, DEFAULT_SEVERITY, DrivenPinTypes, DrivingPinTypes, ERCE_DRIVER_CONFLICT, ERCE_PIN_NOT_CONNECTED, ERCE_PIN_TO_PIN_ERROR, ERCE_T, ERCE_UNANNOTATED, type ERC_CONTEXT, type ERC_INPUT, type ERC_ITEM, type ERC_REPORT, type ERC_REPORTER_CONTEXT, ERC_SETTING, ERC_TESTER, type GRAPH_CONVERTER, IR_GRAPH_CONVERTER, MakerType, type MarkerBase, NetlistTester, PIN_COMPATIBILITY_MATRIX_TESTER, PIN_ERROR, type PIN_TO_PIN_TEST_CONTEXT, PP_DUPLICATED_SOURCES, PP_ERROR, PP_ILLEGAL_CONNECTION, PP_IMPEDANCE_SIGNAL_INTEGRITY, PP_INAPPROPRIATE_FUNC, PP_INCOMPATIBLE_DIGITAL_THRESHOLDS, PP_INCOMPATIBLE_SIGNAL_LEVELS, PP_INCOMPATIBLE_VOLTAGE_LEVELS, PP_INSUFFICIENT_DRIVER, PP_NOT_DRIVEN, PP_OVERCURRENT, PP_OVER_DRIVEN, PP_REQUIRES_CONNECTED_SOURCE_OR_BIDIR, PP_SIGNAL_LEVELS_NOT_CONTAINED_WITHIN_VOLTAGE, type ParameterPropagationTestContext, ParameterPropagationTester, PowerDrivingPinTypes, type RC_ITEM, type REPORT_ITEM, type SCH_ERC_ITEM, type SCH_MARKER, SEVERITY, build_connection_graph, fmt_erc_item_description, get_erc_severity, graph_ecr };

package/dist/index.d.ts

@@ -1,5 +1,5 @@
 import * as _modular_circuit_electronics_model from '@modular-circuit/electronics-model';
-import { VECTOR2, BOX2, ELECTRICAL_NODE, ELECTRICAL_PINTYPE, ConnectionSubgraph, ConnectionNodeMap, GS_SCH_SHEET_PATH, ConnectionGraph, CG_SHEET, NL_PowerSymbol, PowerShape, PowerSymbolPort, Connection, ConnectionNode, DigitalBidirBundle } from '@modular-circuit/electronics-model';
+import { VECTOR2, BOX2, ELECTRICAL_NODE, ELECTRICAL_PINTYPE, ConnectionSubgraph, ConnectionNodeMap, GS_SCH_SHEET_PATH, ConnectionGraph, CG_SHEET, NL_PowerSymbol, DigitalBidirBundle, PowerShape, PowerSymbolPort, Connection, ConnectionNode } from '@modular-circuit/electronics-model';
 import { SCH_ITEM, ModuleResolver, ModuleCircuit, IR_Graph } from '@modular-circuit/ir';
 import { PowerBase } from '@modular-circuit/ir/build/graph/pwr_base';
 import { CC_Visitor } from '@modular-circuit/utils';
@@ -431,12 +431,23 @@ interface CG_SCHEMATIC {
     sheets: CG_SHEET[];
     powers: NL_PowerSymbol[];
 }
+interface BundleInfo {
+    bundle: DigitalBidirBundle;
+    block_name: string;
+    circuit?: ModuleCircuit;
+}
 declare class IR_GRAPH_CONVERTER implements GRAPH_CONVERTER {
     private readonly circuits;
     private graph;
     private connection_node_map;
     private schematics;
+    private bundle_consumed_port_count;
+    private bundles;
     private reporter_context;
+    get_bundle_consumed_port_count(): {
+        bundle_consumed_port_count: Record<string, number>;
+        bundles: Record<string, BundleInfo>;
+    };
     get_report_context(): ERC_REPORTER_CONTEXT;
     constructor(circuits: Record<string, ModuleCircuit>);
     convert_to_graph(designs: Record<string, IR_Graph>): true | Error[];
@@ -453,23 +464,17 @@ declare class ConnectionGraphsBuilder implements CC_Visitor {
     private readonly connection_node_map;
     private net_count;
     private connection_graph;
-    private bundle_consumed_port_count;
-    private bundles;
     constructor(connection_node_map: ConnectionNodeMap);
     end_visit_component(cc: string[]): void;
     resolve_net_drive(nodes: ConnectionNode[], sub_graph: ConnectionSubgraph): void;
     get_connection_graph(): ConnectionGraph;
-    get_bundle_consumed_port_count(): {
-        bundle_consumed_port_count: Record<string, number>;
-        bundles: Record<string, DigitalBidirBundle>;
-    };
 }
 declare function build_connection_graph(ctx: CONNECTION_GRAPH_BUILDER_CTX): Promise<{
     connection_graph: ConnectionGraph;
     cg_schematics: Record<string, CG_SCHEMATIC>;
     bundle_consume_status: {
         bundle_consumed_port_count: Record<string, number>;
-        bundles: Record<string, DigitalBidirBundle>;
+        bundles: Record<string, BundleInfo>;
     };
     pin_name_table: Record<string, string>;
     pin_module_name_table: Record<string, string>;
@@ -484,10 +489,10 @@ declare function graph_ecr(ctx: Omit<ERC_INPUT, 'schematics'> & {
     cg_schematics: Record<string, CG_SCHEMATIC>;
     bundle_consume_status: {
         bundle_consumed_port_count: Record<string, number>;
-        bundles: Record<string, _modular_circuit_electronics_model.DigitalBidirBundle>;
+        bundles: Record<string, BundleInfo>;
     };
     pin_name_table: Record<string, string>;
     pin_module_name_table: Record<string, string>;
 }>;
 
-export { type ADT_AdjacencyList, type ADT_Graph, type CG_SCHEMATIC, CONNECTIONS_COUNT_EXCEEDS_BUNDLE_LIMIT, type CONNECTION_GRAPH_BUILDER_CTX, ConnectionGraphsBuilder, DEFAULT_ERC_SETTING, DEFAULT_PIN_MAP, DEFAULT_PP_ERROR_SEVERITY, DEFAULT_SEVERITY, DrivenPinTypes, DrivingPinTypes, ERCE_DRIVER_CONFLICT, ERCE_PIN_NOT_CONNECTED, ERCE_PIN_TO_PIN_ERROR, ERCE_T, ERCE_UNANNOTATED, type ERC_CONTEXT, type ERC_INPUT, type ERC_ITEM, type ERC_REPORT, type ERC_REPORTER_CONTEXT, ERC_SETTING, ERC_TESTER, type GRAPH_CONVERTER, IR_GRAPH_CONVERTER, MakerType, type MarkerBase, NetlistTester, PIN_COMPATIBILITY_MATRIX_TESTER, PIN_ERROR, type PIN_TO_PIN_TEST_CONTEXT, PP_DUPLICATED_SOURCES, PP_ERROR, PP_ILLEGAL_CONNECTION, PP_IMPEDANCE_SIGNAL_INTEGRITY, PP_INAPPROPRIATE_FUNC, PP_INCOMPATIBLE_DIGITAL_THRESHOLDS, PP_INCOMPATIBLE_SIGNAL_LEVELS, PP_INCOMPATIBLE_VOLTAGE_LEVELS, PP_INSUFFICIENT_DRIVER, PP_NOT_DRIVEN, PP_OVERCURRENT, PP_OVER_DRIVEN, PP_REQUIRES_CONNECTED_SOURCE_OR_BIDIR, PP_SIGNAL_LEVELS_NOT_CONTAINED_WITHIN_VOLTAGE, type ParameterPropagationTestContext, ParameterPropagationTester, PowerDrivingPinTypes, type RC_ITEM, type REPORT_ITEM, type SCH_ERC_ITEM, type SCH_MARKER, SEVERITY, build_connection_graph, fmt_erc_item_description, get_erc_severity, graph_ecr };
+export { type ADT_AdjacencyList, type ADT_Graph, type BundleInfo, type CG_SCHEMATIC, CONNECTIONS_COUNT_EXCEEDS_BUNDLE_LIMIT, type CONNECTION_GRAPH_BUILDER_CTX, ConnectionGraphsBuilder, DEFAULT_ERC_SETTING, DEFAULT_PIN_MAP, DEFAULT_PP_ERROR_SEVERITY, DEFAULT_SEVERITY, DrivenPinTypes, DrivingPinTypes, ERCE_DRIVER_CONFLICT, ERCE_PIN_NOT_CONNECTED, ERCE_PIN_TO_PIN_ERROR, ERCE_T, ERCE_UNANNOTATED, type ERC_CONTEXT, type ERC_INPUT, type ERC_ITEM, type ERC_REPORT, type ERC_REPORTER_CONTEXT, ERC_SETTING, ERC_TESTER, type GRAPH_CONVERTER, IR_GRAPH_CONVERTER, MakerType, type MarkerBase, NetlistTester, PIN_COMPATIBILITY_MATRIX_TESTER, PIN_ERROR, type PIN_TO_PIN_TEST_CONTEXT, PP_DUPLICATED_SOURCES, PP_ERROR, PP_ILLEGAL_CONNECTION, PP_IMPEDANCE_SIGNAL_INTEGRITY, PP_INAPPROPRIATE_FUNC, PP_INCOMPATIBLE_DIGITAL_THRESHOLDS, PP_INCOMPATIBLE_SIGNAL_LEVELS, PP_INCOMPATIBLE_VOLTAGE_LEVELS, PP_INSUFFICIENT_DRIVER, PP_NOT_DRIVEN, PP_OVERCURRENT, PP_OVER_DRIVEN, PP_REQUIRES_CONNECTED_SOURCE_OR_BIDIR, PP_SIGNAL_LEVELS_NOT_CONTAINED_WITHIN_VOLTAGE, type ParameterPropagationTestContext, ParameterPropagationTester, PowerDrivingPinTypes, type RC_ITEM, type REPORT_ITEM, type SCH_ERC_ITEM, type SCH_MARKER, SEVERITY, build_connection_graph, fmt_erc_item_description, get_erc_severity, graph_ecr };

package/dist/index.js

@@ -1589,11 +1589,19 @@ var IR_GRAPH_CONVERTER = class {
     this.graph = {};
     this.connection_node_map = {};
     this.schematics = {};
+    this.bundle_consumed_port_count = {};
+    this.bundles = {};
     this.reporter_context = {
       pin_name_table: {},
       pin_module_name_table: {}
     };
   }
+  get_bundle_consumed_port_count() {
+    return {
+      bundle_consumed_port_count: this.bundle_consumed_port_count,
+      bundles: this.bundles
+    };
+  }
   get_report_context() {
     return this.reporter_context;
   }
@@ -1602,6 +1610,12 @@ var IR_GRAPH_CONVERTER = class {
     if (Object.keys(designs).length > 1) {
       throw new Error("Multiple designs are not supported");
     }
+    const handle_graph_node = (uuid, port_block_name, port_name, port) => {
+      this.add_node(uuid);
+      this.connection_node_map[uuid] = port;
+      this.reporter_context.pin_module_name_table[port.uuid] = port_block_name;
+      this.reporter_context.pin_name_table[port.uuid] = port_name;
+    };
     for (const [sch_name, design] of Object.entries(designs)) {
       this.schematics[sch_name] = { uuid: design.uuid ?? (0, import_utils.gen_uuid)(), sheets: [], powers: [] };
       for (const block of design.blocks ?? []) {
@@ -1609,7 +1623,7 @@ var IR_GRAPH_CONVERTER = class {
           const circuit = this.circuits[(0, import_ir.block_is_associated_with_concrete_module)(block.type) ? block.type : (0, import_utils.fmt_module_name)(block.type)];
           this.schematics[sch_name].sheets.push({
             uuid: block.uuid,
-            sheet_name: design.name ?? circuit.name,
+            sheet_name: circuit.name,
             sheet_file_name: circuit.main,
             ports: block.ports.map((p) => p.uuid)
           });
@@ -1624,38 +1638,47 @@ var IR_GRAPH_CONVERTER = class {
               };
             }
             const uuid = port.uuid;
-            this.add_node(uuid);
-            this.connection_node_map[uuid] = {
+            if (param.type === import_electronics_model8.PortType.DigitalBidirBundle) {
+              this.bundles[uuid] = {
+                bundle: param,
+                block_name: circuit.name,
+                circuit
+              };
+              continue;
+            }
+            handle_graph_node(uuid, circuit.name, port.name, {
               uuid,
               type: import_electronics_model8.ConnectionNodeType.Port,
               param,
               label_shapes: (0, import_utils.get_port_labels)(param, circuit)
-            };
-            this.reporter_context.pin_module_name_table[port.uuid] = circuit.name;
-            this.reporter_context.pin_name_table[port.uuid] = port.name;
+            });
           }
         } else {
-          const sheet_name = design.name ?? block.name;
+          const sheet_name = block.name;
           this.schematics[sch_name].sheets.push({
             uuid: block.uuid,
             sheet_name,
-            sheet_file_name: `${sheet_name}${import_utils.KICAD_SHC_FILE_EXT}`,
+            sheet_file_name: `${sheet_name}.${import_utils.KiCadSchematicFileExtension}`,
             ports: block.ports.map((p) => p.uuid)
           });
           for (const port of block.ports) {
             const param = port.port;
             const uuid = port.uuid;
-            this.add_node(uuid);
-            this.connection_node_map[uuid] = {
+            if (typeof port.port !== "string" && port.port.type === import_electronics_model8.PortType.DigitalBidirBundle) {
+              this.bundles[uuid] = {
+                bundle: port.port,
+                block_name: sheet_name
+              };
+              continue;
+            }
+            handle_graph_node(uuid, sheet_name, typeof port.port === "string" ? port.port : port.port.name, {
               uuid,
               type: import_electronics_model8.ConnectionNodeType.Port,
               param: typeof param === "string" ? {
                 type: import_electronics_model8.PortType.Passive,
                 name: port.port
               } : param
-            };
-            this.reporter_context.pin_module_name_table[port.uuid] = sheet_name;
-            this.reporter_context.pin_name_table[port.uuid] = typeof port.port === "string" ? port.port : port.port.name;
+            });
           }
         }
       }
@@ -1701,10 +1724,47 @@ var IR_GRAPH_CONVERTER = class {
         this.add_node(uuid);
         this.connection_node_map[uuid] = { uuid, type: import_electronics_model8.ConnectionNodeType.Graphics };
       }
-      for (const connection of design.wires ?? []) {
-        const uuid = connection.uuid;
-        this.add_connection(connection.from, connection.to);
-        this.connection_node_map[uuid] = { uuid, type: import_electronics_model8.ConnectionNodeType.Graphics };
+      const handel_wire_instance = (abstract_or_actual_wire, actual_wire_id) => {
+        this.add_connection(abstract_or_actual_wire.from, abstract_or_actual_wire.to);
+        this.connection_node_map[abstract_or_actual_wire.uuid] = {
+          uuid: actual_wire_id,
+          type: import_electronics_model8.ConnectionNodeType.Graphics
+        };
+      };
+      const handel_bundle_connection = (bundle_id) => {
+        const uuid = (0, import_utils.gen_uuid)();
+        const bundle_info = this.bundles[bundle_id];
+        const consumed_count = bundle_id in this.bundle_consumed_port_count ? this.bundle_consumed_port_count[bundle_id] : 0;
+        this.bundle_consumed_port_count[bundle_id] = consumed_count + 1;
+        let labels_shapes = void 0;
+        if (bundle_info.circuit) labels_shapes = (0, import_utils.get_port_labels)(bundle_info.bundle, bundle_info.circuit);
+        const label = bundle_info.bundle.labels_associated[consumed_count] ?? `${bundle_info.bundle.name}-${consumed_count}`;
+        const label_shape = labels_shapes?.[label];
+        handle_graph_node(uuid, bundle_info.block_name, bundle_info.bundle.name, {
+          type: import_electronics_model8.ConnectionNodeType.Port,
+          label_shapes: label_shape ? { [label]: label_shape } : void 0,
+          param: {
+            ...{
+              ...bundle_info.bundle,
+              labels_associated: void 0,
+              type: import_electronics_model8.PortType.DigitalBidir,
+              label_associated: label
+            }
+          },
+          uuid
+        });
+        return uuid;
+      };
+      for (const actual_wire of design.wires ?? []) {
+        const actual_wire_id = actual_wire.uuid;
+        const connection = { ...actual_wire };
+        if (connection.from in this.bundles) {
+          connection.from = handel_bundle_connection(connection.from);
+        }
+        if (connection.to in this.bundles) {
+          connection.to = handel_bundle_connection(connection.to);
+        }
+        handel_wire_instance(connection, actual_wire_id);
       }
     }
     return errors.length ? errors : true;
@@ -1780,8 +1840,6 @@ var ConnectionGraphsBuilder = class {
   constructor(connection_node_map) {
     this.connection_node_map = connection_node_map;
     this.net_count = 0;
-    this.bundle_consumed_port_count = {};
-    this.bundles = {};
     this.connection_graph = {
       subgraphs: []
     };
@@ -1790,27 +1848,7 @@ var ConnectionGraphsBuilder = class {
     const sub_graph = {};
     sub_graph.is_global_pwr = false;
     sub_graph.is_isolated = cc.length < 2;
-    const nodes = cc.map((id) => {
-      const node = this.connection_node_map[id];
-      if (node?.type === import_electronics_model10.ConnectionNodeType.Port) {
-        const port = node.param;
-        if (port.type === import_electronics_model10.PortType.DigitalBidirBundle) {
-          const consumed_count = id in this.bundle_consumed_port_count ? this.bundle_consumed_port_count[id] : 0;
-          this.bundle_consumed_port_count[id] = consumed_count + 1;
-          this.bundles[id] = port;
-          const labels = port.labels_associated;
-          return {
-            ...node,
-            param: {
-              ...node.param,
-              type: import_electronics_model10.PortType.DigitalBidir,
-              label_associated: labels[consumed_count] ?? `${node.param.name}-${consumed_count}`
-            }
-          };
-        }
-      }
-      return node;
-    });
+    const nodes = cc.map((id) => this.connection_node_map[id]);
     sub_graph.nodes = nodes;
     this.resolve_net_drive(nodes, sub_graph);
     this.connection_graph.subgraphs.push(sub_graph);
@@ -1869,12 +1907,6 @@ var ConnectionGraphsBuilder = class {
   get_connection_graph() {
     return this.connection_graph;
   }
-  get_bundle_consumed_port_count() {
-    return {
-      bundle_consumed_port_count: this.bundle_consumed_port_count,
-      bundles: this.bundles
-    };
-  }
 };
 async function build_connection_graph(ctx) {
   const converter = new IR_GRAPH_CONVERTER(await get_dependent_modules_definition(ctx));
@@ -1886,7 +1918,7 @@ async function build_connection_graph(ctx) {
     ...converter.get_report_context(),
     connection_graph: cc_builder.get_connection_graph(),
     cg_schematics: converter.get_schematics(),
-    bundle_consume_status: cc_builder.get_bundle_consumed_port_count()
+    bundle_consume_status: converter.get_bundle_consumed_port_count()
   };
 }
 
@@ -1898,7 +1930,8 @@ async function graph_ecr(ctx) {
   };
   const connection_graph = await build_connection_graph(ctx);
   for (const [port_id, count] of Object.entries(connection_graph.bundle_consume_status.bundle_consumed_port_count)) {
-    const bundle = connection_graph.bundle_consume_status.bundles[port_id];
+    const bundle_info = connection_graph.bundle_consume_status.bundles[port_id];
+    const bundle = bundle_info.bundle;
     if (Array.isArray(bundle.labels_associated) && count > bundle.labels_associated.length) {
       erc_report.erc_errors.push(CONNECTIONS_COUNT_EXCEEDS_BUNDLE_LIMIT(port_id));
     } else {

package/dist/index.mjs

@@ -1546,12 +1546,12 @@ import {
   block_is_associated_with_concrete_module
 } from "@modular-circuit/ir";
 import {
-  KICAD_SHC_FILE_EXT,
   deep_copy,
   fmt_module_name,
   gen_uuid,
   get_circuit_ports,
-  get_port_labels
+  get_port_labels,
+  KiCadSchematicFileExtension
 } from "@modular-circuit/utils";
 var IR_GRAPH_CONVERTER = class {
   constructor(circuits) {
@@ -1559,11 +1559,19 @@ var IR_GRAPH_CONVERTER = class {
     this.graph = {};
     this.connection_node_map = {};
     this.schematics = {};
+    this.bundle_consumed_port_count = {};
+    this.bundles = {};
     this.reporter_context = {
       pin_name_table: {},
       pin_module_name_table: {}
     };
   }
+  get_bundle_consumed_port_count() {
+    return {
+      bundle_consumed_port_count: this.bundle_consumed_port_count,
+      bundles: this.bundles
+    };
+  }
   get_report_context() {
     return this.reporter_context;
   }
@@ -1572,6 +1580,12 @@ var IR_GRAPH_CONVERTER = class {
     if (Object.keys(designs).length > 1) {
       throw new Error("Multiple designs are not supported");
     }
+    const handle_graph_node = (uuid, port_block_name, port_name, port) => {
+      this.add_node(uuid);
+      this.connection_node_map[uuid] = port;
+      this.reporter_context.pin_module_name_table[port.uuid] = port_block_name;
+      this.reporter_context.pin_name_table[port.uuid] = port_name;
+    };
     for (const [sch_name, design] of Object.entries(designs)) {
       this.schematics[sch_name] = { uuid: design.uuid ?? gen_uuid(), sheets: [], powers: [] };
       for (const block of design.blocks ?? []) {
@@ -1579,7 +1593,7 @@ var IR_GRAPH_CONVERTER = class {
           const circuit = this.circuits[block_is_associated_with_concrete_module(block.type) ? block.type : fmt_module_name(block.type)];
           this.schematics[sch_name].sheets.push({
             uuid: block.uuid,
-            sheet_name: design.name ?? circuit.name,
+            sheet_name: circuit.name,
             sheet_file_name: circuit.main,
             ports: block.ports.map((p) => p.uuid)
           });
@@ -1594,38 +1608,47 @@ var IR_GRAPH_CONVERTER = class {
               };
             }
             const uuid = port.uuid;
-            this.add_node(uuid);
-            this.connection_node_map[uuid] = {
+            if (param.type === PortType3.DigitalBidirBundle) {
+              this.bundles[uuid] = {
+                bundle: param,
+                block_name: circuit.name,
+                circuit
+              };
+              continue;
+            }
+            handle_graph_node(uuid, circuit.name, port.name, {
               uuid,
               type: ConnectionNodeType3.Port,
               param,
               label_shapes: get_port_labels(param, circuit)
-            };
-            this.reporter_context.pin_module_name_table[port.uuid] = circuit.name;
-            this.reporter_context.pin_name_table[port.uuid] = port.name;
+            });
           }
         } else {
-          const sheet_name = design.name ?? block.name;
+          const sheet_name = block.name;
           this.schematics[sch_name].sheets.push({
             uuid: block.uuid,
             sheet_name,
-            sheet_file_name: `${sheet_name}${KICAD_SHC_FILE_EXT}`,
+            sheet_file_name: `${sheet_name}.${KiCadSchematicFileExtension}`,
             ports: block.ports.map((p) => p.uuid)
           });
           for (const port of block.ports) {
             const param = port.port;
             const uuid = port.uuid;
-            this.add_node(uuid);
-            this.connection_node_map[uuid] = {
+            if (typeof port.port !== "string" && port.port.type === PortType3.DigitalBidirBundle) {
+              this.bundles[uuid] = {
+                bundle: port.port,
+                block_name: sheet_name
+              };
+              continue;
+            }
+            handle_graph_node(uuid, sheet_name, typeof port.port === "string" ? port.port : port.port.name, {
               uuid,
               type: ConnectionNodeType3.Port,
               param: typeof param === "string" ? {
                 type: PortType3.Passive,
                 name: port.port
               } : param
-            };
-            this.reporter_context.pin_module_name_table[port.uuid] = sheet_name;
-            this.reporter_context.pin_name_table[port.uuid] = typeof port.port === "string" ? port.port : port.port.name;
+            });
           }
         }
       }
@@ -1671,10 +1694,47 @@ var IR_GRAPH_CONVERTER = class {
         this.add_node(uuid);
         this.connection_node_map[uuid] = { uuid, type: ConnectionNodeType3.Graphics };
       }
-      for (const connection of design.wires ?? []) {
-        const uuid = connection.uuid;
-        this.add_connection(connection.from, connection.to);
-        this.connection_node_map[uuid] = { uuid, type: ConnectionNodeType3.Graphics };
+      const handel_wire_instance = (abstract_or_actual_wire, actual_wire_id) => {
+        this.add_connection(abstract_or_actual_wire.from, abstract_or_actual_wire.to);
+        this.connection_node_map[abstract_or_actual_wire.uuid] = {
+          uuid: actual_wire_id,
+          type: ConnectionNodeType3.Graphics
+        };
+      };
+      const handel_bundle_connection = (bundle_id) => {
+        const uuid = gen_uuid();
+        const bundle_info = this.bundles[bundle_id];
+        const consumed_count = bundle_id in this.bundle_consumed_port_count ? this.bundle_consumed_port_count[bundle_id] : 0;
+        this.bundle_consumed_port_count[bundle_id] = consumed_count + 1;
+        let labels_shapes = void 0;
+        if (bundle_info.circuit) labels_shapes = get_port_labels(bundle_info.bundle, bundle_info.circuit);
+        const label = bundle_info.bundle.labels_associated[consumed_count] ?? `${bundle_info.bundle.name}-${consumed_count}`;
+        const label_shape = labels_shapes?.[label];
+        handle_graph_node(uuid, bundle_info.block_name, bundle_info.bundle.name, {
+          type: ConnectionNodeType3.Port,
+          label_shapes: label_shape ? { [label]: label_shape } : void 0,
+          param: {
+            ...{
+              ...bundle_info.bundle,
+              labels_associated: void 0,
+              type: PortType3.DigitalBidir,
+              label_associated: label
+            }
+          },
+          uuid
+        });
+        return uuid;
+      };
+      for (const actual_wire of design.wires ?? []) {
+        const actual_wire_id = actual_wire.uuid;
+        const connection = { ...actual_wire };
+        if (connection.from in this.bundles) {
+          connection.from = handel_bundle_connection(connection.from);
+        }
+        if (connection.to in this.bundles) {
+          connection.to = handel_bundle_connection(connection.to);
+        }
+        handel_wire_instance(connection, actual_wire_id);
       }
     }
     return errors.length ? errors : true;
@@ -1717,7 +1777,6 @@ var IR_GRAPH_CONVERTER = class {
 import {
   ConnectionNodeType as ConnectionNodeType4,
   PRIORITY,
-  PortType as PortType4,
   get_connection_node_priority
 } from "@modular-circuit/electronics-model";
 import { test_connected_components } from "@modular-circuit/utils";
@@ -1758,8 +1817,6 @@ var ConnectionGraphsBuilder = class {
   constructor(connection_node_map) {
     this.connection_node_map = connection_node_map;
     this.net_count = 0;
-    this.bundle_consumed_port_count = {};
-    this.bundles = {};
     this.connection_graph = {
       subgraphs: []
     };
@@ -1768,27 +1825,7 @@ var ConnectionGraphsBuilder = class {
     const sub_graph = {};
     sub_graph.is_global_pwr = false;
     sub_graph.is_isolated = cc.length < 2;
-    const nodes = cc.map((id) => {
-      const node = this.connection_node_map[id];
-      if (node?.type === ConnectionNodeType4.Port) {
-        const port = node.param;
-        if (port.type === PortType4.DigitalBidirBundle) {
-          const consumed_count = id in this.bundle_consumed_port_count ? this.bundle_consumed_port_count[id] : 0;
-          this.bundle_consumed_port_count[id] = consumed_count + 1;
-          this.bundles[id] = port;
-          const labels = port.labels_associated;
-          return {
-            ...node,
-            param: {
-              ...node.param,
-              type: PortType4.DigitalBidir,
-              label_associated: labels[consumed_count] ?? `${node.param.name}-${consumed_count}`
-            }
-          };
-        }
-      }
-      return node;
-    });
+    const nodes = cc.map((id) => this.connection_node_map[id]);
     sub_graph.nodes = nodes;
     this.resolve_net_drive(nodes, sub_graph);
     this.connection_graph.subgraphs.push(sub_graph);
@@ -1847,12 +1884,6 @@ var ConnectionGraphsBuilder = class {
   get_connection_graph() {
     return this.connection_graph;
   }
-  get_bundle_consumed_port_count() {
-    return {
-      bundle_consumed_port_count: this.bundle_consumed_port_count,
-      bundles: this.bundles
-    };
-  }
 };
 async function build_connection_graph(ctx) {
   const converter = new IR_GRAPH_CONVERTER(await get_dependent_modules_definition(ctx));
@@ -1864,7 +1895,7 @@ async function build_connection_graph(ctx) {
     ...converter.get_report_context(),
     connection_graph: cc_builder.get_connection_graph(),
     cg_schematics: converter.get_schematics(),
-    bundle_consume_status: cc_builder.get_bundle_consumed_port_count()
+    bundle_consume_status: converter.get_bundle_consumed_port_count()
   };
 }
 
@@ -1876,7 +1907,8 @@ async function graph_ecr(ctx) {
   };
   const connection_graph = await build_connection_graph(ctx);
   for (const [port_id, count] of Object.entries(connection_graph.bundle_consume_status.bundle_consumed_port_count)) {
-    const bundle = connection_graph.bundle_consume_status.bundles[port_id];
+    const bundle_info = connection_graph.bundle_consume_status.bundles[port_id];
+    const bundle = bundle_info.bundle;
     if (Array.isArray(bundle.labels_associated) && count > bundle.labels_associated.length) {
       erc_report.erc_errors.push(CONNECTIONS_COUNT_EXCEEDS_BUNDLE_LIMIT(port_id));
     } else {

package/package.json

@@ -1,6 +1,6 @@
 {
   "name": "@modular-circuit/perc",
-  "version": "0.1.3",
+  "version": "0.1.5",
   "description": "Programmable Electronic Circuit Check",
   "main": "./dist/index.js",
   "module": "./dist/index.mjs",
@@ -27,8 +27,8 @@
   },
   "dependencies": {
     "@modular-circuit/electronics-model": "0.1.1",
-    "@modular-circuit/ir": "0.1.2",
-    "@modular-circuit/utils": "0.1.2"
+    "@modular-circuit/ir": "0.1.5",
+    "@modular-circuit/utils": "0.1.5"
   },
   "scripts": {
     "clean": "rimraf dist",