@microbit/microbit-connection 0.9.0-apps.alpha.16 → 0.9.0-apps.alpha.17

package/build/esm/usb/arm-debug.test.js

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+import { beforeEach, describe, expect, it, vi } from "vitest";
+import { DeviceError } from "../device.js";
+import { ConsoleLogging } from "../logging.js";
+import { ArmDebugSwd, waitFor } from "./arm-debug.js";
+import { AP, DapResponseMismatchError, DP, READ, WRITE, } from "./cmsis-dap.js";
+// ---------------------------------------------------------------------------
+// Mock DAP
+// ---------------------------------------------------------------------------
+/**
+ * Creates a mock Dap that records transfer calls and returns configurable
+ * values. By default all methods resolve successfully.
+ *
+ * Read operations auto-respond from a register map (keyed by "port:register")
+ * when no queued results are available, making tests resilient to changes in
+ * the number or ordering of internal transfer calls.
+ */
+function createMockDap() {
+    // Track all transfer calls for assertions
+    const transferCalls = [];
+    // Queue of return values for transfer() — takes priority over registers.
+    const transferResults = [];
+    // Queue of return values for transferBlockRead()
+    const blockReadResults = [];
+    // Register map for auto-responding to reads when the queue is empty.
+    const registers = new Map();
+    let _isOpen = false;
+    const mock = {
+        get isOpen() {
+            return _isOpen;
+        },
+        blockSize: 59, // same as real CmsisDapUsb (64 - 4 - 1)
+        transferCalls,
+        registers,
+        queueTransferResult(...values) {
+            transferResults.push(new Uint32Array(values));
+        },
+        queueBlockReadResult(...values) {
+            blockReadResults.push(new Uint32Array(values));
+        },
+        open: vi.fn(async () => {
+            _isOpen = true;
+        }),
+        close: vi.fn(async () => {
+            _isOpen = false;
+        }),
+        send: vi.fn(async () => new DataView(new ArrayBuffer(64))),
+        clearAbort: vi.fn(async () => { }),
+        swjSequence: vi.fn(async () => { }),
+        swjClock: vi.fn(async () => { }),
+        connect: vi.fn(async () => { }),
+        disconnect: vi.fn(async () => { }),
+        configureTransfer: vi.fn(async () => { }),
+        drainStaleResponses: vi.fn(async () => { }),
+        transfer: vi.fn(async (ops) => {
+            transferCalls.push([...ops]);
+            if (transferResults.length > 0) {
+                return transferResults.shift();
+            }
+            // Auto-respond: return values for READ ops from the register map.
+            const readValues = [];
+            for (const op of ops) {
+                if (op.mode === READ) {
+                    readValues.push(registers.get(`${op.port}:${op.register}`) ?? 0);
+                }
+            }
+            return new Uint32Array(readValues);
+        }),
+        transferBlockRead: vi.fn(async () => {
+            return blockReadResults.shift() ?? new Uint32Array(0);
+        }),
+        transferBlockWrite: vi.fn(async () => { }),
+    };
+    return mock;
+}
+// CTRL/STAT power-up ACK bits (must match arm-debug.ts constants)
+const CSYSPWRUPACK = 1 << 31;
+const CDBGPWRUPACK = 1 << 29;
+const POWER_UP_ACK = (CSYSPWRUPACK | CDBGPWRUPACK) >>> 0;
+// AP registers
+const AP_DRW = 0x0c;
+const logging = new ConsoleLogging();
+// DP registers (matching arm-debug.ts constants)
+const DP_DPIDR = 0x0;
+const DP_CTRL_STAT = 0x4;
+// ---------------------------------------------------------------------------
+// Helpers
+// ---------------------------------------------------------------------------
+/**
+ * Set up register map values so the SWD connect sequence succeeds.
+ * Unlike a queue-based approach, this is resilient to changes in the
+ * number or ordering of internal transfer calls during connect.
+ */
+function setupConnectRegisters(dap) {
+    dap.registers.set(`${DP}:${DP_DPIDR}`, 0x0bb11477);
+    dap.registers.set(`${DP}:${DP_CTRL_STAT}`, POWER_UP_ACK);
+}
+// ---------------------------------------------------------------------------
+// Tests
+// ---------------------------------------------------------------------------
+describe("ArmDebugSwd", () => {
+    let dap;
+    let adi;
+    beforeEach(() => {
+        dap = createMockDap();
+        adi = new ArmDebugSwd(dap, logging);
+    });
+    describe("connect", () => {
+        it("runs the SWD init sequence", async () => {
+            setupConnectRegisters(dap);
+            await adi.connect();
+            // Transport opened
+            expect(dap.open).toHaveBeenCalled();
+            // SWD protocol setup
+            expect(dap.swjClock).toHaveBeenCalledWith(10_000_000);
+            expect(dap.connect).toHaveBeenCalled();
+            expect(dap.configureTransfer).toHaveBeenCalledWith(0, 100, 0);
+            // 4 SWJ sequences (line reset, SWD select, line reset, idle)
+            expect(dap.swjSequence).toHaveBeenCalledTimes(4);
+            // DP register operations happened
+            expect(dap.transfer).toHaveBeenCalled();
+        });
+        it("skips if already connected", async () => {
+            setupConnectRegisters(dap);
+            await adi.connect();
+            vi.mocked(dap.open).mockClear();
+            await adi.connect();
+            expect(dap.open).not.toHaveBeenCalled();
+        });
+        it("retries on DapResponseMismatchError", async () => {
+            // First attempt: swjClock throws mismatch
+            vi.mocked(dap.swjClock).mockRejectedValueOnce(new DapResponseMismatchError(0x11, 0x05));
+            // clearAbort on the failed attempt
+            vi.mocked(dap.clearAbort).mockResolvedValueOnce(undefined);
+            // Second attempt succeeds
+            setupConnectRegisters(dap);
+            await adi.connect();
+            expect(dap.drainStaleResponses).toHaveBeenCalledTimes(1);
+            expect(dap.swjClock).toHaveBeenCalledTimes(2);
+        });
+        it("throws after exhausting retries", async () => {
+            vi.mocked(dap.swjClock).mockRejectedValue(new DapResponseMismatchError(0x11, 0x05));
+            await expect(adi.connect(2)).rejects.toThrow(DapResponseMismatchError);
+            expect(dap.drainStaleResponses).toHaveBeenCalledTimes(1);
+        });
+        it("rethrows non-mismatch errors immediately", async () => {
+            vi.mocked(dap.swjClock).mockRejectedValueOnce(new Error("USB gone"));
+            await expect(adi.connect()).rejects.toThrow("USB gone");
+            expect(dap.drainStaleResponses).not.toHaveBeenCalled();
+        });
+    });
+    describe("disconnect", () => {
+        it("disconnects and closes transport", async () => {
+            setupConnectRegisters(dap);
+            await adi.connect();
+            await adi.disconnect();
+            expect(dap.disconnect).toHaveBeenCalled();
+            expect(dap.close).toHaveBeenCalled();
+        });
+        it("is a no-op if not connected", async () => {
+            await adi.disconnect();
+            expect(dap.disconnect).not.toHaveBeenCalled();
+            expect(dap.close).not.toHaveBeenCalled();
+        });
+        it("falls back to clearAbort if disconnect fails", async () => {
+            setupConnectRegisters(dap);
+            await adi.connect();
+            vi.mocked(dap.disconnect).mockRejectedValueOnce(new Error("fail"));
+            await adi.disconnect();
+            expect(dap.clearAbort).toHaveBeenCalled();
+            expect(dap.close).toHaveBeenCalled();
+        });
+    });
+    describe("reinit", () => {
+        it("resets state and reconnects without closing", async () => {
+            setupConnectRegisters(dap);
+            await adi.connect();
+            vi.mocked(dap.open).mockClear();
+            vi.mocked(dap.close).mockClear();
+            // reinit calls connectOnce which needs the full sequence
+            setupConnectRegisters(dap);
+            await adi.reinit();
+            // open is called again (connectOnce opens transport)
+            expect(dap.open).toHaveBeenCalled();
+            // close was NOT called (reinit doesn't close)
+            expect(dap.close).not.toHaveBeenCalled();
+        });
+    });
+    describe("readMem32 / writeMem32", () => {
+        beforeEach(async () => {
+            setupConnectRegisters(dap);
+            await adi.connect();
+            dap.transferCalls.length = 0;
+        });
+        it("reads a 32-bit value from memory", async () => {
+            dap.queueTransferResult(0xdeadbeef);
+            const value = await adi.readMem32(0x10000010);
+            expect(value).toBe(0xdeadbeef);
+            // Should have generated ops for CSW, TAR, and DRW read
+            const ops = dap.transferCalls[0];
+            expect(ops.some((op) => op.register === AP_DRW && op.mode === READ)).toBe(true);
+        });
+        it("writes a 32-bit value to memory", async () => {
+            await adi.writeMem32(0x10000010, 0x12345678);
+            const ops = dap.transferCalls[0];
+            const drwWrite = ops.find((op) => op.register === AP_DRW && op.mode === WRITE);
+            expect(drwWrite).toBeDefined();
+            expect(drwWrite.value).toBe(0x12345678);
+        });
+    });
+    describe("register caching", () => {
+        beforeEach(async () => {
+            setupConnectRegisters(dap);
+            await adi.connect();
+            dap.transferCalls.length = 0;
+        });
+        it("caches DP_SELECT and skips redundant writes", async () => {
+            // First read: all ops including DP_SELECT
+            await adi.readMem32(0x10000010);
+            const firstCallOpCount = dap.transferCalls[0].length;
+            // Second read at same address: DP_SELECT should be cached
+            await adi.readMem32(0x10000010);
+            const secondCallOpCount = dap.transferCalls[1].length;
+            expect(secondCallOpCount).toBeLessThan(firstCallOpCount);
+        });
+        it("invalidates cache on transfer error", async () => {
+            // First read succeeds, populating cache
+            await adi.readMem32(0x10000010);
+            // Second read: cache is warm, fewer ops
+            await adi.readMem32(0x10000010);
+            const cachedCallOpCount = dap.transferCalls[1].length;
+            // Third read fails — this invalidates the cache
+            vi.mocked(dap.transfer).mockRejectedValueOnce(new Error("fault"));
+            await expect(adi.readMem32(0x10000010)).rejects.toThrow("fault");
+            // Fourth read: cache should be invalidated, more ops than cached
+            await adi.readMem32(0x10000010);
+            const afterErrorOpCount = dap.transferCalls[2].length;
+            expect(afterErrorOpCount).toBeGreaterThan(cachedCallOpCount);
+        });
+    });
+    describe("readBlock", () => {
+        beforeEach(async () => {
+            setupConnectRegisters(dap);
+            await adi.connect();
+            dap.transferCalls.length = 0;
+        });
+        it("reads a small block in a single chunk", async () => {
+            dap.queueBlockReadResult(0x100, 0x200, 0x300);
+            const result = await adi.readBlock(0x20000000, 3);
+            expect(result.length).toBe(3);
+            expect(result[0]).toBe(0x100);
+            expect(result[1]).toBe(0x200);
+            expect(result[2]).toBe(0x300);
+            expect(dap.transferBlockRead).toHaveBeenCalledTimes(1);
+        });
+        it("splits reads at TAR auto-increment page boundaries", async () => {
+            // Address near a 1KB boundary: 0x200003F0 is 0x10 (16) bytes from the
+            // 1KB boundary at 0x20000400, so 4 words fit in the first page.
+            const address = 0x200003f0;
+            const count = 8; // 4 words in first page + 4 in next
+            dap.queueBlockReadResult(1, 2, 3, 4);
+            dap.queueBlockReadResult(5, 6, 7, 8);
+            const result = await adi.readBlock(address, count);
+            expect(result.length).toBe(8);
+            expect(Array.from(result)).toEqual([1, 2, 3, 4, 5, 6, 7, 8]);
+            expect(dap.transferBlockRead).toHaveBeenCalledTimes(2);
+        });
+    });
+    describe("writeBlock", () => {
+        beforeEach(async () => {
+            setupConnectRegisters(dap);
+            await adi.connect();
+            dap.transferCalls.length = 0;
+        });
+        it("writes a small block in a single chunk", async () => {
+            await adi.writeBlock(0x20000000, new Uint32Array([0xaa, 0xbb]));
+            expect(dap.transferBlockWrite).toHaveBeenCalledTimes(1);
+            const call = vi.mocked(dap.transferBlockWrite).mock.calls[0];
+            expect(call[0]).toBe(AP);
+            expect(call[1]).toBe(AP_DRW);
+            expect(Array.from(call[2])).toEqual([0xaa, 0xbb]);
+        });
+        it("splits writes at TAR auto-increment page boundaries", async () => {
+            const address = 0x200003f0; // 16 bytes (4 words) from 1KB boundary
+            await adi.writeBlock(address, new Uint32Array([1, 2, 3, 4, 5, 6, 7, 8]));
+            expect(dap.transferBlockWrite).toHaveBeenCalledTimes(2);
+            const firstChunk = vi.mocked(dap.transferBlockWrite).mock.calls[0][2];
+            const secondChunk = vi.mocked(dap.transferBlockWrite).mock.calls[1][2];
+            expect(Array.from(firstChunk)).toEqual([1, 2, 3, 4]);
+            expect(Array.from(secondChunk)).toEqual([5, 6, 7, 8]);
+        });
+    });
+    describe("transferSequence", () => {
+        beforeEach(async () => {
+            setupConnectRegisters(dap);
+            await adi.connect();
+            dap.transferCalls.length = 0;
+        });
+        it("executes groups as separate transfers and concatenates results", async () => {
+            const callsBefore = dap.transferCalls.length;
+            dap.queueTransferResult(0x11);
+            dap.queueTransferResult(0x22);
+            const result = await adi.transferSequence([
+                [{ port: DP, mode: READ, register: 0x00 }],
+                [{ port: DP, mode: READ, register: 0x04 }],
+            ]);
+            // Two new transfer calls for our two groups
+            expect(dap.transferCalls.length - callsBefore).toBe(2);
+            expect(result.length).toBe(2);
+            expect(result[0]).toBe(0x11);
+            expect(result[1]).toBe(0x22);
+        });
+    });
+    describe("waitFor", () => {
+        it("throws DeviceError on timeout", async () => {
+            await expect(waitFor(() => Promise.resolve(false), 1)).rejects.toThrow(DeviceError);
+        });
+    });
+    describe("resetState", () => {
+        it("allows reconnecting after reset", async () => {
+            setupConnectRegisters(dap);
+            await adi.connect();
+            adi.resetState();
+            // Should be able to connect again (connectOnce won't skip)
+            setupConnectRegisters(dap);
+            await adi.connect();
+            // open called twice
+            expect(dap.open).toHaveBeenCalledTimes(2);
+        });
+    });
+});
+//# sourceMappingURL=arm-debug.test.js.map

package/build/esm/usb/arm-debug.test.js.map

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package/build/{cjs → esm/usb}/board-serial-info.d.ts

@@ -3,12 +3,13 @@
  *
  * SPDX-License-Identifier: MIT
  */
-import { BoardId } from "./board-id.js";
+import { BoardId } from "../board-id.js";
 export declare class BoardSerialInfo {
     id: BoardId;
     familyId: string;
     hic: string;
     constructor(id: BoardId, familyId: string, hic: string);
+    static fromSerial(serial: string, log: (msg: string) => void): BoardSerialInfo;
     static parse(device: USBDevice, log: (msg: string) => void): BoardSerialInfo;
     eq(other: BoardSerialInfo): boolean;
 }

package/build/esm/{board-serial-info.js → usb/board-serial-info.js}

@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier: MIT
  */
-import { BoardId } from "./board-id.js";
+import { BoardId } from "../board-id.js";
 export class BoardSerialInfo {
     constructor(id, familyId, hic) {
         Object.defineProperty(this, "id", {
@@ -25,19 +25,22 @@ export class BoardSerialInfo {
             value: hic
         });
     }
-    static parse(device, log) {
-        const serial = device.serialNumber;
-        if (!serial) {
-            throw new Error("Could not detected ID from connected board.");
-        }
+    static fromSerial(serial, log) {
         if (serial.length !== 48) {
-            log(`USB serial number unexpected length: ${serial.length}`);
+            log(`Serial number unexpected length: ${serial.length}`);
         }
         const id = serial.substring(0, 4);
         const familyId = serial.substring(4, 8);
         const hic = serial.slice(-8);
         return new BoardSerialInfo(BoardId.parse(id), familyId, hic);
     }
+    static parse(device, log) {
+        const serial = device.serialNumber;
+        if (!serial) {
+            throw new Error("Could not detected ID from connected board.");
+        }
+        return BoardSerialInfo.fromSerial(serial, log);
+    }
     eq(other) {
         return (other.id === this.id &&
             other.familyId === this.familyId &&

package/build/esm/usb/board-serial-info.js.map

@@ -0,0 +1 @@
+{"version":3,"file":"board-serial-info.js","sourceRoot":"","sources":["../../../src/usb/board-serial-info.ts"],"names":[],"mappings":"AAAA;;;;GAIG;AACH,OAAO,EAAE,OAAO,EAAE,MAAM,gBAAgB,CAAC;AAEzC,MAAM,OAAO,eAAe;IAC1B,YACS,EAAW,EACX,QAAgB,EAChB,GAAW;QAFlB;;;;mBAAO,EAAE;WAAS;QAClB;;;;mBAAO,QAAQ;WAAQ;QACvB;;;;mBAAO,GAAG;WAAQ;IACjB,CAAC;IAEJ,MAAM,CAAC,UAAU,CAAC,MAAc,EAAE,GAA0B;QAC1D,IAAI,MAAM,CAAC,MAAM,KAAK,EAAE,EAAE,CAAC;YACzB,GAAG,CAAC,oCAAoC,MAAM,CAAC,MAAM,EAAE,CAAC,CAAC;QAC3D,CAAC;QACD,MAAM,EAAE,GAAG,MAAM,CAAC,SAAS,CAAC,CAAC,EAAE,CAAC,CAAC,CAAC;QAClC,MAAM,QAAQ,GAAG,MAAM,CAAC,SAAS,CAAC,CAAC,EAAE,CAAC,CAAC,CAAC;QACxC,MAAM,GAAG,GAAG,MAAM,CAAC,KAAK,CAAC,CAAC,CAAC,CAAC,CAAC;QAC7B,OAAO,IAAI,eAAe,CAAC,OAAO,CAAC,KAAK,CAAC,EAAE,CAAC,EAAE,QAAQ,EAAE,GAAG,CAAC,CAAC;IAC/D,CAAC;IAED,MAAM,CAAC,KAAK,CAAC,MAAiB,EAAE,GAA0B;QACxD,MAAM,MAAM,GAAG,MAAM,CAAC,YAAY,CAAC;QACnC,IAAI,CAAC,MAAM,EAAE,CAAC;YACZ,MAAM,IAAI,KAAK,CAAC,6CAA6C,CAAC,CAAC;QACjE,CAAC;QACD,OAAO,eAAe,CAAC,UAAU,CAAC,MAAM,EAAE,GAAG,CAAC,CAAC;IACjD,CAAC;IAED,EAAE,CAAC,KAAsB;QACvB,OAAO,CACL,KAAK,CAAC,EAAE,KAAK,IAAI,CAAC,EAAE;YACpB,KAAK,CAAC,QAAQ,KAAK,IAAI,CAAC,QAAQ;YAChC,KAAK,CAAC,GAAG,KAAK,IAAI,CAAC,GAAG,CACvB,CAAC;IACJ,CAAC;CACF"}

package/build/esm/usb/board-serial-info.test.d.ts

@@ -0,0 +1 @@
+export {};

package/build/esm/{board-serial-info.test.js → usb/board-serial-info.test.js}

@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier: MIT
  */
-import { BoardId } from "./board-id.js";
+import { BoardId } from "../board-id.js";
 import { BoardSerialInfo } from "./board-serial-info.js";
 import { afterEach, describe, expect, it, vi } from "vitest";
 describe("BoardSerialInfo", () => {
@@ -38,9 +38,7 @@ describe("BoardSerialInfo", () => {
             familyId: "3602",
             hic: "00097969",
         });
-        expect(log.mock.calls).toEqual([
-            ["USB serial number unexpected length: 45"],
-        ]);
+        expect(log.mock.calls).toEqual([["Serial number unexpected length: 45"]]);
     });
 });
 //# sourceMappingURL=board-serial-info.test.js.map

package/build/esm/usb/board-serial-info.test.js.map

@@ -0,0 +1 @@
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package/build/esm/usb/cdc-saturation.d.ts

@@ -0,0 +1,36 @@
+/**
+ * (c) 2026, Micro:bit Educational Foundation and contributors
+ *
+ * SPDX-License-Identifier: MIT
+ */
+/**
+ * CDC pipeline saturation
+ *
+ * DAPLink's CDC serial path and WebUSB vendor serial reads share the same
+ * UART ring buffer. After a physical USB connection, CDC consumes early
+ * serial bytes before our vendor reads can get them, causing truncated
+ * output. See: https://github.com/ARMmbed/DAPLink/issues/903
+ *
+ * Workaround: before flashing, push dummy data through the target's UART
+ * to fill DAPLink's internal buffers. When nobody is reading from the CDC
+ * serial port, the CDC TX buffer fills first, then cdc_process_event()
+ * stops pulling from the UART RX ring buffer, and that fills too. Once
+ * both are full, all subsequent UART data overflows harmlessly and
+ * post-flash serial output is left for our vendor reads.
+ *
+ * V1 (nRF51) uses a Thumb blob for the legacy byte-at-a-time UART.
+ * V2 (nRF52833) uses SWD register writes to trigger a UARTE DMA transfer.
+ *
+ * V1 DAPLink defaults to 9600 baud on fresh USB connection, so we call
+ * setBaudrate(115200) before saturation to ensure DAPLink can decode the
+ * bytes we send.
+ */
+import { BoardVersion } from "../device.js";
+import { Logging } from "../logging.js";
+import { type USBDeviceWrapper } from "./device-wrapper.js";
+/**
+ * Push dummy data through the target's UART to fill DAPLink's internal
+ * CDC buffers, preventing CDC from consuming post-flash serial output.
+ * Must be called while the target is halted.
+ */
+export declare function saturateCdcPipeline(device: USBDeviceWrapper, boardVersion: BoardVersion, logging: Logging): Promise<void>;

package/build/esm/usb/cdc-saturation.js

@@ -0,0 +1,148 @@
+/**
+ * (c) 2026, Micro:bit Educational Foundation and contributors
+ *
+ * SPDX-License-Identifier: MIT
+ */
+import { CoreRegister } from "./cortex-m.js";
+const CDC_SAT_LOAD_ADDR = 0x20000000;
+// DAPLink's UART RX ring buffer + CDC TX buffer must both fill before CDC
+// stops consuming. Buffer sizes vary by interface chip:
+//   KL26/KL27:        64 + 64 = 128 bytes
+//   nRF52820/nRF52833: 1024 + 64 = 1088 bytes
+// 2048 covers all known variants with headroom (~178ms at 115200 baud).
+const CDC_SAT_BYTE_COUNT = 2048;
+// nRF51 legacy UART registers (base 0x40002000)
+const NRF51_UART_TASKS_STARTTX = 0x40002008;
+const NRF51_UART_TASKS_STOPTX = 0x4000200c;
+const NRF51_UART_EVENTS_TXDRDY = 0x4000211c;
+const NRF51_UART_ENABLE = 0x40002500;
+const NRF51_UART_PSEL_TXD = 0x4000250c;
+const NRF51_UART_BAUDRATE = 0x40002524;
+const NRF51_UART_TXD = 0x4000251c;
+// nRF52833 UARTE registers (base 0x40002000)
+const NRF52_UARTE_TASKS_STARTTX = 0x40002008;
+const NRF52_UARTE_TASKS_STOPTX = 0x4000210c;
+const NRF52_UARTE_EVENTS_ENDTX = 0x40002120;
+const NRF52_UARTE_EVENTS_TXSTOPPED = 0x40002158;
+const NRF52_UARTE_ENABLE = 0x40002500;
+const NRF52_UARTE_PSEL_TXD = 0x4000250c;
+const NRF52_UARTE_BAUDRATE = 0x40002524;
+const NRF52_UARTE_TXD_PTR = 0x40002544;
+const NRF52_UARTE_TXD_MAXCNT = 0x40002548;
+// UART baud rate register value for 115200 (same encoding on nRF51 and nRF52)
+const NRF_BAUDRATE_115200 = 0x01d7e000;
+// micro:bit UART TX pins (target → interface chip)
+const MICROBIT_V1_TX_PIN = 24; // P0.24
+const MICROBIT_V2_TX_PIN = 6; // P0.06
+/**
+ * Push dummy data through the target's UART to fill DAPLink's internal
+ * CDC buffers, preventing CDC from consuming post-flash serial output.
+ * Must be called while the target is halted.
+ */
+export async function saturateCdcPipeline(device, boardVersion, logging) {
+    try {
+        if (boardVersion === "V1") {
+            await saturateCdcV1(device, logging);
+        }
+        else {
+            await saturateCdcV2(device, logging);
+        }
+    }
+    catch (e) {
+        logging.log(`CDC saturation failed (non-fatal): ${e instanceof Error ? e.message : e}`);
+    }
+}
+/**
+ * V1 (nRF51): Run a Thumb blob that sends CDC_SAT_BYTE_COUNT bytes at
+ * wire speed through the legacy UART. The CPU is resumed with PRIMASK=1
+ * to prevent the halted program's ISRs from interfering.
+ *
+ * Blob register convention (values passed via writeCoreRegister):
+ *   r0 = byte count, r1 = TXD addr, r2 = TXDRDY addr,
+ *   r3 = data byte, r4 = 0 (for clearing events)
+ *
+ * Thumb instructions (word 0 is a BKPT pair used as the LR target):
+ *   loop: str r4, [r2]      // clear TXDRDY
+ *         str r3, [r1]      // write TXD
+ *   wait: ldr r5, [r2]      // read TXDRDY
+ *         cmp r5, #0
+ *         beq wait
+ *         subs r0, #1
+ *         bne loop
+ *         bkpt #0
+ */
+async function saturateCdcV1(device, logging) {
+    const { adi, cortexM } = device;
+    // Stop any in-flight TX and fully reconfigure the UART from scratch.
+    // The previous program (e.g. MakeCode) may not have set up the UART at
+    // all, so we can't assume any registers are configured.
+    await adi.writeMem32(NRF51_UART_TASKS_STOPTX, 1);
+    await adi.writeMem32(NRF51_UART_ENABLE, 0);
+    await adi.writeMem32(NRF51_UART_PSEL_TXD, MICROBIT_V1_TX_PIN);
+    await adi.writeMem32(NRF51_UART_BAUDRATE, NRF_BAUDRATE_115200);
+    await adi.writeMem32(NRF51_UART_ENABLE, 4); // UART enable
+    await adi.writeMem32(NRF51_UART_EVENTS_TXDRDY, 0);
+    await adi.writeMem32(NRF51_UART_TASKS_STARTTX, 1);
+    const blob = new Uint32Array([
+        0xbe00be00, // BKPT (LR target) + pad
+        0x600b6014, // str r4,[r2]; str r3,[r1]
+        0x2d006815, // ldr r5,[r2]; cmp r5,#0
+        0x3801d0fc, // beq wait; subs r0,#1
+        0xbe00d1f8, // bne loop; bkpt
+    ]);
+    await adi.writeBlock(CDC_SAT_LOAD_ADDR, blob);
+    await cortexM.writeCoreRegister(CoreRegister.PC, (CDC_SAT_LOAD_ADDR + 4) | 1);
+    await cortexM.writeCoreRegister(CoreRegister.LR, CDC_SAT_LOAD_ADDR | 1);
+    await cortexM.writeCoreRegister(CoreRegister.SP, 0x20004000);
+    await cortexM.writeCoreRegister(CoreRegister.PSR, 0x01000000);
+    await cortexM.writeCoreRegister(0, CDC_SAT_BYTE_COUNT);
+    await cortexM.writeCoreRegister(1, NRF51_UART_TXD);
+    await cortexM.writeCoreRegister(2, NRF51_UART_EVENTS_TXDRDY);
+    await cortexM.writeCoreRegister(3, 0x00); // NUL byte (ignored by terminals)
+    await cortexM.writeCoreRegister(4, 0);
+    await cortexM.writeCoreRegister(20, 1); // PRIMASK = 1
+    await cortexM.resume(false);
+    // Wait for blob to hit its final BKPT (~178ms for 2048 bytes at 115200).
+    for (let i = 0; i < 2000; i++) {
+        if (await cortexM.isHalted())
+            return;
+    }
+    logging.log("V1 CDC saturation blob did not complete, halting");
+    await cortexM.halt();
+}
+/**
+ * V2 (nRF52833): Set up a UARTE DMA transfer via SWD register writes.
+ * The DMA engine runs independently of the halted CPU.
+ */
+async function saturateCdcV2(device, logging) {
+    const { adi } = device;
+    // Stop any in-flight transfer cleanly
+    await adi.writeMem32(NRF52_UARTE_EVENTS_TXSTOPPED, 0);
+    await adi.writeMem32(NRF52_UARTE_TASKS_STOPTX, 1);
+    for (let i = 0; i < 100; i++) {
+        if (await adi.readMem32(NRF52_UARTE_EVENTS_TXSTOPPED))
+            break;
+    }
+    // Fully reconfigure UARTE from scratch — the previous program may not
+    // have set up the peripheral at all.
+    await adi.writeMem32(NRF52_UARTE_ENABLE, 0);
+    await adi.writeMem32(NRF52_UARTE_PSEL_TXD, MICROBIT_V2_TX_PIN);
+    await adi.writeMem32(NRF52_UARTE_BAUDRATE, NRF_BAUDRATE_115200);
+    await adi.writeMem32(NRF52_UARTE_ENABLE, 8); // 8 = UARTE mode
+    // Write NUL bytes to RAM for the DMA buffer (harmless if seen by a
+    // CDC reader — terminals ignore NUL).
+    const nulBuf = new Uint32Array(CDC_SAT_BYTE_COUNT / 4);
+    await adi.writeBlock(CDC_SAT_LOAD_ADDR, nulBuf);
+    // Set up DMA and trigger
+    await adi.writeMem32(NRF52_UARTE_TXD_PTR, CDC_SAT_LOAD_ADDR);
+    await adi.writeMem32(NRF52_UARTE_TXD_MAXCNT, CDC_SAT_BYTE_COUNT);
+    await adi.writeMem32(NRF52_UARTE_EVENTS_ENDTX, 0);
+    await adi.writeMem32(NRF52_UARTE_TASKS_STARTTX, 1);
+    // Poll for ENDTX (~178ms for 2048 bytes at 115200 baud).
+    for (let i = 0; i < 2000; i++) {
+        if (await adi.readMem32(NRF52_UARTE_EVENTS_ENDTX))
+            return;
+    }
+    logging.log("UARTE ENDTX not detected after polling");
+}
+//# sourceMappingURL=cdc-saturation.js.map

package/build/esm/usb/cdc-saturation.js.map

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