@micro-os-plus/architecture-riscv 4.1.0 → 5.1.0

package/CHANGELOG.md

@@ -6,9 +6,111 @@ Please check
 [GitHub](https://github.com/micro-os-plus/architecture-riscv-xpack/issues/)
 and close existing issues and pull requests.
 
+## 2026-09-09
+
+* v5.1.0
+* b3d5140 re-format
+
+## 2026-09-08
+
+* 0150285 architecture.h __ASSEMBLY__
+* cadd9d4 add micro_os_plus_semihosting_register_t
+
+## 2026-09-07
+
+* bf22010 cosmetics xpm packages
+* 7b75d63 add show-cpuid
+
+## 2026-08-05
+
+* 19ddea8 readme cosmetics
+
+## 2026-08-04
+
+* 8052bbb 5.0.0
+* c3a6757 prepare v5.0.0
+* f8176c2 re-generate top commons
+
+## 2026-07-31
+
+* a172bb5 CHANGELOG update
+* 0705830 xcdl-package.jsonc update
+* 37a7f6d update guards & includes
+
+## 2026-07-22
+
+* 351f4f0 prepare 5.0.0
+* 780394f xcdl export
+* c07d045 re-work includes
+* 98d177f re-generate top commons
+* b79195e re-generate top commons
+* 1a68ac8 extract semihosting.cpp
+* 7f7663c fix copyright notices
+
+## 2026-06-06
+
+* 036a3df copyright update 2026
+
+## 2025-11-20
+
+* ede63b1 rename npm-pack
+
+## 2025-10-07
+
+* 4bcf370 update copyright notices
+
+## 2023-11-28
+
+* d1ef44b README updates
+* 8509b6e package.json: cosmetise scripts
+
+## 2023-10-19
+
+* 9215ac5 package.json: cosmetise description
+* a7b4471 README updates
+
+## 2023-07-14
+
+* 92ed5f2 README updates
+* fa45973 package.json: cosmetise urls
+* 5625c25 package.json: minXpm 0.16.2
+
+## 2023-06-04
+
+* b1fc258 update for @scope/name
+
+## 2023-06-03
+
+* 39ca32a lower case ci.yml
+* 5a019d3 package.json min 0.16.0
+
+## 2023-05-08
+
+* 03d57b0 .npmignore update
+* 99627ed README updates
+* 5e0620b README updates
+* 6c4bd98 READMEs update
+* 1e5a1a6 meson.build cosmetics
+
+## 2022-08-16
+
+* a9fb5e2 package.json min 0.14.0 & defaults
+
+## 2022-08-03
+
+* d97774b README updates
+* 452f77c .vscode/settings.json: cmake.ignoreCMakeListsMissing
+* 87537f4 .vscode/settings.json: makefile.configureOnOpen
+
+## 2022-08-02
+
+* ce9c653 READMEs updates
+
 ## 2022-07-28
 
-* v4.1.0
+* 2bff438 CHANGELOG update
+* e5a9bac 4.1.0
+* 6943ac8 prepare v4.1.0
 * e19aa16 #5: remove linker script ARM sections
 * 5f43150 #7: add sections-flash.ld
 * 963be52 #6: rework semihosting_call_host() to avoid asm() registers
@@ -50,7 +152,7 @@ and close existing issues and pull requests.
 ## 2021-02-04
 
 * v1.1.0
-* first restructured release
+* first restructured release; renamed architecture-riscv
 
 ## 2020-09-19
 

package/CMakeLists.txt

@@ -1,87 +1,105 @@
 # -----------------------------------------------------------------------------
+# DO NOT EDIT! Automatically generated from template file: xcdl-package.jsonc
 #
-# This file is part of the µOS++ distribution.
-#   (https://github.com/micro-os-plus/)
-# Copyright (c) 2021 Liviu Ionescu
+# This file is part of the µOS++ project (https://micro-os-plus.github.io/).
+# Copyright (c) 2021-2026 Liviu Ionescu. All rights reserved.
 #
-# Permission to use, copy, modify, and/or distribute this software
-# for any purpose is hereby granted, under the terms of the MIT license.
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose is hereby granted, under the terms of the MIT license.
 #
-# If a copy of the license was not distributed with this file, it can
-# be obtained from https://opensource.org/licenses/MIT/.
+# If a copy of the license was not distributed with this file, it can be
+# obtained from https://opensource.org/licenses/mit.
 #
 # -----------------------------------------------------------------------------
 
-# This file is intended to be consumed by applications with:
+# This file is intended to be used by applications via:
 #
-# `add_subdirectory("xpacks/micro-os-plus-architecture-riscv")`
+# `add_subdirectory("xpacks/@micro-os-plus/architecture-riscv")`
 #
-# The result is an interface library that can be added to the linker with:
+# This creates libraries that can be linked to a target with:
 #
-# `target_link_libraries(your-target PUBLIC micro-os-plus::architecture-riscv)`
+# ~~~
+# target_link_libraries(your-target PUBLIC micro-os-plus::architectures-riscv)
+# ~~~
 
 # -----------------------------------------------------------------------------
-## Preamble ##
 
 # https://cmake.org/cmake/help/v3.20/
-cmake_minimum_required(VERSION 3.20)
-
-project(
+cmake_minimum_required (VERSION 3.20)
+project (
   micro-os-plus-architecture-riscv
-  DESCRIPTION "µOS++ RISC-V architecture"
+  DESCRIPTION "A source code library with the µOS++ RISC-V architecture port"
+  LANGUAGES C CXX ASM
 )
 
-if(COMMAND xpack_get_package_name_and_version)
-  xpack_get_package_name_and_version("${CMAKE_CURRENT_SOURCE_DIR}/package.json")
-  message(VERBOSE "Processing xPack ${PACKAGE_JSON_NAME}@${PACKAGE_JSON_VERSION}...")
-endif()
-
-# -----------------------------------------------------------------------------
-## The project library definitions ##
-
-# https://cmake.org/cmake/help/v3.20/command/add_library.html?highlight=interface#normal-libraries
-# PRIVATE: build definitions, used internally
-# INTERFACE: usage definitions, passed up to targets linking to it
-# PUBLIC: both
+# To access the optional functions, include the
+# `cmake/micro-os-plus-build-helper.cmake` file from the
+# `@micro-os-plus/build-helper` package.
 
-add_library(micro-os-plus-architecture-riscv-interface INTERFACE EXCLUDE_FROM_ALL)
+if (COMMAND xpack_get_package_name_and_version)
+  xpack_get_package_name_and_version (
+    "${CMAKE_CURRENT_SOURCE_DIR}/package.json"
+  )
+  message (
+    VERBOSE
+    "Processing xpm package ${PACKAGE_JSON_NAME}@${PACKAGE_JSON_VERSION}..."
+  )
+endif ()
 
 # -----------------------------------------------------------------------------
-# Target settings.
-
-target_include_directories(micro-os-plus-architecture-riscv-interface INTERFACE
-  "include"
-)
 
-target_sources(micro-os-plus-architecture-riscv-interface INTERFACE
-  # None.
+# Interface libraries are the main targets, which consumers (like embedded
+# applications) link against. It defines the public API and properties of the
+# library; sources are propagated to and compiled by each consumer.
+
+# They are aliased using namespaced syntax (Project::Target). This is the
+# canonical pattern for consumption via target_link_libraries(), whether the
+# dependency is added via add_subdirectory(), FetchContent, or an installed
+# package via find_package(). Using "::" lets CMake detect an invalid or
+# misspelled target name at configure time, rather than silently passing it
+# through to the linker as a plain string or flag. Note: alias targets are
+# read-only; properties must be set on the underlying target, not on the alias
+# itself.
+
+# https://cmake.org/cmake/help/v3.20/command/add_library.html?highlight=interface#interface-libraries
+# Visibility keywords: PRIVATE applies to the target itself; INTERFACE passes
+# properties up to targets that link against it; PUBLIC does both.
+add_library (
+  micro-os-plus-architectures-riscv-interface INTERFACE EXCLUDE_FROM_ALL
 )
 
-target_compile_definitions(micro-os-plus-architecture-riscv-interface INTERFACE
-  # None.
+target_include_directories (
+  micro-os-plus-architectures-riscv-interface INTERFACE "include"
 )
 
-target_compile_options(micro-os-plus-architecture-riscv-interface INTERFACE
-  # None.
-)
-
-target_link_libraries(micro-os-plus-architecture-riscv-interface INTERFACE
-  # Dependencies
-  # None.
+target_sources (
+  micro-os-plus-architectures-riscv-interface INTERFACE "src/semihosting.cpp"
+                                                        "src/show-cpuid.cpp"
 )
 
 if (COMMAND xpack_display_target_lists)
-  xpack_display_target_lists(micro-os-plus-architecture-riscv-interface)
-endif()
+  xpack_display_target_lists (micro-os-plus-architectures-riscv-interface)
+endif ()
 
 # -----------------------------------------------------------------------------
-# Aliases.
+# Alias.
 
 # https://cmake.org/cmake/help/v3.20/command/add_library.html#alias-libraries
-add_library(micro-os-plus::architecture-riscv ALIAS micro-os-plus-architecture-riscv-interface)
-message(VERBOSE "> micro-os-plus::architecture-riscv -> micro-os-plus-architecture-riscv-interface")
+add_library (
+  micro-os-plus::architectures-riscv ALIAS
+  micro-os-plus-architectures-riscv-interface
+)
+message (
+  VERBOSE
+  "> micro-os-plus::architectures-riscv -> micro-os-plus-architectures-riscv-interface"
+)
 
-add_library(micro-os-plus::architecture ALIAS micro-os-plus-architecture-riscv-interface)
-message(VERBOSE "> micro-os-plus::architecture -> micro-os-plus-architecture-riscv-interface")
+add_library (
+  micro-os-plus::architecture ALIAS micro-os-plus-architectures-riscv-interface
+)
+message (
+  VERBOSE
+  "> micro-os-plus::architecture -> micro-os-plus-architectures-riscv-interface"
+)
 
 # -----------------------------------------------------------------------------

package/LICENSE

@@ -1,6 +1,6 @@
 MIT License
 
-Copyright (c) 2017 Liviu Ionescu
+Copyright (c) 2017-2026 Liviu Ionescu
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

package/README.md

@@ -1,7 +1,10 @@
+[![GitHub package.json version](https://img.shields.io/github/package-json/v/micro-os-plus/architecture-riscv-xpack)](https://github.com/micro-os-plus/architecture-riscv-xpack/blob/xpack/package.json)
+[![GitHub tag (latest by date)](https://img.shields.io/github/v/tag/micro-os-plus/architecture-riscv-xpack)](https://github.com/micro-os-plus/architecture-riscv-xpack/tags/)
+[![npm (scoped)](https://img.shields.io/npm/v/@micro-os-plus/architecture-riscv.svg?color=blue)](https://www.npmjs.com/package/@micro-os-plus/architecture-riscv/)
 [![license](https://img.shields.io/github/license/micro-os-plus/architecture-riscv-xpack)](https://github.com/micro-os-plus/architecture-riscv-xpack/blob/xpack/LICENSE)
-[![CI on Push](https://github.com/micro-os-plus/architecture-riscv-xpack/actions/workflows/CI.yml/badge.svg)](https://github.com/micro-os-plus/architecture-riscv-xpack/actions/workflows/CI.yml)
+[![CI on Push](https://github.com/micro-os-plus/architecture-riscv-xpack/actions/workflows/ci.yml/badge.svg)](https://github.com/micro-os-plus/architecture-riscv-xpack/actions/workflows/ci.yml)
 
-# A source library xPack with the µOS++ RISC-V architecture definitions
+# A source code library with the µOS++ RISC-V architecture definitions
 
 This project provides the **architecture-riscv** source library as an xPack
 dependency and includes architecture definitions for RISC-V embedded projects.
@@ -27,12 +30,18 @@ As a source library xPack, the easiest way to add it to a project is via
 A recent [xpm](https://xpack.github.io/xpm/),
 which is a portable [Node.js](https://nodejs.org/) command line application.
 
+It is recommended to update to the latest version with:
+
+```sh
+npm install --global xpm@latest
+```
+
 For details please follow the instructions in the
 [xPack install](https://xpack.github.io/install/) page.
 
 ### xpm
 
-This package is available from npmjs.com as
+This package is available as
 [`@micro-os-plus/architecture-riscv`](https://www.npmjs.com/package/@micro-os-plus/architecture-riscv)
 from the `npmjs.com` registry:
 
@@ -42,7 +51,7 @@ xpm init # Unless a package.json is already present
 
 xpm install @micro-os-plus/architecture-riscv@latest
 
-ls -l xpacks/micro-os-plus-architecture-riscv
+ls -l xpacks/@micro-os-plus/architecture-riscv
 ```
 
 ### Git submodule
@@ -56,7 +65,7 @@ git init # Unless already a Git project
 mkdir -p xpacks
 
 git submodule add https://github.com/micro-os-plus/architecture-riscv-xpack.git \
-  xpacks/micro-os-plus-architecture-riscv
+  xpacks/@micro-os-plus/architecture-riscv
 ```
 
 ## Branches
@@ -64,12 +73,12 @@ git submodule add https://github.com/micro-os-plus/architecture-riscv-xpack.git
 Apart from the unused `master` branch, there are two active branches:
 
 - `xpack`, with the latest stable version (default)
-- `xpack-develop`, with the current development version
+- `xpack-development`, with the current development version
 
-All development is done in the `xpack-develop` branch, and contributions via
+All development is done in the `xpack-development` branch, and contributions via
 Pull Requests should be directed to this branch.
 
-When new releases are published, the `xpack-develop` branch is merged
+When new releases are published, the `xpack-development` branch is merged
 into `xpack`.
 
 ## Developer info
@@ -103,7 +112,7 @@ like what GPIO pins are used for various LEDs, buttons, etc.
 The portable way to include platform specific definitions in an application is:
 
 ```c
-#include <micro-os-plus/platform.h>
+#include "micro-os-plus/platform.h"
 ```
 
 In µOS++, the platform specific definitions are grouped in the
@@ -117,10 +126,10 @@ SiFive HiFive1 small development board.
 The RISC-V documentation introduces the term _platform_ as:
 
 > A RISC-V hardware _platform_ can contain one or more RISC-V-compatible
-processing cores together with other non-RISC-V-compatible cores,
-fixed-function accelerators, various physical memory structures,
-I/O devices, and an interconnect structure to allow the components
-to communicate.
+> processing cores together with other non-RISC-V-compatible cores,
+> fixed-function accelerators, various physical memory structures,
+> I/O devices, and an interconnect structure to allow the components
+> to communicate.
 
 In modern implementations, this is generally either a physical chip
 or a synthesised one.
@@ -144,7 +153,7 @@ In µOS++, the device specific definitions are grouped in the
 The portable way to include device specific definitions in an application is:
 
 ```c
-#include <micro-os-plus/device.h>
+#include "micro-os-plus/device.h"
 ```
 
 Example of device packages are **sifive/devices** with the SiFive
@@ -155,9 +164,9 @@ Freedom E310 and E31/E51 Arty devices.
 The RISC-V documentation introduces the term _core_ as:
 
 > A component is termed a core if it contains an independent
-instruction fetch unit. A RISC-V-compatible core might support
-multiple RISC-V-compatible hardware threads, or harts, through
-multi-threading.
+> instruction fetch unit. A RISC-V-compatible core might support
+> multiple RISC-V-compatible hardware threads, or harts, through
+> multi-threading.
 
 In µOS++, the core specific definitions are grouped in the
 `riscv::core` namespace.
@@ -166,7 +175,7 @@ The portable way to include architecture specific definitions
 in an application is:
 
 ```c
-#include <micro-os-plus/architecture.h>
+#include "micro-os-plus/architecture.h"
 ```
 
 #### Hart
@@ -210,7 +219,7 @@ The following folders should be passed to the compiler during the build:
 The header files to be included in user projects are:
 
 ```c++
-#include <micro-os-plus/architecture.h>
+#include "micro-os-plus/architecture.h"
 ```
 
 #### Source files
@@ -246,7 +255,7 @@ To integrate the architecture-riscv source library into a CMake application,
 add this folder to the build:
 
 ```cmake
-add_subdirectory("xpacks/micro-os-plus-architecture-riscv")`
+add_subdirectory("xpacks/@micro-os-plus/architecture-riscv")`
 ```
 
 The result is an interface library that can be added as an application
@@ -265,7 +274,7 @@ To integrate the architecture-riscv source library into a meson application,
 add this folder to the build:
 
 ```meson
-subdir('xpacks/micro-os-plus-architecture-riscv')
+subdir('xpacks/@micro-os-plus/architecture-riscv')
 ```
 
 The result is a dependency object that can be added
@@ -300,7 +309,7 @@ TBD
 According to [semver](https://semver.org) rules:
 
 > Major version X (X.y.z | X > 0) MUST be incremented if any
-backwards incompatible changes are introduced to the public API.
+> backwards incompatible changes are introduced to the public API.
 
 The incompatible changes, in reverse chronological order,
 are:
@@ -311,7 +320,7 @@ are:
 
 ## License
 
-The original content is released under the
-[MIT License](https://opensource.org/licenses/MIT/),
+Unless otherwise stated, the content is released under the terms of the
+[MIT License](https://opensource.org/licenses/mit),
 with all rights reserved to
-[Liviu Ionescu](https://github.com/ilg-ul/).
+[Liviu Ionescu](https://github.com/ilg-ul).

package/include/micro-os-plus/architecture-riscv/core-functions.h

@@ -1,13 +1,12 @@
 /*
- * This file is part of the µOS++ distribution.
- *   (https://github.com/micro-os-plus/)
- * Copyright (c) 2017 Liviu Ionescu.
+ * This file is part of the µOS++ project (https://micro-os-plus.github.io/).
+ * Copyright (c) 2017-2026 Liviu Ionescu. All rights reserved.
  *
- * Permission to use, copy, modify, and/or distribute this software
- * for any purpose is hereby granted, under the terms of the MIT license.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose is hereby granted, under the terms of the MIT license.
  *
- * If a copy of the license was not distributed with this file, it can
- * be obtained from https://opensource.org/licenses/MIT/.
+ * If a copy of the license was not distributed with this file, it can be
+ * obtained from https://opensource.org/licenses/mit.
  */
 
 #ifndef MICRO_OS_PLUS_ARCHITECTURE_RISCV_CORE_FUNCTIONS_H_
@@ -98,6 +97,11 @@ namespace riscv
 
 #endif // defined(__cplusplus)
 
+// ============================================================================
+// Templates, inlines & constexpr implementations.
+
+#include "inlines/core-functions-inlines.h"
+
 // ----------------------------------------------------------------------------
 
 #endif // MICRO_OS_PLUS_ARCHITECTURE_RISCV_CORE_FUNCTIONS_H_

package/include/micro-os-plus/architecture-riscv/csr-functions.h

@@ -1,13 +1,12 @@
 /*
- * This file is part of the µOS++ distribution.
- *   (https://github.com/micro-os-plus/)
- * Copyright (c) 2017 Liviu Ionescu.
+ * This file is part of the µOS++ project (https://micro-os-plus.github.io/).
+ * Copyright (c) 2017-2026 Liviu Ionescu. All rights reserved.
  *
- * Permission to use, copy, modify, and/or distribute this software
- * for any purpose is hereby granted, under the terms of the MIT license.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose is hereby granted, under the terms of the MIT license.
  *
- * If a copy of the license was not distributed with this file, it can
- * be obtained from https://opensource.org/licenses/MIT/.
+ * If a copy of the license was not distributed with this file, it can be
+ * obtained from https://opensource.org/licenses/mit.
  */
 
 #ifndef MICRO_OS_PLUS_ARCHITECTURE_RISCV_CSR_FUNCTIONS_H_
@@ -15,7 +14,7 @@
 
 // ----------------------------------------------------------------------------
 
-#include <micro-os-plus/architecture-riscv/types.h>
+#include "micro-os-plus/architecture-riscv/types.h"
 
 // ----------------------------------------------------------------------------
 // RISC-V CSR support functions.
@@ -234,6 +233,11 @@ namespace riscv
 
 #endif // defined(__cplusplus)
 
+// ============================================================================
+// Templates, inlines & constexpr implementations.
+
+#include "inlines/csr-functions-inlines.h"
+
 // ----------------------------------------------------------------------------
 
 #endif // MICRO_OS_PLUS_ARCHITECTURE_RISCV_CSR_FUNCTIONS_H_

package/include/micro-os-plus/architecture-riscv/declarations.h

@@ -1,13 +1,12 @@
 /*
- * This file is part of the µOS++ distribution.
- *   (https://github.com/micro-os-plus/)
- * Copyright (c) 2017 Liviu Ionescu.
+ * This file is part of the µOS++ project (https://micro-os-plus.github.io/).
+ * Copyright (c) 2017-2026 Liviu Ionescu. All rights reserved.
  *
- * Permission to use, copy, modify, and/or distribute this software
- * for any purpose is hereby granted, under the terms of the MIT license.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose is hereby granted, under the terms of the MIT license.
  *
- * If a copy of the license was not distributed with this file, it can
- * be obtained from https://opensource.org/licenses/MIT/.
+ * If a copy of the license was not distributed with this file, it can be
+ * obtained from https://opensource.org/licenses/mit.
  */
 
 #ifndef MICRO_OS_PLUS_ARCHITECTURE_RISCV_ARCH_DECLARATIONS_H_
@@ -15,7 +14,7 @@
 
 // ----------------------------------------------------------------------------
 
-#include <micro-os-plus/architecture-riscv/types.h>
+#include "micro-os-plus/architecture-riscv/types.h"
 
 #include <stdint.h>
 

package/include/micro-os-plus/architecture-riscv/defines.h

@@ -1,17 +1,16 @@
 /*
- * This file is part of the µOS++ distribution.
- *   (https://github.com/micro-os-plus/)
- * Copyright (c) 2017 Liviu Ionescu.
+ * This file is part of the µOS++ project (https://micro-os-plus.github.io/).
+ * Copyright (c) 2017-2026 Liviu Ionescu. All rights reserved.
  *
- * Permission to use, copy, modify, and/or distribute this software
- * for any purpose is hereby granted, under the terms of the MIT license.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose is hereby granted, under the terms of the MIT license.
  *
- * If a copy of the license was not distributed with this file, it can
- * be obtained from https://opensource.org/licenses/MIT/.
+ * If a copy of the license was not distributed with this file, it can be
+ * obtained from https://opensource.org/licenses/mit.
  */
 
-#ifndef MICRO_OS_PLUS_ARCHITECTURE_RISCV_ARCH_DEFINES_H_
-#define MICRO_OS_PLUS_ARCHITECTURE_RISCV_ARCH_DEFINES_H_
+#ifndef MICRO_OS_PLUS_ARCHITECTURE_RISCV_DEFINES_H_
+#define MICRO_OS_PLUS_ARCHITECTURE_RISCV_DEFINES_H_
 
 // ----------------------------------------------------------------------------
 
@@ -45,9 +44,9 @@
 #define DCSR_CAUSE_STEP 4
 #define DCSR_CAUSE_HALT 5
 
-#define MCONTROL_TYPE(xlen) (0xfULL << ((xlen)-4))
-#define MCONTROL_DMODE(xlen) (1ULL << ((xlen)-5))
-#define MCONTROL_MASKMAX(xlen) (0x3fULL << ((xlen)-11))
+#define MCONTROL_TYPE(xlen) (0xfULL << ((xlen) - 4))
+#define MCONTROL_DMODE(xlen) (1ULL << ((xlen) - 5))
+#define MCONTROL_MASKMAX(xlen) (0x3fULL << ((xlen) - 11))
 
 #define MCONTROL_SELECT (1 << 19)
 #define MCONTROL_TIMING (1 << 18)
@@ -129,7 +128,7 @@
 
 // End of SiFive definitions.
 // ----------------------------------------------------------------------------
-#endif
+#endif // 0-1
 
 #define RISCV_CSR_MSTATUS_UIE 0x00000001ul
 #define RISCV_CSR_MSTATUS_SIE 0x00000002ul
@@ -180,6 +179,6 @@
 
 // ----------------------------------------------------------------------------
 
-#endif // MICRO_OS_PLUS_ARCHITECTURE_RISCV_ARCH_DEFINES_H_
+#endif // MICRO_OS_PLUS_ARCHITECTURE_RISCV_DEFINES_H_
 
 // ----------------------------------------------------------------------------

package/include/micro-os-plus/architecture-riscv/device-functions.h

@@ -1,13 +1,12 @@
 /*
- * This file is part of the µOS++ distribution.
- *   (https://github.com/micro-os-plus/)
- * Copyright (c) 2017 Liviu Ionescu.
+ * This file is part of the µOS++ project (https://micro-os-plus.github.io/).
+ * Copyright (c) 2017-2026 Liviu Ionescu. All rights reserved.
  *
- * Permission to use, copy, modify, and/or distribute this software
- * for any purpose is hereby granted, under the terms of the MIT license.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose is hereby granted, under the terms of the MIT license.
  *
- * If a copy of the license was not distributed with this file, it can
- * be obtained from https://opensource.org/licenses/MIT/.
+ * If a copy of the license was not distributed with this file, it can be
+ * obtained from https://opensource.org/licenses/mit.
  */
 
 #ifndef MICRO_OS_PLUS_ARCHITECTURE_RISCV_DEVICE_FUNCTIONS_H_
@@ -15,7 +14,7 @@
 
 // ----------------------------------------------------------------------------
 
-#include <micro-os-plus/architecture-riscv/types.h>
+#include "micro-os-plus/architecture-riscv/types.h"
 
 // ----------------------------------------------------------------------------
 
@@ -24,7 +23,7 @@
  *
  * The declarations are part of the common design, but each device
  * must define the actual address and include the file
- * <micro-os-plus/architecture-riscv/device-functions-inlines.h>.
+ * "micro-os-plus/architecture-riscv/inlines/device-functions-inlines.h".
  */
 
 // ----------------------------------------------------------------------------
@@ -100,7 +99,7 @@ namespace riscv
 {
   namespace device
   {
-    // ----------------------------------------------------------------------------
+    // --------------------------------------------------------------------------
     // `mtime` functions.
 
     /**