@micro-os-plus/architecture-riscv 4.1.0 → 5.0.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/CHANGELOG.md +84 -2
- package/CMakeLists.txt +68 -52
- package/LICENSE +1 -1
- package/README.md +34 -25
- package/include/micro-os-plus/architecture-riscv/core-functions.h +11 -7
- package/include/micro-os-plus/architecture-riscv/csr-functions.h +12 -8
- package/include/micro-os-plus/architecture-riscv/declarations.h +7 -8
- package/include/micro-os-plus/architecture-riscv/defines.h +10 -11
- package/include/micro-os-plus/architecture-riscv/device-functions.h +9 -10
- package/include/micro-os-plus/architecture-riscv/{core-functions-inlines.h → inlines/core-functions-inlines.h} +9 -10
- package/include/micro-os-plus/architecture-riscv/{csr-functions-inlines.h → inlines/csr-functions-inlines.h} +25 -26
- package/include/micro-os-plus/architecture-riscv/{device-functions-inlines.h → inlines/device-functions-inlines.h} +9 -10
- package/include/micro-os-plus/architecture-riscv/{instructions-inlines.h → inlines/instructions-inlines.h} +12 -13
- package/include/micro-os-plus/architecture-riscv/{platform-functions-inlines.h → inlines/platform-functions-inlines.h} +9 -10
- package/include/micro-os-plus/architecture-riscv/inlines/semihosting-inlines.h +46 -0
- package/include/micro-os-plus/architecture-riscv/instructions.h +12 -8
- package/include/micro-os-plus/architecture-riscv/platform-functions.h +6 -7
- package/include/micro-os-plus/architecture-riscv/plic-functions.h +7 -8
- package/include/micro-os-plus/architecture-riscv/types.h +6 -7
- package/include/micro-os-plus/architecture.h +34 -17
- package/linker-scripts/sections-flash.ld +6 -7
- package/linker-scripts/sections-ram.ld +6 -7
- package/meson.build +81 -22
- package/package.json +56 -21
- package/src/semihosting.cpp +58 -0
- package/xcdl-package.jsonc +32 -0
- package/include/micro-os-plus/architecture-riscv/semihosting-inlines.h +0 -79
- package/src/.gitkeep +0 -0
- package/xpack.json +0 -23
package/CHANGELOG.md
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[GitHub](https://github.com/micro-os-plus/architecture-riscv-xpack/issues/)
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and close existing issues and pull requests.
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## 2026-08-04
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* v5.0.0
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## 2026-07-31
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* a172bb5 CHANGELOG update
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* 37a7f6d update guards & includes
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## 2026-07-22
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* 351f4f0 prepare 5.0.0
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* 780394f xcdl export
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* c07d045 re-work includes
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* 98d177f re-generate top commons
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* b79195e re-generate top commons
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* 1a68ac8 extract semihosting.cpp
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* 7f7663c fix copyright notices
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## 2026-06-06
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* 036a3df copyright update 2026
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## 2025-11-20
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* ede63b1 rename npm-pack
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## 2025-10-07
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* 4bcf370 update copyright notices
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## 2023-11-28
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* 8509b6e package.json: cosmetise scripts
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## 2023-10-19
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## 2023-07-14
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* fa45973 package.json: cosmetise urls
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* 5625c25 package.json: minXpm 0.16.2
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## 2023-06-04
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* b1fc258 update for @scope/name
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## 2023-06-03
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* 5a019d3 package.json min 0.16.0
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## 2023-05-08
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* 03d57b0 .npmignore update
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* 1e5a1a6 meson.build cosmetics
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## 2022-08-16
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* a9fb5e2 package.json min 0.14.0 & defaults
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## 2022-08-03
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* d97774b README updates
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* 452f77c .vscode/settings.json: cmake.ignoreCMakeListsMissing
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* 87537f4 .vscode/settings.json: makefile.configureOnOpen
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## 2022-08-02
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* ce9c653 READMEs updates
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## 2022-07-28
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* e5a9bac 4.1.0
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* 6943ac8 prepare v4.1.0
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* e19aa16 #5: remove linker script ARM sections
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* 5f43150 #7: add sections-flash.ld
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* 963be52 #6: rework semihosting_call_host() to avoid asm() registers
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## 2021-02-04
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* v1.1.0
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* first restructured release
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* first restructured release; renamed architecture-riscv
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## 2020-09-19
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package/CMakeLists.txt
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# -----------------------------------------------------------------------------
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# DO NOT EDIT! Automatically generated from template file: xcdl-package.jsonc
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#
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# This file is part of the µOS++
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# Copyright (c) 2021 Liviu Ionescu
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# This file is part of the µOS++ project (https://micro-os-plus.github.io/).
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# Copyright (c) 2021-2026 Liviu Ionescu. All rights reserved.
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# Permission to use, copy, modify, and/or distribute this software
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# Permission to use, copy, modify, and/or distribute this software for any
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# purpose is hereby granted, under the terms of the MIT license.
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#
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# If a copy of the license was not distributed with this file, it can
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# If a copy of the license was not distributed with this file, it can be
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# obtained from https://opensource.org/licenses/mit.
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# -----------------------------------------------------------------------------
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# This file is intended to be used by applications via:
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#
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# `add_subdirectory("xpacks
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# `add_subdirectory("xpacks/@micro-os-plus/architecture-riscv")`
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#
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# ~~~
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# ~~~
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# -----------------------------------------------------------------------------
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## Preamble ##
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project(
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project (
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micro-os-plus-architecture-riscv
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DESCRIPTION "µOS++ RISC-V architecture"
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DESCRIPTION "A source code library with the µOS++ RISC-V architecture port"
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LANGUAGES C CXX ASM
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endif()
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xpack_get_package_name_and_version (
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add_library (
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# None.
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package/LICENSE
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package/README.md
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[](https://www.npmjs.com/package/@micro-os-plus/architecture-riscv/)
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git submodule add https://github.com/micro-os-plus/architecture-riscv-xpack.git \
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xpacks
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xpacks/@micro-os-plus/architecture-riscv
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```
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## Branches
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Apart from the unused `master` branch, there are two active branches:
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- `xpack-development`, with the current development version
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Pull Requests should be directed to this branch.
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When new releases are published, the `xpack-development` branch is merged
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into `xpack`.
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## Developer info
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fixed-function accelerators, various physical memory structures,
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I/O devices, and an interconnect structure to allow the components
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to communicate.
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> fixed-function accelerators, various physical memory structures,
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> to communicate.
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or a synthesised one.
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```
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instruction fetch unit. A RISC-V-compatible core might support
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multiple RISC-V-compatible hardware threads, or harts, through
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multi-threading.
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> instruction fetch unit. A RISC-V-compatible core might support
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> multiple RISC-V-compatible hardware threads, or harts, through
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> multi-threading.
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`riscv::core` namespace.
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in an application is:
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```c
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```
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#### Hart
|
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The header files to be included in user projects are:
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```c++
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#include
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#include "micro-os-plus/architecture.h"
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```
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#### Source files
|
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@@ -246,7 +255,7 @@ To integrate the architecture-riscv source library into a CMake application,
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add this folder to the build:
|
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```cmake
|
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-
add_subdirectory("xpacks
|
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+
add_subdirectory("xpacks/@micro-os-plus/architecture-riscv")`
|
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|
```
|
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The result is an interface library that can be added as an application
|
|
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add this folder to the build:
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```meson
|
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-
subdir('xpacks
|
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+
subdir('xpacks/@micro-os-plus/architecture-riscv')
|
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|
```
|
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The result is a dependency object that can be added
|
|
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According to [semver](https://semver.org) rules:
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> Major version X (X.y.z | X > 0) MUST be incremented if any
|
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backwards incompatible changes are introduced to the public API.
|
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+
> backwards incompatible changes are introduced to the public API.
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The incompatible changes, in reverse chronological order,
|
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are:
|
|
@@ -311,7 +320,7 @@ are:
|
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## License
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[MIT License](https://opensource.org/licenses/
|
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+
Unless otherwise stated, the content is released under the terms of the
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+
[MIT License](https://opensource.org/licenses/mit),
|
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with all rights reserved to
|
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-
[Liviu Ionescu](https://github.com/ilg-ul
|
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+
[Liviu Ionescu](https://github.com/ilg-ul).
|
|
@@ -1,13 +1,12 @@
|
|
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1
1
|
/*
|
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2
|
-
* This file is part of the µOS++
|
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|
-
*
|
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4
|
-
* Copyright (c) 2017 Liviu Ionescu.
|
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|
+
* This file is part of the µOS++ project (https://micro-os-plus.github.io/).
|
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|
+
* Copyright (c) 2017-2026 Liviu Ionescu. All rights reserved.
|
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4
|
*
|
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6
|
-
* Permission to use, copy, modify, and/or distribute this software
|
|
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|
-
*
|
|
5
|
+
* Permission to use, copy, modify, and/or distribute this software for any
|
|
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|
+
* purpose is hereby granted, under the terms of the MIT license.
|
|
8
7
|
*
|
|
9
|
-
* If a copy of the license was not distributed with this file, it can
|
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|
-
*
|
|
8
|
+
* If a copy of the license was not distributed with this file, it can be
|
|
9
|
+
* obtained from https://opensource.org/licenses/mit.
|
|
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10
|
*/
|
|
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11
|
|
|
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|
#ifndef MICRO_OS_PLUS_ARCHITECTURE_RISCV_CORE_FUNCTIONS_H_
|
|
@@ -98,6 +97,11 @@ namespace riscv
|
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#endif // defined(__cplusplus)
|
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// ============================================================================
|
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+
// Templates, inlines & constexpr implementations.
|
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+
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+
#include "inlines/core-functions-inlines.h"
|
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+
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// ----------------------------------------------------------------------------
|
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#endif // MICRO_OS_PLUS_ARCHITECTURE_RISCV_CORE_FUNCTIONS_H_
|
|
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|
|
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1
|
/*
|
|
2
|
-
* This file is part of the µOS++
|
|
3
|
-
*
|
|
4
|
-
* Copyright (c) 2017 Liviu Ionescu.
|
|
2
|
+
* This file is part of the µOS++ project (https://micro-os-plus.github.io/).
|
|
3
|
+
* Copyright (c) 2017-2026 Liviu Ionescu. All rights reserved.
|
|
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4
|
*
|
|
6
|
-
* Permission to use, copy, modify, and/or distribute this software
|
|
7
|
-
*
|
|
5
|
+
* Permission to use, copy, modify, and/or distribute this software for any
|
|
6
|
+
* purpose is hereby granted, under the terms of the MIT license.
|
|
8
7
|
*
|
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9
|
-
* If a copy of the license was not distributed with this file, it can
|
|
10
|
-
*
|
|
8
|
+
* If a copy of the license was not distributed with this file, it can be
|
|
9
|
+
* obtained from https://opensource.org/licenses/mit.
|
|
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10
|
*/
|
|
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|
|
|
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|
#ifndef MICRO_OS_PLUS_ARCHITECTURE_RISCV_CSR_FUNCTIONS_H_
|
|
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|
|
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14
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|
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16
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// ----------------------------------------------------------------------------
|
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|
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#include
|
|
17
|
+
#include "micro-os-plus/architecture-riscv/types.h"
|
|
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18
|
|
|
20
19
|
// ----------------------------------------------------------------------------
|
|
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|
// RISC-V CSR support functions.
|
|
@@ -234,6 +233,11 @@ namespace riscv
|
|
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|
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|
#endif // defined(__cplusplus)
|
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|
|
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// ============================================================================
|
|
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|
+
// Templates, inlines & constexpr implementations.
|
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|
+
|
|
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|
+
#include "inlines/csr-functions-inlines.h"
|
|
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|
+
|
|
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|
// ----------------------------------------------------------------------------
|
|
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|
|
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|
#endif // MICRO_OS_PLUS_ARCHITECTURE_RISCV_CSR_FUNCTIONS_H_
|
|
@@ -1,13 +1,12 @@
|
|
|
1
1
|
/*
|
|
2
|
-
* This file is part of the µOS++
|
|
3
|
-
*
|
|
4
|
-
* Copyright (c) 2017 Liviu Ionescu.
|
|
2
|
+
* This file is part of the µOS++ project (https://micro-os-plus.github.io/).
|
|
3
|
+
* Copyright (c) 2017-2026 Liviu Ionescu. All rights reserved.
|
|
5
4
|
*
|
|
6
|
-
* Permission to use, copy, modify, and/or distribute this software
|
|
7
|
-
*
|
|
5
|
+
* Permission to use, copy, modify, and/or distribute this software for any
|
|
6
|
+
* purpose is hereby granted, under the terms of the MIT license.
|
|
8
7
|
*
|
|
9
|
-
* If a copy of the license was not distributed with this file, it can
|
|
10
|
-
*
|
|
8
|
+
* If a copy of the license was not distributed with this file, it can be
|
|
9
|
+
* obtained from https://opensource.org/licenses/mit.
|
|
11
10
|
*/
|
|
12
11
|
|
|
13
12
|
#ifndef MICRO_OS_PLUS_ARCHITECTURE_RISCV_ARCH_DECLARATIONS_H_
|
|
@@ -15,7 +14,7 @@
|
|
|
15
14
|
|
|
16
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|
// ----------------------------------------------------------------------------
|
|
17
16
|
|
|
18
|
-
#include
|
|
17
|
+
#include "micro-os-plus/architecture-riscv/types.h"
|
|
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18
|
|
|
20
19
|
#include <stdint.h>
|
|
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20
|
|
|
@@ -1,13 +1,12 @@
|
|
|
1
1
|
/*
|
|
2
|
-
* This file is part of the µOS++
|
|
3
|
-
*
|
|
4
|
-
* Copyright (c) 2017 Liviu Ionescu.
|
|
2
|
+
* This file is part of the µOS++ project (https://micro-os-plus.github.io/).
|
|
3
|
+
* Copyright (c) 2017-2026 Liviu Ionescu. All rights reserved.
|
|
5
4
|
*
|
|
6
|
-
* Permission to use, copy, modify, and/or distribute this software
|
|
7
|
-
*
|
|
5
|
+
* Permission to use, copy, modify, and/or distribute this software for any
|
|
6
|
+
* purpose is hereby granted, under the terms of the MIT license.
|
|
8
7
|
*
|
|
9
|
-
* If a copy of the license was not distributed with this file, it can
|
|
10
|
-
*
|
|
8
|
+
* If a copy of the license was not distributed with this file, it can be
|
|
9
|
+
* obtained from https://opensource.org/licenses/mit.
|
|
11
10
|
*/
|
|
12
11
|
|
|
13
12
|
#ifndef MICRO_OS_PLUS_ARCHITECTURE_RISCV_ARCH_DEFINES_H_
|
|
@@ -45,9 +44,9 @@
|
|
|
45
44
|
#define DCSR_CAUSE_STEP 4
|
|
46
45
|
#define DCSR_CAUSE_HALT 5
|
|
47
46
|
|
|
48
|
-
#define MCONTROL_TYPE(xlen) (0xfULL << ((xlen)-4))
|
|
49
|
-
#define MCONTROL_DMODE(xlen) (1ULL << ((xlen)-5))
|
|
50
|
-
#define MCONTROL_MASKMAX(xlen) (0x3fULL << ((xlen)-11))
|
|
47
|
+
#define MCONTROL_TYPE(xlen) (0xfULL << ((xlen) - 4))
|
|
48
|
+
#define MCONTROL_DMODE(xlen) (1ULL << ((xlen) - 5))
|
|
49
|
+
#define MCONTROL_MASKMAX(xlen) (0x3fULL << ((xlen) - 11))
|
|
51
50
|
|
|
52
51
|
#define MCONTROL_SELECT (1 << 19)
|
|
53
52
|
#define MCONTROL_TIMING (1 << 18)
|
|
@@ -129,7 +128,7 @@
|
|
|
129
128
|
|
|
130
129
|
// End of SiFive definitions.
|
|
131
130
|
// ----------------------------------------------------------------------------
|
|
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|
-
#endif
|
|
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|
+
#endif // 0-1
|
|
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132
|
|
|
134
133
|
#define RISCV_CSR_MSTATUS_UIE 0x00000001ul
|
|
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134
|
#define RISCV_CSR_MSTATUS_SIE 0x00000002ul
|
|
@@ -1,13 +1,12 @@
|
|
|
1
1
|
/*
|
|
2
|
-
* This file is part of the µOS++
|
|
3
|
-
*
|
|
4
|
-
* Copyright (c) 2017 Liviu Ionescu.
|
|
2
|
+
* This file is part of the µOS++ project (https://micro-os-plus.github.io/).
|
|
3
|
+
* Copyright (c) 2017-2026 Liviu Ionescu. All rights reserved.
|
|
5
4
|
*
|
|
6
|
-
* Permission to use, copy, modify, and/or distribute this software
|
|
7
|
-
*
|
|
5
|
+
* Permission to use, copy, modify, and/or distribute this software for any
|
|
6
|
+
* purpose is hereby granted, under the terms of the MIT license.
|
|
8
7
|
*
|
|
9
|
-
* If a copy of the license was not distributed with this file, it can
|
|
10
|
-
*
|
|
8
|
+
* If a copy of the license was not distributed with this file, it can be
|
|
9
|
+
* obtained from https://opensource.org/licenses/mit.
|
|
11
10
|
*/
|
|
12
11
|
|
|
13
12
|
#ifndef MICRO_OS_PLUS_ARCHITECTURE_RISCV_DEVICE_FUNCTIONS_H_
|
|
@@ -15,7 +14,7 @@
|
|
|
15
14
|
|
|
16
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|
// ----------------------------------------------------------------------------
|
|
17
16
|
|
|
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|
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#include
|
|
17
|
+
#include "micro-os-plus/architecture-riscv/types.h"
|
|
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18
|
|
|
20
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|
// ----------------------------------------------------------------------------
|
|
21
20
|
|
|
@@ -24,7 +23,7 @@
|
|
|
24
23
|
*
|
|
25
24
|
* The declarations are part of the common design, but each device
|
|
26
25
|
* must define the actual address and include the file
|
|
27
|
-
*
|
|
26
|
+
* "micro-os-plus/architecture-riscv/inlines/device-functions-inlines.h".
|
|
28
27
|
*/
|
|
29
28
|
|
|
30
29
|
// ----------------------------------------------------------------------------
|
|
@@ -100,7 +99,7 @@ namespace riscv
|
|
|
100
99
|
{
|
|
101
100
|
namespace device
|
|
102
101
|
{
|
|
103
|
-
//
|
|
102
|
+
// --------------------------------------------------------------------------
|
|
104
103
|
// `mtime` functions.
|
|
105
104
|
|
|
106
105
|
/**
|
|
@@ -1,17 +1,16 @@
|
|
|
1
1
|
/*
|
|
2
|
-
* This file is part of the µOS++
|
|
3
|
-
*
|
|
4
|
-
* Copyright (c) 2017 Liviu Ionescu.
|
|
2
|
+
* This file is part of the µOS++ project (https://micro-os-plus.github.io/).
|
|
3
|
+
* Copyright (c) 2017-2026 Liviu Ionescu. All rights reserved.
|
|
5
4
|
*
|
|
6
|
-
* Permission to use, copy, modify, and/or distribute this software
|
|
7
|
-
*
|
|
5
|
+
* Permission to use, copy, modify, and/or distribute this software for any
|
|
6
|
+
* purpose is hereby granted, under the terms of the MIT license.
|
|
8
7
|
*
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9
|
-
* If a copy of the license was not distributed with this file, it can
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10
|
-
*
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8
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+
* If a copy of the license was not distributed with this file, it can be
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9
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+
* obtained from https://opensource.org/licenses/mit.
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11
10
|
*/
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12
11
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13
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-
#ifndef
|
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14
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-
#define
|
|
12
|
+
#ifndef MICRO_OS_PLUS_ARCHITECTURE_RISCV_INLINES_CORE_FUNCTIONS_INLINES_H_
|
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13
|
+
#define MICRO_OS_PLUS_ARCHITECTURE_RISCV_INLINES_CORE_FUNCTIONS_INLINES_H_
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15
14
|
|
|
16
15
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// ----------------------------------------------------------------------------
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17
16
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@@ -81,6 +80,6 @@ namespace riscv
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81
80
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|
82
81
|
// ----------------------------------------------------------------------------
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83
82
|
|
|
84
|
-
#endif //
|
|
83
|
+
#endif // MICRO_OS_PLUS_ARCHITECTURE_RISCV_INLINES_CORE_FUNCTIONS_INLINES_H_
|
|
85
84
|
|
|
86
85
|
// ----------------------------------------------------------------------------
|