@kernaut/kernaut-resources 0.1.17-beta.1 → 0.1.18

package/resources/kop-2026-10-23-0.1.17-beta.1/product_capabilities/kernel_optflow/skills/KernelWiki-private/wiki/nvidia/hardware/tma.md

@@ -1,387 +0,0 @@
----
-id: hw-tma
-title: Tensor Memory Accelerator (TMA)
-type: hardware
-architectures:
-- sm100
-- sm100a
-- sm90
-- sm90a
-languages:
-- '*'
-tags:
-- tma
-- mbarrier
-confidence: source-reported
-evidence_level: spec
-related:
-- hw-tcgen05-mma
-- technique-pipeline-stages
-- technique-swizzling
-sources:
-- doc-nvidia-tuning-guide
-- blog-tcgen05-tutorial
-- pr-flashinfer-2387
-aliases:
-- TMA
-- tensor memory accelerator
-- cp.async.bulk
----
-# Tensor Memory Accelerator (TMA)
-
-## Overview
-
-The Tensor Memory Accelerator (TMA) is a hardware unit that performs **asynchronous bulk data transfers** between global memory and shared memory. First introduced on Hopper (SM90), TMA carries forward to Blackwell (SM100) with stricter requirements for tcgen05 compatibility.
-
-TMA offloads data movement from CUDA cores entirely -- a single thread issues the transfer, and the TMA hardware engine handles the multi-dimensional copy, address calculation, out-of-bounds clamping, and format conversion.
-
-## Key Properties
-
-| Property | Detail |
-|---|---|
-| Transfer direction | GMEM <-> SMEM (bidirectional) |
-| Dimensionality | 1D to 5D tensor copies |
-| Max transfer size | Up to 256 bytes per element, tiles up to 128x256 |
-| Swizzle modes | None, 32B, 64B, 128B (128B required for tcgen05) |
-| Format conversion | FP32<->BF16, FP32<->FP16 during transfer |
-| Multicast | Single GMEM tile -> multiple CTAs in a cluster |
-| Synchronization | mbarrier-based (arrive/wait) |
-| Thread requirement | Single thread issues the operation |
-
-## TMA Descriptor
-
-TMA operations are driven by a **descriptor** that encodes the tensor layout, addressing, and transfer parameters. The descriptor is created on the host and passed to the kernel.
-
-### Host-Side Descriptor Creation
-
-```cuda
-#include <cuda.h>
-
-// Create a 2D TMA descriptor for a row-major FP16 matrix
-CUtensorMap create_tma_descriptor_2d(
-    const half* global_ptr,
-    int M, int N,           // Global tensor dimensions
-    int tile_m, int tile_n, // Tile dimensions for each transfer
-    int swizzle_bytes       // Swizzle mode: 0, 32, 64, 128
-) {
-    CUtensorMap tensor_map;
-
-    // Tensor dimensions (outermost to innermost)
-    uint64_t global_dims[2] = {(uint64_t)N, (uint64_t)M};
-    uint64_t global_strides[1] = {(uint64_t)(N * sizeof(half))};
-
-    // Tile box dimensions
-    uint32_t box_dims[2] = {(uint32_t)tile_n, (uint32_t)tile_m};
-
-    // Element strides (1 = contiguous)
-    uint32_t elem_strides[2] = {1, 1};
-
-    CUtensorMapSwizzle swizzle;
-    switch (swizzle_bytes) {
-        case 0:   swizzle = CU_TENSOR_MAP_SWIZZLE_NONE; break;
-        case 32:  swizzle = CU_TENSOR_MAP_SWIZZLE_32B; break;
-        case 64:  swizzle = CU_TENSOR_MAP_SWIZZLE_64B; break;
-        case 128: swizzle = CU_TENSOR_MAP_SWIZZLE_128B; break;
-    }
-
-    cuTensorMapEncodeTiled(
-        &tensor_map,
-        CU_TENSOR_MAP_DATA_TYPE_FLOAT16,  // Element type
-        2,                                  // Dimensionality
-        (void*)global_ptr,                 // Global pointer
-        global_dims,                       // Tensor dimensions
-        global_strides,                    // Byte strides (exclude innermost)
-        box_dims,                          // Tile/box dimensions
-        elem_strides,                      // Element strides
-        CU_TENSOR_MAP_INTERLEAVE_NONE,
-        swizzle,
-        CU_TENSOR_MAP_L2_PROMOTION_NONE,
-        CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE
-    );
-
-    return tensor_map;
-}
-```
-
-### Blackwell Requirement: 128-Byte Swizzle
-
-On Blackwell, `tcgen05.mma` requires operands in **128-byte swizzled** SMEM layout. If TMA loads data without 128B swizzling, the MMA will produce incorrect results.
-
-```cuda
-// CORRECT for Blackwell tcgen05:
-CUtensorMap desc = create_tma_descriptor_2d(ptr, M, N, 128, 64, 128);
-//                                                     swizzle=128 ^^^
-
-// WRONG for tcgen05 (will silently produce garbage):
-CUtensorMap desc = create_tma_descriptor_2d(ptr, M, N, 128, 64, 0);
-//                                                     swizzle=0 ^^^
-```
-
-## Asynchronous Copy Operations
-
-### GMEM to SMEM (Load)
-
-```cuda
-// TMA load: single thread issues, hardware executes asynchronously
-__device__ void tma_load_tile(
-    const CUtensorMap* desc,
-    void* smem_ptr,
-    uint64_t* mbar_ptr,  // mbarrier for synchronization
-    int coord_x, int coord_y
-) {
-    if (threadIdx.x == 0) {
-        // Set expected bytes on the mbarrier
-        uint32_t expected_bytes = TILE_M * TILE_N * sizeof(half);
-        asm volatile(
-            "mbarrier.arrive.expect_tx.shared.b64 _, [%0], %1;"
-            :
-            : "r"((uint32_t)__cvta_generic_to_shared(mbar_ptr)),
-              "r"(expected_bytes)
-        );
-
-        // Issue TMA copy
-        asm volatile(
-            "cp.async.bulk.tensor.2d.shared::cluster.global.mbarrier::complete_tx::bytes "
-            "[%0], [%1, {%2, %3}], [%4];"
-            :
-            : "r"((uint32_t)__cvta_generic_to_shared(smem_ptr)),
-              "l"(desc),
-              "r"(coord_x), "r"(coord_y),
-              "r"((uint32_t)__cvta_generic_to_shared(mbar_ptr))
-        );
-    }
-}
-```
-
-### SMEM to GMEM (Store)
-
-```cuda
-// TMA store: write a tile from shared memory back to global memory
-__device__ void tma_store_tile(
-    const CUtensorMap* desc,
-    const void* smem_ptr,
-    int coord_x, int coord_y
-) {
-    if (threadIdx.x == 0) {
-        asm volatile(
-            "cp.async.bulk.tensor.2d.global.shared::cta "
-            "[%0, {%1, %2}], [%3];"
-            :
-            : "l"(desc),
-              "r"(coord_x), "r"(coord_y),
-              "r"((uint32_t)__cvta_generic_to_shared(smem_ptr))
-        );
-
-        // Commit the store
-        asm volatile("cp.async.bulk.commit_group;");
-    }
-}
-```
-
-## mbarrier Synchronization
-
-TMA uses mbarriers (memory barriers) for producer-consumer synchronization. The pattern is:
-
-1. **Producer** (TMA): arrives at the barrier when the transfer completes, decrementing the expected transaction count.
-2. **Consumer** (compute warps): waits on the barrier before reading the loaded data.
-
-### Pipeline Stage Pattern
-
-```cuda
-// Multi-stage pipeline with TMA + mbarrier
-__device__ void pipelined_mainloop(
-    const CUtensorMap* desc_a,
-    const CUtensorMap* desc_b,
-    void* smem_a_stages[NUM_STAGES],
-    void* smem_b_stages[NUM_STAGES],
-    uint64_t* mbar[NUM_STAGES],
-    int num_k_tiles
-) {
-    // Prologue: fill the first NUM_STAGES-1 stages
-    for (int s = 0; s < NUM_STAGES - 1 && s < num_k_tiles; ++s) {
-        tma_load_tile(desc_a, smem_a_stages[s], mbar[s], 0, s);
-        tma_load_tile(desc_b, smem_b_stages[s], mbar[s], s, 0);
-    }
-
-    // Mainloop
-    for (int k = 0; k < num_k_tiles; ++k) {
-        int stage = k % NUM_STAGES;
-
-        // Wait for data to arrive in this stage
-        mbarrier_wait(mbar[stage]);
-
-        // Issue MMA using this stage's SMEM buffers
-        if (threadIdx.x == 0) {
-            asm volatile(
-                "tcgen05.mma.cta_group::1.kind::f16 "
-                "[%0], %1, %2, %3, 1;"
-                :
-                : "r"(tmem_acc),
-                  "l"(make_desc(smem_a_stages[stage])),
-                  "l"(make_desc(smem_b_stages[stage])),
-                  "r"(0)
-            );
-        }
-
-        // Prefetch next stage
-        int next_k = k + NUM_STAGES - 1;
-        if (next_k < num_k_tiles) {
-            int next_stage = next_k % NUM_STAGES;
-            tma_load_tile(desc_a, smem_a_stages[next_stage],
-                         mbar[next_stage], 0, next_k);
-            tma_load_tile(desc_b, smem_b_stages[next_stage],
-                         mbar[next_stage], next_k, 0);
-        }
-    }
-}
-```
-
-### mbarrier Operations
-
-```cuda
-// Initialize an mbarrier
-__device__ void mbarrier_init(uint64_t* mbar, int arrive_count) {
-    if (threadIdx.x == 0) {
-        asm volatile(
-            "mbarrier.init.shared.b64 [%0], %1;"
-            :
-            : "r"((uint32_t)__cvta_generic_to_shared(mbar)),
-              "r"(arrive_count)
-        );
-    }
-}
-
-// Wait for an mbarrier to complete (phase-based)
-__device__ void mbarrier_wait(uint64_t* mbar, int phase) {
-    uint32_t mbar_addr = (uint32_t)__cvta_generic_to_shared(mbar);
-    asm volatile(
-        "{\n"
-        ".reg .pred p;\n"
-        "WAIT_LOOP:\n"
-        "mbarrier.try_wait.parity.shared.b64 p, [%0], %1;\n"
-        "@!p bra WAIT_LOOP;\n"
-        "}\n"
-        :
-        : "r"(mbar_addr), "r"(phase)
-    );
-}
-```
-
-## TMA Multicast
-
-TMA multicast sends a single GMEM tile to **multiple CTAs within a cluster** simultaneously. This is critical for GEMM where the B operand is shared across M-axis tiles.
-
-```cuda
-// Multicast TMA: load B tile to all CTAs in the cluster
-__device__ void tma_multicast_load(
-    const CUtensorMap* desc,
-    void* smem_ptr,
-    uint64_t* mbar_ptr,
-    int coord_x, int coord_y,
-    uint16_t multicast_mask  // bitmask: which CTAs in cluster receive the data
-) {
-    if (threadIdx.x == 0) {
-        uint32_t expected_bytes = TILE_K * TILE_N * sizeof(half);
-        asm volatile(
-            "mbarrier.arrive.expect_tx.shared.b64 _, [%0], %1;"
-            :
-            : "r"((uint32_t)__cvta_generic_to_shared(mbar_ptr)),
-              "r"(expected_bytes)
-        );
-
-        asm volatile(
-            "cp.async.bulk.tensor.2d.shared::cluster.global.mbarrier::complete_tx::bytes.multicast::cluster "
-            "[%0], [%1, {%2, %3}], [%4], %5;"
-            :
-            : "r"((uint32_t)__cvta_generic_to_shared(smem_ptr)),
-              "l"(desc),
-              "r"(coord_x), "r"(coord_y),
-              "r"((uint32_t)__cvta_generic_to_shared(mbar_ptr)),
-              "h"(multicast_mask)
-        );
-    }
-}
-```
-
-### Multicast in GEMM
-
-```
-Cluster: 2 CTAs (CTA0 and CTA1) each computing different M-tiles of the same N column
-
-CTA0: computes C[0:128, 0:256]   -- needs A[0:128, :] and B[:, 0:256]
-CTA1: computes C[128:256, 0:256] -- needs A[128:256, :] and B[:, 0:256]
-
-B[:, 0:256] is SHARED -- multicast it once from GMEM to both CTAs
-A tiles are UNIQUE -- each CTA loads its own A tile
-
-Result: B bandwidth is halved (1 GMEM read serves 2 CTAs)
-```
-
-## Blackwell-Specific Enhancements
-
-### 128-Byte Swizzle for tcgen05
-
-All TMA loads feeding `tcgen05.mma` must use 128-byte swizzling. The swizzle pattern rearranges bytes within each 128-byte line to match the tensor core's internal data layout:
-
-```
-Without swizzle (linear):
-  Row 0: bytes [0, 1, 2, ..., 127]
-  Row 1: bytes [128, 129, ..., 255]
-
-With 128B swizzle:
-  Row 0: bytes [0, 1, ..., 127]     (unchanged)
-  Row 1: bytes [128, 129, ..., 255] XOR pattern applied
-  Row 2: bytes [256, ...] XOR pattern applied differently
-  ...
-```
-
-The swizzle eliminates bank conflicts when the tensor core reads operand tiles from SMEM.
-
-### TMA + TMEM Integration
-
-On Blackwell, data flows through a characteristic pipeline:
-
-```
-GMEM --[TMA]--> SMEM --[tcgen05.mma]--> TMEM --[tcgen05.ld]--> Registers --[st.global]--> GMEM
-                  ^                        |
-                  |                        v
-                  +---- (epilogue) --------+
-                        (bias, activation, etc.)
-```
-
-## Performance Considerations
-
-| Tip | Detail |
-|---|---|
-| Maximize TMA utilization | Keep the TMA unit busy with back-to-back loads across pipeline stages |
-| Use multicast for shared operands | Reduces GMEM bandwidth by cluster_size x for shared tiles |
-| Always use 128B swizzle on Blackwell | Non-128B swizzle produces incorrect tcgen05 results |
-| Prefer 2D TMA over manual addressing | TMA handles out-of-bounds clamping, padding, and strided access |
-| Pipeline depth | 3-5 stages typically optimal; more stages increase SMEM usage |
-
-## CuTe-DSL Example
-
-```python
-# CuTe-DSL TMA copy setup for Blackwell GEMM
-from cute import *
-
-# Define TMA copy atom for operand A (BF16, 128x64 tile)
-tma_a = make_tma_copy(
-    SM100_TMA_LOAD_2D,
-    tensor_a,                      # global tensor
-    smem_layout_a,                 # shared memory layout
-    tile_shape=(128, 64),          # tile dimensions
-    swizzle=Swizzle(7, 0, 4),     # 128-byte swizzle
-    multicast_mask=None            # no multicast for A
-)
-
-# Define TMA copy atom for operand B with multicast
-tma_b = make_tma_copy(
-    SM100_TMA_LOAD_2D_MULTICAST,
-    tensor_b,
-    smem_layout_b,
-    tile_shape=(64, 256),
-    swizzle=Swizzle(7, 0, 4),     # 128-byte swizzle
-    multicast_mask=cluster_mask    # multicast B to all CTAs in cluster
-)
-```

package/resources/kop-2026-10-23-0.1.17-beta.1/product_capabilities/kernel_optflow/skills/KernelWiki-private/wiki/nvidia/hardware/tmem.md

@@ -1,321 +0,0 @@
----
-id: hw-tmem
-title: "Tensor Memory (TMEM)"
-type: hardware
-architectures: [sm100, sm100a]
-languages:
-- '*'
-tags: [tmem, tcgen05]
-confidence: verified
-evidence_level: spec
-evidence_basis:
-  - source_id: doc-nvidia-tuning-guide
-    evidence_type: official-doc
-  - source_id: pr-cutlass-2139
-    evidence_type: upstream-code
-related: [hw-tcgen05-mma, technique-double-buffering, pattern-register-pressure]
-sources: [pr-cutlass-2139, doc-nvidia-tuning-guide, blog-tcgen05-tutorial, blog-colfax-cutlass]
-aliases: [TMEM, "tensor memory", "Tensor Memory"]
----
-
-# Tensor Memory (TMEM)
-
-## Overview
-
-Tensor Memory (TMEM) is a new addressable memory space introduced in the Blackwell architecture (SM100). Each SM contains **256KB of dedicated TMEM**, used primarily as the accumulator storage for `tcgen05.mma` operations. TMEM eliminates the register pressure that plagued Hopper's wgmma, where accumulators consumed 128+ registers per warpgroup.
-
-## Architecture Layout
-
-TMEM is organized as a 2D matrix:
-
-| Dimension | Size | Description |
-|---|---|---|
-| Rows | 128 | Mapped to warp lanes (4 warps x 32 lanes) |
-| Columns | 512 | 32-bit (4-byte) elements per row |
-| Total | 128 x 512 x 4 bytes = 256 KB | Per-SM capacity |
-
-### Row-to-Lane Mapping
-
-TMEM rows are mapped to warp lanes within a CTA:
-
-```
-Row 0-31:   Warp 0, lanes 0-31
-Row 32-63:  Warp 1, lanes 0-31
-Row 64-95:  Warp 2, lanes 0-31
-Row 96-127: Warp 3, lanes 0-31
-```
-
-Each thread "owns" the TMEM row corresponding to its warp and lane. When reading from TMEM, thread `T` in warp `W` accesses row `W*32 + T%32`.
-
-### Column Addressing
-
-Columns are addressed via a column offset in the TMEM descriptor. A 128x256 MMA accumulator tile occupies:
-
-- 128 rows (all lanes across 4 warps)
-- 256 columns of FP32 values = 1024 bytes per row
-
-```
-TMEM Layout for 128x256 FP32 accumulator:
-  col 0        col 255     col 511
-  |------------|-----------|-----------|
-  |  Acc Tile  |  (free)   |  (free)   |  row 0   (warp0, lane0)
-  |  128x256   |           |           |  row 1   (warp0, lane1)
-  |  FP32      |           |           |  ...
-  |            |           |           |  row 127  (warp3, lane31)
-  |------------|-----------|-----------|
-```
-
-## Allocation and Deallocation Lifecycle
-
-TMEM is **explicitly managed** by the programmer. There is no automatic allocation or garbage collection.
-
-### Allocation
-
-```cuda
-// Shared storage for CTA-wide broadcast of TMEM address
-__shared__ uint32_t s_tmem_addr;
-
-__device__ uint32_t tmem_alloc_cta(uint32_t num_cols) {
-    // Only thread 0 allocates; result must reach ALL warps in the CTA.
-    // __shfl_sync is warp-local — it cannot broadcast across warps.
-    if (threadIdx.x == 0) {
-        uint32_t addr;
-        asm volatile(
-            "tcgen05.alloc.cta_group::1.sync.aligned.b32 %0, %1;"
-            : "=r"(addr)
-            : "r"(num_cols)
-        );
-        s_tmem_addr = addr;
-    }
-    __syncthreads();  // All warps now see s_tmem_addr
-    return s_tmem_addr;
-}
-```
-
-Key points:
-- `num_cols` specifies the number of 32-bit columns to allocate.
-- A 128x256 FP32 accumulator needs 256 columns.
-- Allocation is **CTA-scoped** -- all threads in the CTA share the same TMEM region.
-- Only one thread (typically thread 0) issues the allocation.
-- The returned `tmem_addr` is the base column index.
-
-### Deallocation
-
-```cuda
-__device__ void tmem_dealloc(uint32_t tmem_addr, uint32_t num_cols) {
-    if (threadIdx.x == 0) {
-        asm volatile(
-            "tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;"
-            :
-            : "r"(tmem_addr), "r"(num_cols)
-        );
-    }
-    __syncthreads();
-}
-```
-
-**Warning**: Failure to deallocate TMEM before CTA exit will leak memory and prevent subsequent CTAs from allocating, leading to hangs in persistent kernels.
-
-### Lifecycle in a Persistent GEMM Kernel
-
-```cuda
-__global__ void persistent_gemm_kernel(/* ... */) {
-    // 1. Allocate TMEM for accumulators
-    uint32_t tmem_acc = tmem_alloc(256);  // 256 cols for M=128, N=256
-
-    while (has_more_tiles()) {
-        // 2. Zero-initialize TMEM accumulator
-        tmem_zero(tmem_acc, 256);
-
-        // 3. Mainloop: accumulate K tiles
-        for (int k = 0; k < K_tiles; ++k) {
-            issue_tcgen05_mma(tmem_acc, smem_a[k], smem_b[k]);
-        }
-
-        // 4. Fence and read results
-        asm volatile("tcgen05.mma.fence::before_thread_sync;");
-        __syncthreads();
-
-        // 5. Epilogue: read from TMEM, apply bias/activation, write to GMEM
-        epilogue_from_tmem(tmem_acc, output);
-
-        // 6. TMEM persists across tiles -- no need to reallocate
-    }
-
-    // 7. Deallocate before exit
-    tmem_dealloc(tmem_acc, 256);
-}
-```
-
-## Data Movement Operations
-
-### TMEM Store (Register to TMEM)
-
-```cuda
-// Store a register value to TMEM
-// Each thread writes to its own TMEM row at the specified column
-__device__ void tmem_store_f32(uint32_t tmem_col, float value) {
-    asm volatile(
-        "tcgen05.st.sync.aligned.32x1b.x1.b32 [%0], {%1};"
-        :
-        : "r"(tmem_col), "f"(value)
-    );
-}
-
-// Vectorized store: 4 consecutive FP32 values
-__device__ void tmem_store_f32x4(uint32_t tmem_col, float4 values) {
-    asm volatile(
-        "tcgen05.st.sync.aligned.32x1b.x4.b32 [%0], {%1, %2, %3, %4};"
-        :
-        : "r"(tmem_col),
-          "f"(values.x), "f"(values.y),
-          "f"(values.z), "f"(values.w)
-    );
-}
-```
-
-### TMEM Load (TMEM to Register)
-
-```cuda
-// Load a single FP32 from TMEM
-__device__ float tmem_load_f32(uint32_t tmem_col) {
-    float result;
-    asm volatile(
-        "tcgen05.ld.sync.aligned.32x1b.x1.b32 {%0}, [%1];"
-        : "=f"(result)
-        : "r"(tmem_col)
-    );
-    return result;
-}
-
-// Vectorized load: 4 consecutive FP32 values
-__device__ float4 tmem_load_f32x4(uint32_t tmem_col) {
-    float4 result;
-    asm volatile(
-        "tcgen05.ld.sync.aligned.32x1b.x4.b32 {%0, %1, %2, %3}, [%4];"
-        : "=f"(result.x), "=f"(result.y),
-          "=f"(result.z), "=f"(result.w)
-        : "r"(tmem_col)
-    );
-    return result;
-}
-```
-
-### TMEM Zero-Fill
-
-```cuda
-// Zero-fill a range of TMEM columns
-__device__ void tmem_zero(uint32_t tmem_base_col, uint32_t num_cols) {
-    // Each thread zeros its own row
-    for (uint32_t c = 0; c < num_cols; c += 4) {
-        float4 zero = make_float4(0.f, 0.f, 0.f, 0.f);
-        tmem_store_f32x4(tmem_base_col + c, zero);
-    }
-}
-```
-
-### Bulk TMEM Copy via tcgen05.cp
-
-TMEM supports bulk copy operations between TMEM regions:
-
-```ptx
-// Copy 256 columns of TMEM from src to dst
-tcgen05.cp.cta_group::1.b128 [dst_tmem_col], [src_tmem_col];
-```
-
-## Double-Buffering with TMEM
-
-Double-buffering TMEM accumulators enables overlapping the epilogue of the current tile with the MMA accumulation of the next tile:
-
-```cuda
-__global__ void double_buffered_gemm(/* ... */) {
-    // Allocate two accumulator buffers
-    uint32_t tmem_acc[2];
-    tmem_acc[0] = tmem_alloc(256);
-    tmem_acc[1] = tmem_alloc(256);
-
-    int buf = 0;
-
-    for (int tile = 0; tile < num_tiles; ++tile) {
-        // Zero the current buffer
-        tmem_zero(tmem_acc[buf], 256);
-
-        // Mainloop: accumulate into current buffer
-        for (int k = 0; k < K_tiles; ++k) {
-            issue_tcgen05_mma(tmem_acc[buf], smem_a[k], smem_b[k]);
-        }
-        asm volatile("tcgen05.mma.fence::before_thread_sync;");
-        __syncthreads();
-
-        // If not the first tile, the *other* buffer's epilogue
-        // was overlapped with this tile's MMA in the pipeline.
-
-        // Start epilogue for current buffer
-        // (can overlap with next tile's MMA on the other buffer)
-        epilogue_from_tmem(tmem_acc[buf], output_tile[tile]);
-
-        buf ^= 1;  // Swap buffers
-    }
-
-    // Cleanup
-    tmem_dealloc(tmem_acc[0], 256);
-    tmem_dealloc(tmem_acc[1], 256);
-}
-```
-
-### TMEM Budget Considerations
-
-With 512 total columns per SM:
-
-| Accumulator Size | Columns | Max Buffers | Remaining for Scratch |
-|---|---|---|---|
-| 128x128 FP32 | 128 cols | 4 | 0 |
-| 128x192 FP32 | 192 cols | 2 | 128 |
-| 128x256 FP32 | 256 cols | 2 | 0 |
-| 128x256 FP32 (2x) | 512 cols | 2 (double-buf) | 0 |
-
-For double-buffered 128x256 tiles, the full 512 columns are consumed. If additional scratch TMEM is needed (e.g., for softmax in attention kernels), reduce the tile size or use a single accumulator buffer.
-
-## Microbenchmark Data
-
-From published Blackwell microbenchmarks:
-
-| Metric | TMEM | SMEM | Registers |
-|---|---|---|---|
-| End-to-end latency (cache miss) | ~420 cycles | ~30 cycles | ~4 cycles |
-| Bandwidth for large working sets | High (dedicated bus) | Medium | N/A (limited count) |
-| Best for | Multi-stage tensor pipelines | Single-shot small matrix | Scalar/vector ALU |
-
-TMEM is **not** a replacement for shared memory. Its strength is in serving as a dedicated accumulator buffer that eliminates register pressure for large MMA tiles. SMEM remains faster for small, frequently accessed data.
-
-## TMEM in the CUTLASS Abstraction
-
-In CUTLASS 4.5.0 for SM100, TMEM is managed through CuTe layouts:
-
-```python
-# CuTe-DSL example: TMEM accumulator layout
-# 128 rows x 256 columns, FP32
-tmem_layout = Layout(
-    shape=(128, 256),
-    stride=(256, 1),
-    memory_space=MemorySpace.TMEM
-)
-
-# Allocate TMEM accumulator
-acc = tmem_alloc(tmem_layout)
-
-# Issue MMA -- accumulator lives in TMEM
-tcgen05_mma(acc, smem_a, smem_b)
-
-# Fence and read
-tcgen05_fence()
-result = tmem_load(acc)
-```
-
-## Common Pitfalls
-
-1. **Forgetting to fence**: Reading TMEM without `tcgen05.mma.fence::before_thread_sync` produces undefined (stale) values.
-2. **Forgetting to deallocate**: In persistent kernels, TMEM must be freed before re-acquiring tiles. Otherwise, the next allocation will fail or hang.
-3. **Exceeding 512 columns**: Attempting to allocate more than the SM's total column budget silently corrupts data or causes a hang.
-4. **Cross-warp reads**: A thread can only directly read/write TMEM rows mapped to its own lane. Accessing another warp's rows requires explicit shuffle or SMEM staging.
-5. **Assuming SMEM-like latency**: TMEM has ~420-cycle latency on cache miss vs ~30 cycles for SMEM. Do not use TMEM for low-latency random access patterns.