@jutge.org/toolkit 4.2.34 → 4.2.35

package/assets/problems/circuits/full_adder.pbm/README.md

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+# Full adder
+
+## Features
+
+- Circuit problem: implement a full adder using Verilog
+- Formal verification: This kind of problems do not have test cases, only a golden solution
+
+## Abstract
+
+Implement a full adder using Verilog.

package/assets/problems/circuits/full_adder.pbm/code.v

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+module full_adder(a, b, cin, sum, cout);
+   input  a, b, cin;
+   output sum, cout;

package/assets/problems/circuits/full_adder.pbm/handler.yml

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+handler: circuits

package/assets/problems/circuits/full_adder.pbm/problem.en.tex

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+\Problem{Full adder}
+%\UseVerilog
+
+\Statement
+Design a \textbf{full adder}. A full adder is a circuit that performs
+a 1-bit addition receiving an input carry and generating an
+output carry.
+
+\Specification
+\begin{verbatim}
+module full_adder(a, b, cin, sum, cout);
+   input a, b, cin;
+   output sum, cout;
+\end{verbatim}
+
+\Input
+\begin{itemize}
+\item \lstinline|a| and \lstinline|b| are the two inputs.
+\item \lstinline|cin| is the input carry.
+\end{itemize}
+
+\Output
+\begin{itemize}
+\item \lstinline|sum| is the sum of the two bits and the input carry.
+\item \lstinline|cout| is the output carry.
+\end{itemize}

package/assets/problems/circuits/full_adder.pbm/problem.en.yml

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+email: jordi.cortadella@upc.edu
+title: Full adder
+author: Jordi Cortadella

package/assets/problems/circuits/full_adder.pbm/solution.v

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+module full_adder (a, b, cin, sum, cout);
+  input a, b, cin;
+  output sum, cout;
+  assign {cout, sum} = a + b + cin;
+endmodule
+  

package/assets/problems/circuits/half_adder.pbm/README.md

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+# Half adder
+
+## Features
+
+- Circuit problem: implement a half adder using Verilog
+- Formal verification: This kind of problems do not have test cases, only a golden solution
+
+## Abstract
+
+Implement a half adder using Verilog.

package/assets/problems/circuits/half_adder.pbm/handler.yml

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+handler: circuits

package/assets/problems/circuits/half_adder.pbm/problem.en.tex

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+\Problem{Half adder}
+
+
+\Statement
+Design a \textbf{half adder} that is a circuit that performs the addition of
+two binary digits, \lstinline|a| and \lstinline|b|. It outputs the \lstinline|sum| and the output \lstinline|carry|.
+
+\Specification
+
+\begin{lstlisting}[language=verilog]
+module halfadder(a, b, sum, carry);
+    input a, b;
+    output sum, carry;
+\end{lstlisting}
+
+
+\Input
+\begin{itemize}
+\item \lstinline|a| and \lstinline|b| are the two input values.
+\end{itemize}
+
+\Output
+\begin{itemize}
+\item \lstinline|sum| is the least significant digit of $a + b$.
+
+\item \lstinline|carry| is the output carry, i.e., the most significant digit of $a + b$.
+\end{itemize}

package/assets/problems/circuits/half_adder.pbm/problem.en.yml

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+email: jspedro@lsi.upc.edu
+title: Half adder
+author: Javier de San Pedro Martín

package/assets/problems/circuits/half_adder.pbm/solution.v

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+module halfadder(a, b, sum, carry);
+	input a, b;
+	output sum, carry;
+	assign {carry, sum} = a + b;
+endmodule

package/package.json

@@ -1,7 +1,7 @@
 {
     "name": "@jutge.org/toolkit",
     "description": "Toolkit to prepare problems for Jutge.org",
-    "version": "4.2.34",
+    "version": "4.2.35",
     "homepage": "https://jutge.org",
     "author": {
         "name": "Jutge.org",