@jhlagado/azm 0.2.6 → 0.2.8

package/dist/src/z80/parse-io-control.d.ts

@@ -0,0 +1,5 @@
+import type { ParseZ80InstructionResult } from './parse-instruction.js';
+export declare function parseInputInstruction(text: string): ParseZ80InstructionResult | undefined;
+export declare function parseOutputInstruction(text: string): ParseZ80InstructionResult | undefined;
+export declare function parseInterruptModeInstruction(text: string): ParseZ80InstructionResult | undefined;
+export declare function parseRstInstruction(text: string): ParseZ80InstructionResult | undefined;

package/dist/src/z80/parse-io-control.js

@@ -0,0 +1,108 @@
+import { splitInstructionOperands } from './operand-split.js';
+import { isRstVector, parseConstantExpression, parseIndexHalfRegister, parsePortOperand, parseRegister8Operand, } from './parse-operands.js';
+export function parseInputInstruction(text) {
+    const input = /^IN(?:\s+(.*))?$/i.exec(text);
+    if (input) {
+        const operandText = input[1] ?? '';
+        const parts = splitInstructionOperands(operandText);
+        if (operandText.trim().length === 0 || parts.length > 2) {
+            return { error: 'in expects one or two operands' };
+        }
+        if (parts.length === 1)
+            return parseOneOperandInput(parts[0] ?? '');
+        return parseTwoOperandInput(parts[0] ?? '', parts[1] ?? '');
+    }
+    return undefined;
+}
+function parseOneOperandInput(portText) {
+    const port = parsePortOperand(portText);
+    return port?.kind === 'c'
+        ? { instruction: { mnemonic: 'in', port } }
+        : { error: 'in (c) is the only one-operand in form' };
+}
+function parseTwoOperandInput(targetText, portText) {
+    const target = parseRegister8Operand(targetText);
+    if (!target) {
+        return parseIndexHalfRegister(targetText)
+            ? { error: 'in destination must use plain reg8 B/C/D/E/H/L/A' }
+            : { error: 'in expects a reg8 destination' };
+    }
+    const port = parsePortOperand(portText);
+    if (!port) {
+        return { error: 'in expects a port operand (c) or (imm8)' };
+    }
+    if (port.kind === 'imm' && target.register !== 'a') {
+        return { error: 'in a,(n) immediate port form requires destination A' };
+    }
+    return { instruction: { mnemonic: 'in', target, port } };
+}
+export function parseOutputInstruction(text) {
+    const output = /^OUT(?:\s+(.*))?$/i.exec(text);
+    if (output) {
+        const operandText = output[1] ?? '';
+        const parts = splitInstructionOperands(operandText);
+        if (operandText.trim().length === 0 || parts.length !== 2) {
+            return { error: 'out expects two operands' };
+        }
+        const port = parsePortOperand(parts[0] ?? '');
+        if (!port) {
+            return { error: 'out expects a port operand (c) or (imm8)' };
+        }
+        return parseOutputSource(port, parts[1] ?? '');
+    }
+    return undefined;
+}
+function parseOutputSource(port, sourceText) {
+    const source = parseRegister8Operand(sourceText);
+    if (source) {
+        if (port.kind === 'imm' && source.register !== 'a') {
+            return { error: 'out (n),a immediate port form requires source A' };
+        }
+        return { instruction: { mnemonic: 'out', port, source } };
+    }
+    if (parseIndexHalfRegister(sourceText)) {
+        return { error: 'out source must use plain reg8 B/C/D/E/H/L/A' };
+    }
+    return parseOutputZeroSource(port, sourceText);
+}
+function parseOutputZeroSource(port, sourceText) {
+    const zero = parseConstantExpression(sourceText);
+    if (zero !== undefined && port.kind === 'c') {
+        return zero === 0
+            ? { instruction: { mnemonic: 'out', port, source: { kind: 'zero' } } }
+            : { error: 'out (c), n immediate form supports n=0 only' };
+    }
+    return { error: 'out expects a reg8 source' };
+}
+export function parseInterruptModeInstruction(text) {
+    const im = /^IM(?:\s+(.*))?$/i.exec(text);
+    if (im) {
+        const operandText = im[1] ?? '';
+        const parts = splitInstructionOperands(operandText);
+        if (operandText.trim().length === 0 || parts.length !== 1) {
+            return { error: 'im expects one operand' };
+        }
+        const mode = parseConstantExpression(parts[0] ?? '');
+        if (mode !== 0 && mode !== 1 && mode !== 2) {
+            return { error: 'im expects 0, 1, or 2' };
+        }
+        return { instruction: { mnemonic: 'im', mode } };
+    }
+    return undefined;
+}
+export function parseRstInstruction(text) {
+    const rst = /^RST(?:\s+(.*))?$/i.exec(text);
+    if (rst) {
+        const operandText = rst[1] ?? '';
+        const parts = splitInstructionOperands(operandText);
+        if (operandText.trim().length === 0 || parts.length !== 1) {
+            return { error: 'rst expects one operand' };
+        }
+        const vector = parseConstantExpression(parts[0] ?? '');
+        if (!isRstVector(vector)) {
+            return { error: 'rst expects an imm8 multiple of 8 (0..56)' };
+        }
+        return { instruction: { mnemonic: 'rst', vector } };
+    }
+    return undefined;
+}

package/dist/src/z80/parse-ld.d.ts

@@ -0,0 +1,2 @@
+import type { ParseZ80InstructionResult } from './parse-instruction.js';
+export declare function parseLdInstruction(text: string): ParseZ80InstructionResult | undefined;

package/dist/src/z80/parse-ld.js

@@ -0,0 +1,83 @@
+import { isSupportedLd, unsupportedLdReason } from './ld-support.js';
+import { splitInstructionOperands } from './operand-split.js';
+import { indexedBracketError, invalidLdOperandDiagnostics, parseLdOperand, } from './parse-operands.js';
+export function parseLdInstruction(text) {
+    const ld = /^LD\s+(.+)$/i.exec(text);
+    if (ld) {
+        return parseLdOperands(ld[1] ?? '');
+    }
+    return undefined;
+}
+function parseLdOperands(operandText) {
+    const parts = splitInstructionOperands(operandText);
+    if (parts.length !== 2) {
+        return { error: 'ld expects two operands' };
+    }
+    return parseLdOperandTexts(parts[0] ?? '', parts[1] ?? '');
+}
+function parseLdOperandTexts(leftText, rightText) {
+    const indexedBracket = indexedBracketError(leftText) ?? indexedBracketError(rightText);
+    if (indexedBracket) {
+        return { error: indexedBracket };
+    }
+    if (/^AF$/i.test(leftText) || /^AF$/i.test(rightText)) {
+        return { error: 'ld does not support AF in this form' };
+    }
+    const operands = parseLdOperandPair(leftText, rightText);
+    if ('error' in operands)
+        return operands;
+    const formError = ldFormError(operands.target, operands.source);
+    if (formError)
+        return { error: formError };
+    const { target, source } = operands;
+    return { instruction: { mnemonic: 'ld', target, source } };
+}
+function parseLdOperandPair(leftText, rightText) {
+    const target = parseLdOperand(leftText);
+    const source = parseLdOperand(rightText);
+    if (target && source) {
+        return { target, source };
+    }
+    const operandDiagnostics = [
+        ...invalidLdOperandDiagnostics(leftText),
+        ...invalidLdOperandDiagnostics(rightText),
+    ];
+    if (operandDiagnostics.length > 0) {
+        return {
+            error: operandDiagnostics[operandDiagnostics.length - 1],
+            diagnostics: operandDiagnostics,
+        };
+    }
+    return { error: 'ld expects a supported register/memory/immediate transfer form' };
+}
+function ldFormError(target, source) {
+    return (ldRegisterIndirectFormError(target, source) ??
+        ldHalfIndexFormError(target, source) ??
+        unsupportedLdReason(target, source) ??
+        unsupportedLdFormError(target, source));
+}
+function ldRegisterIndirectFormError(target, source) {
+    if (target.kind === 'reg8' &&
+        target.register !== 'a' &&
+        source.kind === 'reg-indirect' &&
+        source.register !== 'hl') {
+        return 'ld r8, (bc/de) supports destination A only';
+    }
+    if (target.kind === 'reg-indirect' &&
+        source.kind === 'reg8' &&
+        source.register !== 'a' &&
+        target.register !== 'hl') {
+        return 'ld (bc/de), r8 supports source A only';
+    }
+    return undefined;
+}
+function ldHalfIndexFormError(target, source) {
+    return target.kind === 'reg-half-index' && source.kind === 'reg-indirect'
+        ? `ld ${target.register.toUpperCase()}, source expects (ix+disp)`
+        : undefined;
+}
+function unsupportedLdFormError(target, source) {
+    return isSupportedLd(target, source)
+        ? undefined
+        : 'ld expects a supported register/memory/immediate transfer form';
+}

package/dist/src/z80/parse-operands.d.ts

@@ -0,0 +1,41 @@
+import type { Expression } from '../model/expression.js';
+import type { Z80IndexHalfRegister, Z80IndexRegister16, Z80Instruction, Z80Operand, Z80RstVector, Z80StackRegister16 } from './instruction.js';
+export declare function parseLdOperand(text: string): Z80Operand | undefined;
+export declare function invalidLdOperandDiagnostics(text: string): readonly string[];
+export declare function aluImm8RangeError(expression: Expression, mnemonic: string): string | undefined;
+export declare function parseAluOperand(text: string): Z80Operand | undefined;
+export declare function parseCbOperand(text: string): Extract<Z80Operand, {
+    readonly kind: 'reg8';
+}> | {
+    readonly kind: 'reg-indirect';
+    readonly register: 'hl';
+} | Extract<Z80Operand, {
+    readonly kind: 'indexed';
+}> | undefined;
+export declare function parseRegister8Operand(text: string): Extract<Z80Operand, {
+    readonly kind: 'reg8';
+}> | undefined;
+export declare function parseRegister16Operand(text: string): Extract<Z80Operand, {
+    readonly kind: 'reg16';
+}> | undefined;
+export declare function parseIncDecOperand(text: string): Extract<Z80Instruction, {
+    readonly mnemonic: 'inc' | 'dec';
+}>['operand'] | undefined;
+export declare function parseIndexRegister16(text: string): Z80IndexRegister16 | undefined;
+export declare function parseIndexHalfRegister(text: string): Z80IndexHalfRegister | undefined;
+export declare function halfIndexFamilyFromRegister(register: Z80IndexHalfRegister): Z80IndexRegister16;
+export declare function parseStackRegister(text: string): Z80StackRegister16 | undefined;
+export declare function parseIndexedOperand(text: string): Extract<Z80Operand, {
+    readonly kind: 'indexed';
+}> | undefined;
+export declare function parsePortOperand(text: string): {
+    readonly kind: 'c';
+} | {
+    readonly kind: 'imm';
+    readonly expression: Expression;
+} | undefined;
+export declare function indexedBracketError(text: string): string | undefined;
+export declare function parseConstantExpression(text: string): number | undefined;
+export declare function isRstVector(value: number | undefined): value is Z80RstVector;
+export declare function parseBitIndex(text: string): 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | undefined;
+export declare function constantExpressionValue(expression: Expression): number | undefined;

package/dist/src/z80/parse-operands.js

@@ -0,0 +1,259 @@
+import { applyBinaryOperator } from '../semantics/constant-operators.js';
+import { parseExpression } from '../syntax/parse-expression.js';
+export function parseLdOperand(text) {
+    const trimmed = text.trim();
+    for (const parser of LD_OPERAND_PARSERS) {
+        const operand = parser(trimmed);
+        if (operand) {
+            return operand;
+        }
+    }
+    return undefined;
+}
+const LD_OPERAND_PARSERS = [
+    parseIndexedOperand,
+    parseLdRegisterIndirectOperand,
+    parseLdAbsoluteMemoryOperand,
+    parseRegister8Operand,
+    parseLdIndex16Operand,
+    parseLdHalfIndexOperand,
+    parseRegister16Operand,
+    parseLdSpecial8Operand,
+    parseLdImmediateOperand,
+];
+function parseLdRegisterIndirectOperand(trimmed) {
+    const match = /^\((BC|DE|HL)\)$/i.exec(trimmed);
+    if (!match) {
+        return undefined;
+    }
+    return {
+        kind: 'reg-indirect',
+        register: (match[1] ?? '').toLowerCase(),
+    };
+}
+function parseLdAbsoluteMemoryOperand(trimmed) {
+    if (!trimmed.startsWith('(') || !trimmed.endsWith(')')) {
+        return undefined;
+    }
+    const expression = parseExpression(trimmed.slice(1, -1).trim());
+    return expression ? { kind: 'mem-abs', expression } : undefined;
+}
+function parseLdIndex16Operand(trimmed) {
+    const register = parseIndexRegister16(trimmed);
+    return register ? { kind: 'reg-index16', register } : undefined;
+}
+function parseLdHalfIndexOperand(trimmed) {
+    const register = parseIndexHalfRegister(trimmed);
+    return register ? { kind: 'reg-half-index', register } : undefined;
+}
+function parseLdSpecial8Operand(trimmed) {
+    const register = parseSpecialRegister8(trimmed);
+    return register ? { kind: 'special8', register } : undefined;
+}
+function parseLdImmediateOperand(trimmed) {
+    const expression = parseExpression(trimmed);
+    return expression ? { kind: 'imm', expression } : undefined;
+}
+export function invalidLdOperandDiagnostics(text) {
+    const trimmed = text.trim();
+    if (trimmed === '?') {
+        return ['Invalid imm expression: ?', 'Unsupported operand: ?'];
+    }
+    if (trimmed.startsWith("'") && parseExpression(trimmed) === undefined) {
+        return [`Invalid imm expression: ${trimmed}`];
+    }
+    return [];
+}
+export function aluImm8RangeError(expression, mnemonic) {
+    const value = constantExpressionValue(expression);
+    if (value === undefined) {
+        return undefined;
+    }
+    if (value < -128 || value > 255) {
+        return `${mnemonic} expects imm8`;
+    }
+    return undefined;
+}
+export function parseAluOperand(text) {
+    const trimmed = text.trim();
+    const indexed = parseIndexedOperand(trimmed);
+    if (indexed) {
+        return indexed;
+    }
+    const memory = /^\(HL\)$/i.exec(trimmed);
+    if (memory) {
+        return { kind: 'reg-indirect', register: 'hl' };
+    }
+    if (trimmed.startsWith('(') && trimmed.endsWith(')')) {
+        return undefined;
+    }
+    const register = parseRegister8Operand(trimmed);
+    if (register) {
+        return register;
+    }
+    const half = parseIndexHalfRegister(trimmed);
+    if (half) {
+        return { kind: 'reg-half-index', register: half };
+    }
+    const expression = parseExpression(trimmed);
+    return expression ? { kind: 'imm', expression } : undefined;
+}
+export function parseCbOperand(text) {
+    const trimmed = text.trim();
+    const indexed = parseIndexedOperand(trimmed);
+    if (indexed) {
+        return indexed;
+    }
+    if (/^\(HL\)$/i.test(trimmed)) {
+        return { kind: 'reg-indirect', register: 'hl' };
+    }
+    return parseRegister8Operand(trimmed);
+}
+export function parseRegister8Operand(text) {
+    const trimmed = text.trim();
+    if (/^(A|B|C|D|E|H|L)$/i.test(trimmed)) {
+        return { kind: 'reg8', register: trimmed.toLowerCase() };
+    }
+    return undefined;
+}
+export function parseRegister16Operand(text) {
+    const trimmed = text.trim();
+    if (/^(BC|DE|HL|SP)$/i.test(trimmed)) {
+        return { kind: 'reg16', register: trimmed.toLowerCase() };
+    }
+    return undefined;
+}
+export function parseIncDecOperand(text) {
+    const trimmed = text.trim();
+    const indexed = parseIndexedOperand(trimmed);
+    if (indexed) {
+        return indexed;
+    }
+    if (/^\(HL\)$/i.test(trimmed)) {
+        return { kind: 'reg-indirect', register: 'hl' };
+    }
+    const register8 = parseRegister8Operand(trimmed);
+    if (register8) {
+        return register8;
+    }
+    const register16 = parseRegister16Operand(trimmed);
+    if (register16) {
+        return register16;
+    }
+    const index16 = parseIndexRegister16(trimmed);
+    if (index16) {
+        return { kind: 'reg16', register: index16 };
+    }
+    const half = parseIndexHalfRegister(trimmed);
+    return half ? { kind: 'reg-half-index', register: half } : undefined;
+}
+export function parseIndexRegister16(text) {
+    const trimmed = text.trim();
+    return /^(IX|IY)$/i.test(trimmed) ? trimmed.toLowerCase() : undefined;
+}
+export function parseIndexHalfRegister(text) {
+    const trimmed = text.trim();
+    return /^(IXH|IXL|IYH|IYL)$/i.test(trimmed)
+        ? trimmed.toLowerCase()
+        : undefined;
+}
+export function halfIndexFamilyFromRegister(register) {
+    return register.startsWith('ix') ? 'ix' : 'iy';
+}
+function parseSpecialRegister8(text) {
+    const trimmed = text.trim();
+    return /^(I|R)$/i.test(trimmed) ? trimmed.toLowerCase() : undefined;
+}
+export function parseStackRegister(text) {
+    const trimmed = text.trim();
+    return /^(BC|DE|HL|AF|IX|IY)$/i.test(trimmed)
+        ? trimmed.toLowerCase()
+        : undefined;
+}
+export function parseIndexedOperand(text) {
+    const trimmed = text.trim();
+    if (!trimmed.startsWith('(') || !trimmed.endsWith(')')) {
+        return undefined;
+    }
+    const inner = trimmed.slice(1, -1).trim();
+    const match = /^(IX|IY)(?:\s*([+-])\s*(.+))?$/i.exec(inner);
+    if (!match) {
+        return undefined;
+    }
+    const register = (match[1] ?? '').toLowerCase();
+    const sign = match[2];
+    const displacementText = match[3] ?? '0';
+    const parsed = parseExpression(sign === '-' ? `-${displacementText}` : displacementText);
+    if (!parsed) {
+        return undefined;
+    }
+    return { kind: 'indexed', register, displacement: parsed };
+}
+export function parsePortOperand(text) {
+    const trimmed = text.trim();
+    if (/^\(C\)$/i.test(trimmed)) {
+        return { kind: 'c' };
+    }
+    if (!trimmed.startsWith('(') || !trimmed.endsWith(')')) {
+        return undefined;
+    }
+    const expression = parseExpression(trimmed.slice(1, -1).trim());
+    return expression ? { kind: 'imm', expression } : undefined;
+}
+export function indexedBracketError(text) {
+    const match = /^\(?\s*((IX|IY)\s*\[\s*.+?\s*\])\s*\)?$/i.exec(text.trim());
+    return match
+        ? `Indexed memory operands use (ix+disp)/(iy+disp), not ${match[1]?.toLowerCase().replace(/\s+/g, '')}.`
+        : undefined;
+}
+export function parseConstantExpression(text) {
+    const expression = parseExpression(text);
+    return expression ? constantExpressionValue(expression) : undefined;
+}
+export function isRstVector(value) {
+    return RST_VECTORS.has(value);
+}
+const RST_VECTORS = new Set([0, 8, 16, 24, 32, 40, 48, 56]);
+export function parseBitIndex(text) {
+    const value = parseConstantExpression(text);
+    return isBitIndex(value) ? value : undefined;
+}
+function isBitIndex(value) {
+    return BIT_INDEXES.has(value);
+}
+const BIT_INDEXES = new Set([0, 1, 2, 3, 4, 5, 6, 7]);
+export function constantExpressionValue(expression) {
+    switch (expression.kind) {
+        case 'number':
+            return expression.value;
+        case 'unary':
+            return constantUnaryExpressionValue(expression);
+        case 'binary':
+            return constantBinaryExpressionValue(expression);
+        case 'symbol':
+        case 'current-location':
+            return undefined;
+    }
+}
+function constantUnaryExpressionValue(expression) {
+    const value = constantExpressionValue(expression.expression);
+    if (value === undefined) {
+        return undefined;
+    }
+    switch (expression.operator) {
+        case '+':
+            return value;
+        case '-':
+            return -value;
+        case '~':
+            return ~value;
+    }
+}
+function constantBinaryExpressionValue(expression) {
+    const left = constantExpressionValue(expression.left);
+    const right = constantExpressionValue(expression.right);
+    if (left === undefined || right === undefined) {
+        return undefined;
+    }
+    return applyBinaryOperator(expression.operator, left, right);
+}

package/docs/reference/cli.md

@@ -10,7 +10,7 @@ azm [options] <entry.asm|entry.z80>
 ```
 
 The entry file must be the final argument. AZM source uses `.asm` or `.z80`.
-Register-care interface files use `.asmi`; they are loaded with `--interface`
+Register contracts interface files use `.asmi`; they are loaded with `--interface`
 and are not compile entries.
 
 ## Basic Use
@@ -51,46 +51,46 @@ azm --source-root . --output build/program.hex src/program.asm
 By default AZM writes the primary output plus useful side artifacts using the
 same base path.
 
-| Artifact       | Meaning                          |
-| -------------- | -------------------------------- |
-| `.hex`         | Intel HEX output                 |
-| `.bin`         | flat binary output               |
-| `.d8.json`     | Debug80 map                      |
-| `.z80`         | lowered assembler source         |
-| `.regcare.txt` | register-care report             |
-| `.asmi`        | inferred register-care interface |
+| Artifact            | Meaning                                |
+| ------------------- | -------------------------------------- |
+| `.hex`              | Intel HEX output                       |
+| `.bin`              | flat binary output                     |
+| `.d8.json`          | Debug80 map                            |
+| `.z80`              | lowered assembler source               |
+| `.regcontracts.txt` | opt-in register contracts debug report |
+| `.asmi`             | inferred register contracts interface  |
 
 Disable standard artifacts when they are not needed:
 
 ```sh
 azm --nod8m program.asm
-azm --nobin --nohex --reg-report --rc audit program.asm
+azm --nobin --nohex --nod8m --rc audit program.asm
 ```
 
 ## Options
 
-| Option                                        | Meaning                                                              |
-| --------------------------------------------- | -------------------------------------------------------------------- |
-| `-o, --output <file>`                         | Primary output path. The extension must match `--type`.              |
-| `-t, --type <hex\|bin>`                       | Primary output type. Default: `hex`.                                 |
-| `--nobin`                                     | Do not write `.bin`.                                                 |
-| `--nohex`                                     | Do not write `.hex`.                                                 |
-| `--nod8m`                                     | Do not write `.d8.json`.                                             |
-| `--asm80`                                     | Write lowered assembler source as `.z80`.                            |
-| `--source-root <dir>`                         | Emit project-relative source paths in `.d8.json`.                    |
+| Option                                        | Meaning                                                                        |
+| --------------------------------------------- | ------------------------------------------------------------------------------ |
+| `-o, --output <file>`                         | Primary output path. The extension must match `--type`.                        |
+| `-t, --type <hex\|bin>`                       | Primary output type. Default: `hex`.                                           |
+| `--nobin`                                     | Do not write `.bin`.                                                           |
+| `--nohex`                                     | Do not write `.hex`.                                                           |
+| `--nod8m`                                     | Do not write `.d8.json`.                                                       |
+| `--asm80`                                     | Write lowered assembler source as `.z80`.                                      |
+| `--source-root <dir>`                         | Emit project-relative source paths in `.d8.json`.                              |
 | `--case-style <mode>`                         | Lint mnemonic/register/op-head case: `off`, `upper`, `lower`, or `consistent`. |
-| `--rc, --register-care <mode>`                | Register-care mode: `off`, `audit`, `warn`, `error`, or `strict`.    |
-| `--reg-report, --emit-register-report`        | Write `.regcare.txt`.                                                |
-| `--reg-interface, --emit-register-interface`  | Write inferred `.asmi` interface.                                    |
-| `--contracts, --annotate-register-contracts`  | Update AZMDoc contract comments in source.                           |
-| `--fix`                                       | Apply conservative register-care source fixes and update contracts.  |
-| `--accept-out <routine:carrier>`              | Promote an inferred output candidate while annotating.               |
-| `--interface <file>`                          | Load external register-care contracts from `.asmi`. Repeatable.      |
-| `--reg-profile, --register-profile <profile>` | Register-care profile. Currently `mon3`.                             |
-| `--aliases <file>`                            | Load project directive alias JSON. Repeatable.                       |
-| `-I, --include <dir>`                         | Add an include search path. Repeatable.                              |
-| `-V, --version`                               | Print package version.                                               |
-| `-h, --help`                                  | Print CLI help.                                                      |
+| `--rc, --register-contracts <mode>`           | Register contracts mode: `off`, `audit`, `warn`, `error`, or `strict`.         |
+| `--reg-report, --emit-register-report`        | Opt-in debug report: write `.regcontracts.txt`.                                |
+| `--reg-interface, --emit-register-interface`  | Write inferred `.asmi` interface.                                              |
+| `--contracts, --annotate-register-contracts`  | Update AZMDoc contract comments in source.                                     |
+| `--fix`                                       | Apply conservative register contract source fixes and update contracts.        |
+| `--accept-out <routine:carrier>`              | Promote an inferred output candidate while annotating.                         |
+| `--interface <file>`                          | Load external register contracts from `.asmi`. Repeatable.                     |
+| `--reg-profile, --register-profile <profile>` | Register contracts profile. Currently `mon3`.                                  |
+| `--aliases <file>`                            | Load project directive alias JSON. Repeatable.                                 |
+| `-I, --include <dir>`                         | Add an include search path. Repeatable.                                        |
+| `-V, --version`                               | Print package version.                                                         |
+| `-h, --help`                                  | Print CLI help.                                                                |
 
 ## Debug80 Maps
 
@@ -104,12 +104,12 @@ keys and generator input paths are written relative to that directory with `/`
 separators. Constants are emitted as `value` metadata without fake addresses;
 labels and addressable data carry `address`.
 
-## Register-Care Examples
+## Register Contracts Examples
 
 Audit inferred contracts without failing the build:
 
 ```sh
-azm --rc audit --reg-report program.asm
+azm --rc audit program.asm
 ```
 
 Treat contract conflicts as build failures:
@@ -118,6 +118,13 @@ Treat contract conflicts as build failures:
 azm --rc error program.asm
 ```
 
+Treat every register contracts issue as a build failure, including unknown call
+boundaries and stack effects AZM cannot prove within an `@` routine boundary:
+
+```sh
+azm --rc strict program.asm
+```
+
 Generate compact AZMDoc blocks in source:
 
 ```sh
@@ -132,7 +139,7 @@ azm --rc error --interface mon3.asmi program.asm
 
 ## `.asmi` Interfaces
 
-External register-care interfaces are plain metadata files:
+External register contract interfaces are plain metadata files:
 
 ```text
 extern MON_PRINT_CHAR
@@ -145,7 +152,7 @@ Use `.asmi` for these files so they are clearly distinct from assembler source.
 
 ## Exit Behavior
 
-The CLI exits with a non-zero status when parsing, semantic checks, register-care
+The CLI exits with a non-zero status when parsing, semantic checks, register contracts
 mode, lowering, or artifact writing reports an error. Diagnostics are printed
 with file, line, column, severity, and diagnostic ID where that information is
 available.