@jhlagado/azm 0.1.1 → 0.2.1
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/README.md +103 -70
- package/dist/{src → legacy-root-azm/src}/formats/index.d.ts +1 -1
- package/dist/{src → legacy-root-azm/src}/formats/index.js +1 -1
- package/dist/{src → legacy-root-azm/src}/formats/types.d.ts +67 -7
- package/dist/{src → legacy-root-azm/src}/formats/writeHex.d.ts +0 -1
- package/dist/{src → legacy-root-azm/src}/formats/writeHex.js +0 -1
- package/dist/{src → legacy-root-azm/src}/pipeline.d.ts +3 -5
- package/dist/legacy-root-azm/src/z80/effects.d.ts +3 -0
- package/dist/legacy-root-azm/src/z80/effects.js +516 -0
- package/dist/legacy-root-azm/src/z80/encode.d.ts +10 -0
- package/dist/legacy-root-azm/src/z80/encode.js +412 -0
- package/dist/src/api-compile.d.ts +49 -8
- package/dist/src/api-compile.js +313 -3
- package/dist/src/api-tooling.d.ts +7 -25
- package/dist/src/api-tooling.js +3 -21
- package/dist/src/assembly/address-planning.d.ts +19 -0
- package/dist/src/assembly/address-planning.js +268 -0
- package/dist/src/assembly/assemble-program.d.ts +13 -0
- package/dist/src/assembly/assemble-program.js +34 -0
- package/dist/src/assembly/fixup-emission.d.ts +10 -0
- package/dist/src/assembly/fixup-emission.js +247 -0
- package/dist/src/assembly/placement.d.ts +26 -0
- package/dist/src/assembly/placement.js +79 -0
- package/dist/src/assembly/program-emission.d.ts +13 -0
- package/dist/src/assembly/program-emission.js +268 -0
- package/dist/src/cli/parse-args.d.ts +29 -0
- package/dist/src/cli/parse-args.js +372 -0
- package/dist/src/cli/run.d.ts +2 -0
- package/dist/src/cli/run.js +35 -0
- package/dist/src/cli/write-artifacts.d.ts +21 -0
- package/dist/src/cli/write-artifacts.js +175 -0
- package/dist/src/cli.d.ts +1 -30
- package/dist/src/cli.js +20 -524
- package/dist/src/core/compile-artifacts.d.ts +26 -0
- package/dist/src/core/compile-artifacts.js +17 -0
- package/dist/src/core/compile.d.ts +26 -0
- package/dist/src/core/compile.js +164 -0
- package/dist/src/diagnostics/format.d.ts +4 -0
- package/dist/src/diagnostics/format.js +9 -0
- package/dist/src/expansion/op-expansion.d.ts +96 -0
- package/dist/src/expansion/op-expansion.js +913 -0
- package/dist/src/index.d.ts +14 -3
- package/dist/src/index.js +7 -2
- package/dist/src/model/diagnostic.d.ts +50 -0
- package/dist/src/model/diagnostic.js +29 -0
- package/dist/src/model/expression.d.ts +51 -0
- package/dist/src/model/expression.js +1 -0
- package/dist/src/model/fixup.d.ts +18 -0
- package/dist/src/model/fixup.js +1 -0
- package/dist/src/model/source-item.d.ts +87 -0
- package/dist/src/model/source-item.js +1 -0
- package/dist/src/model/symbol.d.ts +1 -0
- package/dist/src/model/symbol.js +1 -0
- package/dist/src/node/source-host.d.ts +19 -0
- package/dist/src/node/source-host.js +146 -0
- package/dist/src/outputs/hex.d.ts +1 -0
- package/dist/src/outputs/hex.js +75 -0
- package/dist/src/outputs/index.d.ts +3 -0
- package/dist/src/outputs/index.js +13 -0
- package/dist/src/outputs/range.d.ts +3 -0
- package/dist/src/outputs/range.js +31 -0
- package/dist/src/outputs/types.d.ts +182 -0
- package/dist/src/outputs/types.js +1 -0
- package/dist/src/outputs/write-asm80.d.ts +7 -0
- package/dist/src/outputs/write-asm80.js +666 -0
- package/dist/src/outputs/write-bin.d.ts +2 -0
- package/dist/src/outputs/write-bin.js +27 -0
- package/dist/src/outputs/write-d8.d.ts +2 -0
- package/dist/src/outputs/write-d8.js +257 -0
- package/dist/src/outputs/write-hex.d.ts +2 -0
- package/dist/src/outputs/write-hex.js +53 -0
- package/dist/src/outputs/write-listing.d.ts +2 -0
- package/dist/src/outputs/write-listing.js +79 -0
- package/dist/src/register-care/accept-output.d.ts +2 -0
- package/dist/src/register-care/accept-output.js +35 -0
- package/dist/src/register-care/analyze.d.ts +26 -0
- package/dist/src/register-care/analyze.js +115 -0
- package/dist/src/register-care/annotate.d.ts +11 -0
- package/dist/src/register-care/annotate.js +76 -0
- package/dist/src/register-care/annotations.d.ts +8 -0
- package/dist/src/register-care/annotations.js +41 -0
- package/dist/src/register-care/boundaryHints.d.ts +2 -0
- package/dist/src/register-care/boundaryHints.js +11 -0
- package/dist/src/register-care/carriers.d.ts +2 -0
- package/dist/src/register-care/carriers.js +78 -0
- package/dist/src/register-care/controlFlow.d.ts +5 -0
- package/dist/src/register-care/controlFlow.js +38 -0
- package/dist/src/register-care/fix.d.ts +11 -0
- package/dist/src/register-care/fix.js +130 -0
- package/dist/src/register-care/instruction-shape.d.ts +11 -0
- package/dist/src/register-care/instruction-shape.js +129 -0
- package/dist/src/register-care/liveness.d.ts +3 -0
- package/dist/src/register-care/liveness.js +197 -0
- package/dist/src/register-care/profiles.d.ts +9 -0
- package/dist/src/register-care/profiles.js +47 -0
- package/dist/src/register-care/programModel.d.ts +3 -0
- package/dist/src/register-care/programModel.js +188 -0
- package/dist/src/register-care/report.d.ts +5 -0
- package/dist/src/register-care/report.js +139 -0
- package/dist/src/register-care/routine-summaries.d.ts +6 -0
- package/dist/src/register-care/routine-summaries.js +89 -0
- package/dist/src/register-care/smartComments.d.ts +5 -0
- package/dist/src/register-care/smartComments.js +243 -0
- package/dist/src/register-care/sourceText.d.ts +8 -0
- package/dist/src/register-care/sourceText.js +15 -0
- package/dist/src/register-care/summaries.d.ts +12 -0
- package/dist/src/register-care/summaries.js +121 -0
- package/dist/src/register-care/summary.d.ts +3 -0
- package/dist/src/register-care/summary.js +474 -0
- package/dist/src/{registerCare → register-care}/tooling.d.ts +7 -6
- package/dist/src/{registerCare → register-care}/tooling.js +17 -6
- package/dist/src/register-care/types.d.ts +170 -0
- package/dist/src/register-care/types.js +1 -0
- package/dist/src/semantics/expression-evaluation.d.ts +29 -0
- package/dist/src/semantics/expression-evaluation.js +409 -0
- package/dist/src/source/logical-lines.d.ts +7 -0
- package/dist/src/source/logical-lines.js +11 -0
- package/dist/src/source/source-file.d.ts +5 -0
- package/dist/src/source/source-file.js +3 -0
- package/dist/src/source/source-span.d.ts +5 -0
- package/dist/src/source/source-span.js +1 -0
- package/dist/src/source/strip-line-comment.d.ts +6 -0
- package/dist/src/source/strip-line-comment.js +53 -0
- package/dist/src/syntax/directive-aliases.d.ts +10 -0
- package/dist/src/syntax/directive-aliases.js +199 -0
- package/dist/src/syntax/parse-diagnostics.d.ts +12 -0
- package/dist/src/syntax/parse-diagnostics.js +18 -0
- package/dist/src/syntax/parse-expression.d.ts +3 -0
- package/dist/src/syntax/parse-expression.js +551 -0
- package/dist/src/syntax/parse-line.d.ts +12 -0
- package/dist/src/syntax/parse-line.js +382 -0
- package/dist/src/tooling/api.d.ts +42 -0
- package/dist/src/tooling/api.js +42 -0
- package/dist/src/tooling/case-style.d.ts +8 -0
- package/dist/src/tooling/case-style.js +163 -0
- package/dist/src/z80/effects.d.ts +3 -3
- package/dist/src/z80/effects.js +349 -302
- package/dist/src/z80/encode.d.ts +2 -10
- package/dist/src/z80/encode.js +951 -374
- package/dist/src/z80/instruction.d.ts +226 -0
- package/dist/src/z80/instruction.js +1 -0
- package/dist/src/z80/parse-instruction.d.ts +7 -0
- package/dist/src/z80/parse-instruction.js +1068 -0
- package/docs/reference/tooling-api.md +68 -9
- package/package.json +22 -3
- /package/dist/{src → legacy-root-azm/src}/analysis.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/analysis.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/compile.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/compile.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/compileShared.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/compileShared.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/diagnosticTypes.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/diagnosticTypes.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/formats/range.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/formats/range.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/formats/types.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/formats/writeAsm80.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/formats/writeAsm80.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/formats/writeBin.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/formats/writeBin.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/formats/writeD8m.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/formats/writeD8m.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/formats/writeListing.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/formats/writeListing.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/asm80/asmLine.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/asm80/asmLine.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/asm80/parseAsmRawValues.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/asm80/parseAsmRawValues.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/asm80/quoteScan.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/asm80/quoteScan.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/ast.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/ast.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/directiveAliases.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/directiveAliases.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/grammarData.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/grammarData.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/immExprUtils.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/immExprUtils.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseAsmFlatDirectiveLine.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseAsmFlatDirectiveLine.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseAsmInstruction.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseAsmInstruction.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseAsmStatements.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseAsmStatements.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseAsmStream.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseAsmStream.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseAsmTopLevel.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseAsmTopLevel.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseDiagnostics.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseDiagnostics.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseEnum.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseEnum.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseImm.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseImm.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseLogicalLines.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseLogicalLines.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseOp.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseOp.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseOpHeader.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseOpHeader.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseOperands.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseOperands.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseParams.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseParams.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseParserRecovery.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseParserRecovery.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseParserShared.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseParserShared.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseRawDataDirectiveStart.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseRawDataDirectiveStart.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseRawDataDirectives.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseRawDataDirectives.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseRecordFieldDecl.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseRecordFieldDecl.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseSourceItemDispatch.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseSourceItemDispatch.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseSourceItemTable.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseSourceItemTable.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseTopLevelCommon.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseTopLevelCommon.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseTypes.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parseTypes.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parser.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/parser.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/source.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/source.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/sourceExtensions.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/frontend/sourceExtensions.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lintCaseStyle.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lintCaseStyle.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmDirectiveLowering.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmDirectiveLowering.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmDirectiveTraversal.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmDirectiveTraversal.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmEquResolution.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmEquResolution.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmInstructionLdHelpers.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmInstructionLdHelpers.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmInstructionLowering.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmInstructionLowering.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmInstructionStream.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmInstructionStream.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmLoweringBranchCall.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmLoweringBranchCall.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmLoweringHost.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmLoweringHost.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmLoweringLd.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmLoweringLd.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmRangeLowering.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmRangeLowering.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmRawDataLowering.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmRawDataLowering.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmSourceEmitter.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmSourceEmitter.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmSourceInstructionLowering.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmSourceInstructionLowering.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmUtils.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/asmUtils.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/assemblerFlowSetup.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/assemblerFlowSetup.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/assemblerLoweringContext.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/assemblerLoweringContext.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/assemblerLoweringContextSplit.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/assemblerLoweringContextSplit.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/assemblerLoweringPhases.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/assemblerLoweringPhases.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/bytePlacement.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/bytePlacement.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/capabilities.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/capabilities.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/eaResolution.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/eaResolution.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emissionCore.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emissionCore.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emit.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emit.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitContextBuilder.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitContextBuilder.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitFinalization.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitFinalization.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitFinalizationSetup.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitFinalizationSetup.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitPhase1BuildProgramLoweringContext.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitPhase1BuildProgramLoweringContext.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitPhase1Helpers.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitPhase1Helpers.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitPhase1Types.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitPhase1Types.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitPhase1WirePipeline.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitPhase1WirePipeline.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitPhase1Workspace.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitPhase1Workspace.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitPipeline.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitPipeline.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitProgramContext.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitProgramContext.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitState.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/emitState.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/fixupBaseResolution.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/fixupBaseResolution.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/fixupEmission.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/fixupEmission.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/immMath.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/immMath.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/inputAssets.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/inputAssets.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/ldEncoding.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/ldEncoding.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/ldEncodingRegMemHelpers.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/ldEncodingRegMemHelpers.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/ldFormSelection.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/ldFormSelection.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/ldLowering.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/ldLowering.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/loweredAsmByteEmission.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/loweredAsmByteEmission.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/loweredAsmPlacement.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/loweredAsmPlacement.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/loweredAsmStreamRecording.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/loweredAsmStreamRecording.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/loweredAsmTypes.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/loweredAsmTypes.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/loweredFormat.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/loweredFormat.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/loweredItemSize.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/loweredItemSize.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/loweringDiagnostics.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/loweringDiagnostics.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/loweringTypes.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/loweringTypes.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/opCandidateRegistry.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/opCandidateRegistry.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/opExpansionExecution.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/opExpansionExecution.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/opExpansionOrchestration.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/opExpansionOrchestration.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/opExpansionStream.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/opExpansionStream.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/opMatching.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/opMatching.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/opSubstitution.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/opSubstitution.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/prescanTypes.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/prescanTypes.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/programLowering.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/programLowering.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/programLoweringDeclarations.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/programLoweringDeclarations.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/programLoweringFinalize.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/programLoweringFinalize.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/programLoweringTraversal.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/programLoweringTraversal.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/programPrescan.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/programPrescan.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/traceFormat.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/lowering/traceFormat.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/packageInfo.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/packageInfo.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/pathCompare.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/pathCompare.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/pipeline.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/analyze.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/analyze.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/annotate.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/annotate.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/boundaryHints.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/boundaryHints.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/carriers.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/carriers.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/controlFlow.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/controlFlow.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/fix.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/fix.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/liveness.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/liveness.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/profiles.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/profiles.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/programModel.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/programModel.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/report.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/report.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/smartComments.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/smartComments.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/sourceText.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/sourceText.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/summary.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/summary.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/types.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/registerCare/types.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/semantics/declVisitor.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/semantics/declVisitor.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/semantics/env.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/semantics/env.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/semantics/layout.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/semantics/layout.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/semantics/layoutCastFold.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/semantics/layoutCastFold.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/semantics/semanticsDiagnostics.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/semantics/semanticsDiagnostics.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/semantics/typeQueries.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/semantics/typeQueries.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/sourceIncludeExpansion.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/sourceIncludeExpansion.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/sourceIncludePaths.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/sourceIncludePaths.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/sourceLoader.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/sourceLoader.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/z80/encodeAlu.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/z80/encodeAlu.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/z80/encodeBitOps.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/z80/encodeBitOps.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/z80/encodeContext.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/z80/encodeContext.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/z80/encodeControl.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/z80/encodeControl.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/z80/encodeCoreOps.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/z80/encodeCoreOps.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/z80/encodeIo.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/z80/encodeIo.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/z80/encodeLd.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/z80/encodeLd.js +0 -0
- /package/dist/{src → legacy-root-azm/src}/z80/encoderRegistry.d.ts +0 -0
- /package/dist/{src → legacy-root-azm/src}/z80/encoderRegistry.js +0 -0
package/dist/src/z80/encode.js
CHANGED
|
@@ -1,412 +1,989 @@
|
|
|
1
|
-
|
|
2
|
-
|
|
3
|
-
|
|
4
|
-
|
|
5
|
-
|
|
6
|
-
|
|
7
|
-
|
|
8
|
-
|
|
9
|
-
|
|
10
|
-
|
|
11
|
-
|
|
12
|
-
|
|
13
|
-
|
|
14
|
-
|
|
15
|
-
|
|
16
|
-
|
|
17
|
-
|
|
18
|
-
|
|
19
|
-
|
|
20
|
-
|
|
21
|
-
|
|
22
|
-
|
|
23
|
-
|
|
1
|
+
export function encodeZ80Instruction(instruction) {
|
|
2
|
+
switch (instruction.mnemonic) {
|
|
3
|
+
case 'nop':
|
|
4
|
+
return { size: 1, fragments: [{ kind: 'bytes', bytes: [0x00] }] };
|
|
5
|
+
case 'ret':
|
|
6
|
+
return { size: 1, fragments: [{ kind: 'bytes', bytes: [0xc9] }] };
|
|
7
|
+
case 'ret-cc':
|
|
8
|
+
return {
|
|
9
|
+
size: 1,
|
|
10
|
+
fragments: [{ kind: 'bytes', bytes: [retConditionOpcode(instruction.condition)] }],
|
|
11
|
+
};
|
|
12
|
+
case 'di':
|
|
13
|
+
case 'ei':
|
|
14
|
+
case 'scf':
|
|
15
|
+
case 'ccf':
|
|
16
|
+
case 'cpl':
|
|
17
|
+
case 'daa':
|
|
18
|
+
case 'exx':
|
|
19
|
+
case 'halt':
|
|
20
|
+
case 'rlca':
|
|
21
|
+
case 'rrca':
|
|
22
|
+
case 'rla':
|
|
23
|
+
case 'rra':
|
|
24
|
+
case 'neg':
|
|
25
|
+
case 'rrd':
|
|
26
|
+
case 'rld':
|
|
27
|
+
case 'ldi':
|
|
28
|
+
case 'ldir':
|
|
29
|
+
case 'ldd':
|
|
30
|
+
case 'lddr':
|
|
31
|
+
case 'cpi':
|
|
32
|
+
case 'cpir':
|
|
33
|
+
case 'cpd':
|
|
34
|
+
case 'cpdr':
|
|
35
|
+
case 'ini':
|
|
36
|
+
case 'inir':
|
|
37
|
+
case 'ind':
|
|
38
|
+
case 'indr':
|
|
39
|
+
case 'outi':
|
|
40
|
+
case 'otir':
|
|
41
|
+
case 'outd':
|
|
42
|
+
case 'otdr':
|
|
43
|
+
case 'reti':
|
|
44
|
+
case 'retn':
|
|
45
|
+
return encodeCore(instruction.mnemonic);
|
|
46
|
+
case 'ex':
|
|
47
|
+
return encodeExchange(instruction.form);
|
|
48
|
+
case 'im':
|
|
49
|
+
return {
|
|
50
|
+
size: 2,
|
|
51
|
+
fragments: [{ kind: 'bytes', bytes: [0xed, imOpcode(instruction.mode)] }],
|
|
52
|
+
};
|
|
53
|
+
case 'rst':
|
|
54
|
+
return {
|
|
55
|
+
size: 1,
|
|
56
|
+
fragments: [{ kind: 'bytes', bytes: [rstOpcode(instruction.vector)] }],
|
|
57
|
+
};
|
|
58
|
+
case 'inc':
|
|
59
|
+
case 'dec':
|
|
60
|
+
return encodeIncDec(instruction.mnemonic, instruction.operand);
|
|
61
|
+
case 'push':
|
|
62
|
+
case 'pop':
|
|
63
|
+
return encodeStack(instruction.mnemonic, instruction.register);
|
|
64
|
+
case 'ld-a-imm':
|
|
65
|
+
return {
|
|
66
|
+
size: 2,
|
|
67
|
+
fragments: [
|
|
68
|
+
{ kind: 'bytes', bytes: [0x3e] },
|
|
69
|
+
{ kind: 'imm8', expression: instruction.expression },
|
|
70
|
+
],
|
|
71
|
+
};
|
|
72
|
+
case 'ld':
|
|
73
|
+
return encodeLd(instruction.target, instruction.source);
|
|
74
|
+
case 'in':
|
|
75
|
+
return encodeIn(instruction.target, instruction.port);
|
|
76
|
+
case 'out':
|
|
77
|
+
return encodeOut(instruction.port, instruction.source);
|
|
78
|
+
case 'bit':
|
|
79
|
+
case 'res':
|
|
80
|
+
case 'set':
|
|
81
|
+
return encodeBitLike(instruction.mnemonic, instruction.bit, instruction.operand, instruction.destination);
|
|
82
|
+
case 'rlc':
|
|
83
|
+
case 'rrc':
|
|
84
|
+
case 'rl':
|
|
85
|
+
case 'rr':
|
|
86
|
+
case 'sla':
|
|
87
|
+
case 'sra':
|
|
88
|
+
case 'sll':
|
|
89
|
+
case 'sls':
|
|
90
|
+
case 'srl':
|
|
91
|
+
return encodeRotateShift(instruction.mnemonic, instruction.operand, instruction.destination);
|
|
92
|
+
case 'add':
|
|
93
|
+
case 'adc':
|
|
94
|
+
if ('target' in instruction) {
|
|
95
|
+
return encode16BitAlu(instruction.mnemonic, instruction.target.register, instruction.source.register);
|
|
96
|
+
}
|
|
97
|
+
return encodeAlu(instruction.mnemonic, instruction.source);
|
|
98
|
+
case 'sub':
|
|
99
|
+
case 'sbc':
|
|
100
|
+
if ('target' in instruction) {
|
|
101
|
+
return encode16BitAlu(instruction.mnemonic, instruction.target.register, instruction.source.register);
|
|
102
|
+
}
|
|
103
|
+
return encodeAlu(instruction.mnemonic, instruction.source);
|
|
104
|
+
case 'and':
|
|
105
|
+
case 'or':
|
|
106
|
+
case 'xor':
|
|
107
|
+
case 'cp':
|
|
108
|
+
return encodeAlu(instruction.mnemonic, instruction.source);
|
|
109
|
+
case 'jp':
|
|
110
|
+
return absoluteTarget(0xc3, instruction.expression);
|
|
111
|
+
case 'jp-cc':
|
|
112
|
+
return absoluteTarget(jpConditionOpcode(instruction.condition), instruction.expression);
|
|
113
|
+
case 'jp-indirect':
|
|
114
|
+
return jumpIndirect(instruction.register);
|
|
115
|
+
case 'call':
|
|
116
|
+
return absoluteTarget(0xcd, instruction.expression);
|
|
117
|
+
case 'call-cc':
|
|
118
|
+
return absoluteTarget(callConditionOpcode(instruction.condition), instruction.expression);
|
|
119
|
+
case 'jr':
|
|
120
|
+
return relativeTarget(0x18, 'jr', instruction.expression);
|
|
121
|
+
case 'jr-cc':
|
|
122
|
+
return relativeTarget(jrConditionOpcode(instruction.condition), `jr ${instruction.condition}`, instruction.expression);
|
|
123
|
+
case 'djnz':
|
|
124
|
+
return relativeTarget(0x10, 'djnz', instruction.expression);
|
|
125
|
+
}
|
|
24
126
|
}
|
|
25
|
-
function
|
|
26
|
-
|
|
27
|
-
|
|
28
|
-
|
|
127
|
+
function encodeExchange(form) {
|
|
128
|
+
switch (form) {
|
|
129
|
+
case 'af-af':
|
|
130
|
+
return { size: 1, fragments: [{ kind: 'bytes', bytes: [0x08] }] };
|
|
131
|
+
case 'de-hl':
|
|
132
|
+
return { size: 1, fragments: [{ kind: 'bytes', bytes: [0xeb] }] };
|
|
133
|
+
case 'sp-hl':
|
|
134
|
+
return { size: 1, fragments: [{ kind: 'bytes', bytes: [0xe3] }] };
|
|
135
|
+
case 'sp-ix':
|
|
136
|
+
return { size: 2, fragments: [{ kind: 'bytes', bytes: [0xdd, 0xe3] }] };
|
|
137
|
+
case 'sp-iy':
|
|
138
|
+
return { size: 2, fragments: [{ kind: 'bytes', bytes: [0xfd, 0xe3] }] };
|
|
139
|
+
}
|
|
29
140
|
}
|
|
30
|
-
function
|
|
31
|
-
|
|
141
|
+
function encodeCore(mnemonic) {
|
|
142
|
+
const opcode = coreOpcode(mnemonic);
|
|
143
|
+
return {
|
|
144
|
+
size: opcode.length,
|
|
145
|
+
fragments: [{ kind: 'bytes', bytes: opcode }],
|
|
146
|
+
};
|
|
32
147
|
}
|
|
33
|
-
function
|
|
34
|
-
|
|
148
|
+
function coreOpcode(mnemonic) {
|
|
149
|
+
switch (mnemonic) {
|
|
150
|
+
case 'di':
|
|
151
|
+
return [0xf3];
|
|
152
|
+
case 'ei':
|
|
153
|
+
return [0xfb];
|
|
154
|
+
case 'scf':
|
|
155
|
+
return [0x37];
|
|
156
|
+
case 'ccf':
|
|
157
|
+
return [0x3f];
|
|
158
|
+
case 'cpl':
|
|
159
|
+
return [0x2f];
|
|
160
|
+
case 'daa':
|
|
161
|
+
return [0x27];
|
|
162
|
+
case 'exx':
|
|
163
|
+
return [0xd9];
|
|
164
|
+
case 'halt':
|
|
165
|
+
return [0x76];
|
|
166
|
+
case 'rlca':
|
|
167
|
+
return [0x07];
|
|
168
|
+
case 'rrca':
|
|
169
|
+
return [0x0f];
|
|
170
|
+
case 'rla':
|
|
171
|
+
return [0x17];
|
|
172
|
+
case 'rra':
|
|
173
|
+
return [0x1f];
|
|
174
|
+
case 'neg':
|
|
175
|
+
return [0xed, 0x44];
|
|
176
|
+
case 'rrd':
|
|
177
|
+
return [0xed, 0x67];
|
|
178
|
+
case 'rld':
|
|
179
|
+
return [0xed, 0x6f];
|
|
180
|
+
case 'ldi':
|
|
181
|
+
return [0xed, 0xa0];
|
|
182
|
+
case 'ldir':
|
|
183
|
+
return [0xed, 0xb0];
|
|
184
|
+
case 'ldd':
|
|
185
|
+
return [0xed, 0xa8];
|
|
186
|
+
case 'lddr':
|
|
187
|
+
return [0xed, 0xb8];
|
|
188
|
+
case 'cpi':
|
|
189
|
+
return [0xed, 0xa1];
|
|
190
|
+
case 'cpir':
|
|
191
|
+
return [0xed, 0xb1];
|
|
192
|
+
case 'cpd':
|
|
193
|
+
return [0xed, 0xa9];
|
|
194
|
+
case 'cpdr':
|
|
195
|
+
return [0xed, 0xb9];
|
|
196
|
+
case 'ini':
|
|
197
|
+
return [0xed, 0xa2];
|
|
198
|
+
case 'inir':
|
|
199
|
+
return [0xed, 0xb2];
|
|
200
|
+
case 'ind':
|
|
201
|
+
return [0xed, 0xaa];
|
|
202
|
+
case 'indr':
|
|
203
|
+
return [0xed, 0xba];
|
|
204
|
+
case 'outi':
|
|
205
|
+
return [0xed, 0xa3];
|
|
206
|
+
case 'otir':
|
|
207
|
+
return [0xed, 0xb3];
|
|
208
|
+
case 'outd':
|
|
209
|
+
return [0xed, 0xab];
|
|
210
|
+
case 'otdr':
|
|
211
|
+
return [0xed, 0xbb];
|
|
212
|
+
case 'reti':
|
|
213
|
+
return [0xed, 0x4d];
|
|
214
|
+
case 'retn':
|
|
215
|
+
return [0xed, 0x45];
|
|
216
|
+
}
|
|
35
217
|
}
|
|
36
|
-
function
|
|
37
|
-
|
|
218
|
+
function encodeIn(target, port) {
|
|
219
|
+
if (port.kind === 'c') {
|
|
220
|
+
const opcode = target ? 0x40 + register8Code(target.register) * 8 : 0x70;
|
|
221
|
+
return { size: 2, fragments: [{ kind: 'bytes', bytes: [0xed, opcode] }] };
|
|
222
|
+
}
|
|
223
|
+
return {
|
|
224
|
+
size: 2,
|
|
225
|
+
fragments: [
|
|
226
|
+
{ kind: 'bytes', bytes: [0xdb] },
|
|
227
|
+
{
|
|
228
|
+
kind: 'port8',
|
|
229
|
+
expression: port.expression,
|
|
230
|
+
message: 'in a,(n) expects an imm8 port number',
|
|
231
|
+
},
|
|
232
|
+
],
|
|
233
|
+
};
|
|
38
234
|
}
|
|
39
|
-
function
|
|
40
|
-
|
|
41
|
-
?
|
|
42
|
-
:
|
|
43
|
-
? op.expr.name.toUpperCase()
|
|
44
|
-
: undefined;
|
|
45
|
-
if (!name)
|
|
46
|
-
return undefined;
|
|
47
|
-
switch (name) {
|
|
48
|
-
case 'A':
|
|
49
|
-
case 'B':
|
|
50
|
-
case 'C':
|
|
51
|
-
case 'D':
|
|
52
|
-
case 'E':
|
|
53
|
-
case 'H':
|
|
54
|
-
case 'L':
|
|
55
|
-
case 'BC':
|
|
56
|
-
case 'DE':
|
|
57
|
-
case 'HL':
|
|
58
|
-
case 'SP':
|
|
59
|
-
case 'AF':
|
|
60
|
-
case 'IX':
|
|
61
|
-
case 'IY':
|
|
62
|
-
case 'IXH':
|
|
63
|
-
case 'IXL':
|
|
64
|
-
case 'IYH':
|
|
65
|
-
case 'IYL':
|
|
66
|
-
return name;
|
|
67
|
-
default:
|
|
68
|
-
return undefined;
|
|
235
|
+
function encodeOut(port, source) {
|
|
236
|
+
if (port.kind === 'c') {
|
|
237
|
+
const opcode = source.kind === 'zero' ? 0x71 : 0x41 + register8Code(source.register) * 8;
|
|
238
|
+
return { size: 2, fragments: [{ kind: 'bytes', bytes: [0xed, opcode] }] };
|
|
69
239
|
}
|
|
240
|
+
return {
|
|
241
|
+
size: 2,
|
|
242
|
+
fragments: [
|
|
243
|
+
{ kind: 'bytes', bytes: [0xd3] },
|
|
244
|
+
{
|
|
245
|
+
kind: 'port8',
|
|
246
|
+
expression: port.expression,
|
|
247
|
+
message: 'out (n),a expects an imm8 port number',
|
|
248
|
+
},
|
|
249
|
+
],
|
|
250
|
+
};
|
|
70
251
|
}
|
|
71
|
-
function
|
|
72
|
-
switch (
|
|
73
|
-
case
|
|
74
|
-
return
|
|
75
|
-
case
|
|
76
|
-
return
|
|
77
|
-
case
|
|
78
|
-
return
|
|
79
|
-
|
|
80
|
-
|
|
81
|
-
|
|
82
|
-
|
|
83
|
-
case
|
|
84
|
-
return
|
|
85
|
-
case
|
|
86
|
-
return
|
|
87
|
-
|
|
88
|
-
return
|
|
89
|
-
|
|
90
|
-
|
|
91
|
-
|
|
92
|
-
|
|
93
|
-
|
|
94
|
-
|
|
95
|
-
|
|
96
|
-
|
|
97
|
-
case
|
|
98
|
-
return
|
|
99
|
-
case 'IXL':
|
|
100
|
-
return { prefix: 0xdd, code: 5, display: 'IXL' };
|
|
101
|
-
case 'IYH':
|
|
102
|
-
return { prefix: 0xfd, code: 4, display: 'IYH' };
|
|
103
|
-
case 'IYL':
|
|
104
|
-
return { prefix: 0xfd, code: 5, display: 'IYL' };
|
|
252
|
+
function imOpcode(mode) {
|
|
253
|
+
switch (mode) {
|
|
254
|
+
case 0:
|
|
255
|
+
return 0x46;
|
|
256
|
+
case 1:
|
|
257
|
+
return 0x56;
|
|
258
|
+
case 2:
|
|
259
|
+
return 0x5e;
|
|
260
|
+
}
|
|
261
|
+
}
|
|
262
|
+
function rstOpcode(vector) {
|
|
263
|
+
switch (vector) {
|
|
264
|
+
case 0:
|
|
265
|
+
return 0xc7;
|
|
266
|
+
case 8:
|
|
267
|
+
return 0xcf;
|
|
268
|
+
case 16:
|
|
269
|
+
return 0xd7;
|
|
270
|
+
case 24:
|
|
271
|
+
return 0xdf;
|
|
272
|
+
case 32:
|
|
273
|
+
return 0xe7;
|
|
274
|
+
case 40:
|
|
275
|
+
return 0xef;
|
|
276
|
+
case 48:
|
|
277
|
+
return 0xf7;
|
|
278
|
+
case 56:
|
|
279
|
+
return 0xff;
|
|
105
280
|
default:
|
|
106
|
-
|
|
281
|
+
throw new Error(`invalid RST vector: ${vector}`);
|
|
107
282
|
}
|
|
108
283
|
}
|
|
109
|
-
function
|
|
110
|
-
|
|
284
|
+
function encodeIncDec(mnemonic, operand) {
|
|
285
|
+
if (operand.kind === 'reg8') {
|
|
286
|
+
return {
|
|
287
|
+
size: 1,
|
|
288
|
+
fragments: [
|
|
289
|
+
{
|
|
290
|
+
kind: 'bytes',
|
|
291
|
+
bytes: [incDecBase(mnemonic).reg8 + register8Code(operand.register) * 8],
|
|
292
|
+
},
|
|
293
|
+
],
|
|
294
|
+
};
|
|
295
|
+
}
|
|
296
|
+
if (operand.kind === 'reg16') {
|
|
297
|
+
const bytes = incDecRegister16Opcode(mnemonic, operand.register);
|
|
298
|
+
return { size: bytes.length, fragments: [{ kind: 'bytes', bytes }] };
|
|
299
|
+
}
|
|
300
|
+
if (operand.kind === 'reg-half-index') {
|
|
301
|
+
const bytes = incDecHalfIndexOpcode(mnemonic, operand.register);
|
|
302
|
+
return { size: bytes.length, fragments: [{ kind: 'bytes', bytes }] };
|
|
303
|
+
}
|
|
304
|
+
if (operand.kind === 'indexed') {
|
|
305
|
+
return {
|
|
306
|
+
size: 3,
|
|
307
|
+
fragments: [
|
|
308
|
+
{ kind: 'bytes', bytes: [indexPrefix(operand.register), incDecBase(mnemonic).memHl] },
|
|
309
|
+
{ kind: 'disp8', expression: operand.displacement },
|
|
310
|
+
],
|
|
311
|
+
};
|
|
312
|
+
}
|
|
313
|
+
return {
|
|
314
|
+
size: 1,
|
|
315
|
+
fragments: [{ kind: 'bytes', bytes: [incDecBase(mnemonic).memHl] }],
|
|
316
|
+
};
|
|
111
317
|
}
|
|
112
|
-
function
|
|
113
|
-
return
|
|
318
|
+
function incDecBase(mnemonic) {
|
|
319
|
+
return mnemonic === 'inc' ? { reg8: 0x04, memHl: 0x34 } : { reg8: 0x05, memHl: 0x35 };
|
|
114
320
|
}
|
|
115
|
-
function
|
|
116
|
-
|
|
117
|
-
|
|
118
|
-
|
|
119
|
-
|
|
120
|
-
|
|
121
|
-
|
|
122
|
-
|
|
321
|
+
function incDecRegister16Opcode(mnemonic, register) {
|
|
322
|
+
const base = mnemonic === 'inc' ? 0x03 : 0x0b;
|
|
323
|
+
switch (register) {
|
|
324
|
+
case 'bc':
|
|
325
|
+
return [base];
|
|
326
|
+
case 'de':
|
|
327
|
+
return [base + 0x10];
|
|
328
|
+
case 'hl':
|
|
329
|
+
return [base + 0x20];
|
|
330
|
+
case 'sp':
|
|
331
|
+
return [base + 0x30];
|
|
332
|
+
case 'ix':
|
|
333
|
+
return [0xdd, base + 0x20];
|
|
334
|
+
case 'iy':
|
|
335
|
+
return [0xfd, base + 0x20];
|
|
336
|
+
}
|
|
123
337
|
}
|
|
124
|
-
function
|
|
125
|
-
|
|
126
|
-
|
|
127
|
-
|
|
128
|
-
|
|
129
|
-
|
|
130
|
-
|
|
131
|
-
|
|
132
|
-
|
|
133
|
-
return
|
|
134
|
-
|
|
135
|
-
|
|
136
|
-
|
|
137
|
-
|
|
138
|
-
|
|
338
|
+
function incDecHalfIndexOpcode(mnemonic, register) {
|
|
339
|
+
const lowOpcode = mnemonic === 'inc' ? 0x2c : 0x2d;
|
|
340
|
+
const highOpcode = mnemonic === 'inc' ? 0x24 : 0x25;
|
|
341
|
+
switch (register) {
|
|
342
|
+
case 'ixh':
|
|
343
|
+
return [0xdd, highOpcode];
|
|
344
|
+
case 'ixl':
|
|
345
|
+
return [0xdd, lowOpcode];
|
|
346
|
+
case 'iyh':
|
|
347
|
+
return [0xfd, highOpcode];
|
|
348
|
+
case 'iyl':
|
|
349
|
+
return [0xfd, lowOpcode];
|
|
350
|
+
}
|
|
351
|
+
}
|
|
352
|
+
function encodeStack(mnemonic, register) {
|
|
353
|
+
const bytes = stackOpcode(mnemonic, register);
|
|
354
|
+
return { size: bytes.length, fragments: [{ kind: 'bytes', bytes }] };
|
|
355
|
+
}
|
|
356
|
+
function encodeBitLike(mnemonic, bit, operand, destination) {
|
|
357
|
+
const operandCode = destination ? register8Code(destination.register) : cbOperandCode(operand);
|
|
358
|
+
const opcode = bitLikeOpcodeBase(mnemonic) + bit * 8 + operandCode;
|
|
359
|
+
return operand.kind === 'indexed'
|
|
360
|
+
? indexedCbInstruction(operand, opcode, mnemonic)
|
|
361
|
+
: cbInstruction(opcode);
|
|
362
|
+
}
|
|
363
|
+
function encodeRotateShift(mnemonic, operand, destination) {
|
|
364
|
+
const operandCode = destination ? register8Code(destination.register) : cbOperandCode(operand);
|
|
365
|
+
const opcode = rotateShiftOpcodeBase(mnemonic) + operandCode;
|
|
366
|
+
return operand.kind === 'indexed'
|
|
367
|
+
? indexedCbInstruction(operand, opcode, mnemonic)
|
|
368
|
+
: cbInstruction(opcode);
|
|
369
|
+
}
|
|
370
|
+
function cbInstruction(opcode) {
|
|
371
|
+
return {
|
|
372
|
+
size: 2,
|
|
373
|
+
fragments: [{ kind: 'bytes', bytes: [0xcb, opcode] }],
|
|
374
|
+
};
|
|
375
|
+
}
|
|
376
|
+
function indexedCbInstruction(operand, opcode, mnemonic) {
|
|
377
|
+
return {
|
|
378
|
+
size: 4,
|
|
379
|
+
fragments: [
|
|
380
|
+
{ kind: 'bytes', bytes: [indexPrefix(operand.register), 0xcb] },
|
|
381
|
+
{
|
|
382
|
+
kind: 'disp8',
|
|
383
|
+
expression: operand.displacement,
|
|
384
|
+
message: `${mnemonic} (ix/iy+disp) expects disp8`,
|
|
385
|
+
},
|
|
386
|
+
{ kind: 'bytes', bytes: [opcode] },
|
|
387
|
+
],
|
|
139
388
|
};
|
|
140
|
-
|
|
141
|
-
|
|
389
|
+
}
|
|
390
|
+
function bitLikeOpcodeBase(mnemonic) {
|
|
391
|
+
switch (mnemonic) {
|
|
392
|
+
case 'bit':
|
|
393
|
+
return 0x40;
|
|
394
|
+
case 'res':
|
|
395
|
+
return 0x80;
|
|
396
|
+
case 'set':
|
|
397
|
+
return 0xc0;
|
|
142
398
|
}
|
|
143
|
-
|
|
144
|
-
|
|
145
|
-
|
|
146
|
-
|
|
147
|
-
|
|
148
|
-
|
|
399
|
+
}
|
|
400
|
+
function rotateShiftOpcodeBase(mnemonic) {
|
|
401
|
+
switch (mnemonic) {
|
|
402
|
+
case 'rlc':
|
|
403
|
+
return 0x00;
|
|
404
|
+
case 'rrc':
|
|
405
|
+
return 0x08;
|
|
406
|
+
case 'rl':
|
|
407
|
+
return 0x10;
|
|
408
|
+
case 'rr':
|
|
409
|
+
return 0x18;
|
|
410
|
+
case 'sla':
|
|
411
|
+
return 0x20;
|
|
412
|
+
case 'sra':
|
|
413
|
+
return 0x28;
|
|
414
|
+
case 'sll':
|
|
415
|
+
case 'sls':
|
|
416
|
+
return 0x30;
|
|
417
|
+
case 'srl':
|
|
418
|
+
return 0x38;
|
|
149
419
|
}
|
|
150
|
-
|
|
151
|
-
|
|
420
|
+
}
|
|
421
|
+
function cbOperandCode(operand) {
|
|
422
|
+
return operand.kind === 'reg8' ? register8Code(operand.register) : 0x06;
|
|
423
|
+
}
|
|
424
|
+
function stackOpcode(mnemonic, register) {
|
|
425
|
+
const base = mnemonic === 'push' ? 0xc5 : 0xc1;
|
|
426
|
+
switch (register) {
|
|
427
|
+
case 'bc':
|
|
428
|
+
return [base];
|
|
429
|
+
case 'de':
|
|
430
|
+
return [base + 0x10];
|
|
431
|
+
case 'hl':
|
|
432
|
+
return [base + 0x20];
|
|
433
|
+
case 'af':
|
|
434
|
+
return [base + 0x30];
|
|
435
|
+
case 'ix':
|
|
436
|
+
return [0xdd, base + 0x20];
|
|
437
|
+
case 'iy':
|
|
438
|
+
return [0xfd, base + 0x20];
|
|
152
439
|
}
|
|
153
|
-
|
|
154
|
-
|
|
440
|
+
}
|
|
441
|
+
function encode16BitAlu(mnemonic, target, source) {
|
|
442
|
+
if ((target === 'ix' || target === 'iy') && mnemonic !== 'add') {
|
|
443
|
+
throw new Error(`unsupported indexed ${mnemonic.toUpperCase()} target: ${target}`);
|
|
155
444
|
}
|
|
156
|
-
|
|
445
|
+
const opcode = target === 'ix' || target === 'iy'
|
|
446
|
+
? indexedAddOpcode(target, source)
|
|
447
|
+
: hlAluOpcode(mnemonic, source);
|
|
448
|
+
return {
|
|
449
|
+
size: opcode.length,
|
|
450
|
+
fragments: [{ kind: 'bytes', bytes: opcode }],
|
|
451
|
+
};
|
|
157
452
|
}
|
|
158
|
-
function
|
|
159
|
-
|
|
160
|
-
|
|
161
|
-
|
|
162
|
-
|
|
163
|
-
|
|
164
|
-
|
|
165
|
-
|
|
166
|
-
|
|
167
|
-
|
|
168
|
-
|
|
169
|
-
|
|
170
|
-
return evalImmExpr(ea.expr, env);
|
|
171
|
-
case 'EaAdd': {
|
|
172
|
-
const base = evalEaAbs16(ea.base);
|
|
173
|
-
const delta = evalImmExpr(ea.offset, env);
|
|
174
|
-
if (base === undefined || delta === undefined)
|
|
175
|
-
return undefined;
|
|
176
|
-
return base + delta;
|
|
453
|
+
function indexedAddOpcode(target, source) {
|
|
454
|
+
const prefix = indexPrefix(target);
|
|
455
|
+
switch (source) {
|
|
456
|
+
case 'bc':
|
|
457
|
+
return [prefix, 0x09];
|
|
458
|
+
case 'de':
|
|
459
|
+
return [prefix, 0x19];
|
|
460
|
+
case 'sp':
|
|
461
|
+
return [prefix, 0x39];
|
|
462
|
+
case 'ix':
|
|
463
|
+
if (target === 'ix') {
|
|
464
|
+
return [prefix, 0x29];
|
|
177
465
|
}
|
|
178
|
-
|
|
179
|
-
|
|
180
|
-
|
|
181
|
-
|
|
182
|
-
return undefined;
|
|
183
|
-
return base - delta;
|
|
466
|
+
break;
|
|
467
|
+
case 'iy':
|
|
468
|
+
if (target === 'iy') {
|
|
469
|
+
return [prefix, 0x29];
|
|
184
470
|
}
|
|
185
|
-
|
|
186
|
-
|
|
187
|
-
|
|
188
|
-
};
|
|
189
|
-
return evalEaAbs16(op.expr);
|
|
471
|
+
break;
|
|
472
|
+
}
|
|
473
|
+
throw new Error(`unsupported indexed ADD source: ${source}`);
|
|
190
474
|
}
|
|
191
|
-
function
|
|
192
|
-
|
|
193
|
-
|
|
194
|
-
|
|
195
|
-
|
|
196
|
-
|
|
475
|
+
function hlAluOpcode(mnemonic, source) {
|
|
476
|
+
const registerCode = register16Code(source);
|
|
477
|
+
switch (mnemonic) {
|
|
478
|
+
case 'add':
|
|
479
|
+
return [0x09 + registerCode * 0x10];
|
|
480
|
+
case 'adc':
|
|
481
|
+
return [0xed, 0x4a + registerCode * 0x10];
|
|
482
|
+
case 'sbc':
|
|
483
|
+
return [0xed, 0x42 + registerCode * 0x10];
|
|
484
|
+
}
|
|
197
485
|
}
|
|
198
|
-
function
|
|
199
|
-
|
|
200
|
-
|
|
201
|
-
|
|
202
|
-
|
|
203
|
-
|
|
204
|
-
|
|
486
|
+
function encodeAlu(mnemonic, source) {
|
|
487
|
+
const opcodes = aluOpcodes(mnemonic);
|
|
488
|
+
if (source.kind === 'reg8') {
|
|
489
|
+
return {
|
|
490
|
+
size: 1,
|
|
491
|
+
fragments: [
|
|
492
|
+
{ kind: 'bytes', bytes: [opcodes.registerBase + register8Code(source.register)] },
|
|
493
|
+
],
|
|
494
|
+
};
|
|
495
|
+
}
|
|
496
|
+
if (source.kind === 'reg-half-index') {
|
|
497
|
+
return {
|
|
498
|
+
size: 2,
|
|
499
|
+
fragments: [
|
|
500
|
+
{
|
|
501
|
+
kind: 'bytes',
|
|
502
|
+
bytes: [
|
|
503
|
+
halfIndexPrefix(source, source),
|
|
504
|
+
opcodes.registerBase + halfIndexRegisterCode(source.register),
|
|
505
|
+
],
|
|
506
|
+
},
|
|
507
|
+
],
|
|
508
|
+
};
|
|
509
|
+
}
|
|
510
|
+
if (source.kind === 'reg-indirect' && source.register === 'hl') {
|
|
511
|
+
return { size: 1, fragments: [{ kind: 'bytes', bytes: [opcodes.memHl] }] };
|
|
512
|
+
}
|
|
513
|
+
if (source.kind === 'indexed') {
|
|
514
|
+
return {
|
|
515
|
+
size: 3,
|
|
516
|
+
fragments: [
|
|
517
|
+
{ kind: 'bytes', bytes: [indexPrefix(source.register), opcodes.memHl] },
|
|
518
|
+
{ kind: 'disp8', expression: source.displacement },
|
|
519
|
+
],
|
|
520
|
+
};
|
|
521
|
+
}
|
|
522
|
+
if (source.kind === 'imm') {
|
|
523
|
+
return {
|
|
524
|
+
size: 2,
|
|
525
|
+
fragments: [
|
|
526
|
+
{ kind: 'bytes', bytes: [opcodes.immediate] },
|
|
527
|
+
{ kind: 'imm8', expression: source.expression },
|
|
528
|
+
],
|
|
529
|
+
};
|
|
530
|
+
}
|
|
531
|
+
return { size: 0, fragments: [] };
|
|
532
|
+
}
|
|
533
|
+
function aluOpcodes(mnemonic) {
|
|
534
|
+
switch (mnemonic) {
|
|
535
|
+
case 'add':
|
|
536
|
+
return { registerBase: 0x80, immediate: 0xc6, memHl: 0x86 };
|
|
537
|
+
case 'adc':
|
|
538
|
+
return { registerBase: 0x88, immediate: 0xce, memHl: 0x8e };
|
|
539
|
+
case 'sub':
|
|
540
|
+
return { registerBase: 0x90, immediate: 0xd6, memHl: 0x96 };
|
|
541
|
+
case 'sbc':
|
|
542
|
+
return { registerBase: 0x98, immediate: 0xde, memHl: 0x9e };
|
|
543
|
+
case 'and':
|
|
544
|
+
return { registerBase: 0xa0, immediate: 0xe6, memHl: 0xa6 };
|
|
545
|
+
case 'or':
|
|
546
|
+
return { registerBase: 0xb0, immediate: 0xf6, memHl: 0xb6 };
|
|
547
|
+
case 'xor':
|
|
548
|
+
return { registerBase: 0xa8, immediate: 0xee, memHl: 0xae };
|
|
549
|
+
case 'cp':
|
|
550
|
+
return { registerBase: 0xb8, immediate: 0xfe, memHl: 0xbe };
|
|
551
|
+
}
|
|
552
|
+
}
|
|
553
|
+
const LD_UNSUPPORTED_FORM_MESSAGE = 'ld expects a supported register/memory/immediate transfer form';
|
|
554
|
+
function encodeLd(target, source) {
|
|
555
|
+
const legacyReg16Pair = encodeLegacyReg16ByteTransferLd(target, source);
|
|
556
|
+
if (legacyReg16Pair) {
|
|
557
|
+
return legacyReg16Pair;
|
|
558
|
+
}
|
|
559
|
+
const specialRegisterLd = encodeSpecialRegisterLd(target, source);
|
|
560
|
+
if (specialRegisterLd) {
|
|
561
|
+
return specialRegisterLd;
|
|
562
|
+
}
|
|
563
|
+
if (target.kind === 'reg8' && source.kind === 'imm') {
|
|
564
|
+
return {
|
|
565
|
+
size: 2,
|
|
566
|
+
fragments: [
|
|
567
|
+
{ kind: 'bytes', bytes: [0x06 + register8Code(target.register) * 8] },
|
|
568
|
+
{
|
|
569
|
+
kind: 'imm8',
|
|
570
|
+
expression: source.expression,
|
|
571
|
+
failureMessage: LD_UNSUPPORTED_FORM_MESSAGE,
|
|
572
|
+
},
|
|
573
|
+
],
|
|
574
|
+
};
|
|
575
|
+
}
|
|
576
|
+
if (target.kind === 'reg8' && source.kind === 'reg8') {
|
|
577
|
+
return {
|
|
578
|
+
size: 1,
|
|
579
|
+
fragments: [
|
|
580
|
+
{
|
|
581
|
+
kind: 'bytes',
|
|
582
|
+
bytes: [0x40 + register8Code(target.register) * 8 + register8Code(source.register)],
|
|
583
|
+
},
|
|
584
|
+
],
|
|
585
|
+
};
|
|
586
|
+
}
|
|
587
|
+
if (target.kind === 'reg8' && target.register === 'a' && source.kind === 'mem-abs') {
|
|
588
|
+
return absoluteLd(0x3a, source.expression);
|
|
589
|
+
}
|
|
590
|
+
if (target.kind === 'mem-abs' && source.kind === 'reg8' && source.register === 'a') {
|
|
591
|
+
return absoluteLd(0x32, target.expression);
|
|
592
|
+
}
|
|
593
|
+
if ((target.kind === 'reg8' || target.kind === 'reg-half-index') &&
|
|
594
|
+
(source.kind === 'reg8' || source.kind === 'reg-half-index') &&
|
|
595
|
+
isEncodableHalfIndexLd(target, source)) {
|
|
596
|
+
const prefix = halfIndexPrefix(target, source);
|
|
597
|
+
return {
|
|
598
|
+
size: 2,
|
|
599
|
+
fragments: [
|
|
600
|
+
{
|
|
601
|
+
kind: 'bytes',
|
|
602
|
+
bytes: [prefix, 0x40 + byteRegisterCode(target) * 8 + byteRegisterCode(source)],
|
|
603
|
+
},
|
|
604
|
+
],
|
|
605
|
+
};
|
|
606
|
+
}
|
|
607
|
+
if (target.kind === 'reg16' && source.kind === 'imm') {
|
|
608
|
+
return {
|
|
609
|
+
size: 3,
|
|
610
|
+
fragments: [
|
|
611
|
+
{ kind: 'bytes', bytes: [0x01 + register16Code(target.register) * 0x10] },
|
|
612
|
+
{ kind: 'abs16', expression: source.expression },
|
|
613
|
+
],
|
|
614
|
+
};
|
|
615
|
+
}
|
|
616
|
+
if (target.kind === 'reg-index16' && source.kind === 'imm') {
|
|
617
|
+
return {
|
|
618
|
+
size: 4,
|
|
619
|
+
fragments: [
|
|
620
|
+
{ kind: 'bytes', bytes: [indexPrefix(target.register), 0x21] },
|
|
621
|
+
{ kind: 'abs16', expression: source.expression },
|
|
622
|
+
],
|
|
623
|
+
};
|
|
624
|
+
}
|
|
625
|
+
if (target.kind === 'reg16' &&
|
|
626
|
+
target.register === 'sp' &&
|
|
627
|
+
((source.kind === 'reg16' && source.register === 'hl') || source.kind === 'reg-index16')) {
|
|
628
|
+
return {
|
|
629
|
+
size: source.kind === 'reg-index16' ? 2 : 1,
|
|
630
|
+
fragments: [{ kind: 'bytes', bytes: loadSpOpcode(source.register) }],
|
|
631
|
+
};
|
|
632
|
+
}
|
|
633
|
+
if (target.kind === 'reg16' && source.kind === 'mem-abs') {
|
|
634
|
+
return absoluteRegister16Load(target.register, source.expression);
|
|
635
|
+
}
|
|
636
|
+
if (target.kind === 'reg-index16' && source.kind === 'mem-abs') {
|
|
637
|
+
return prefixedAbsoluteLd(indexPrefix(target.register), 0x2a, source.expression);
|
|
638
|
+
}
|
|
639
|
+
if (target.kind === 'mem-abs' && source.kind === 'reg16') {
|
|
640
|
+
return absoluteRegister16Store(source.register, target.expression);
|
|
641
|
+
}
|
|
642
|
+
if (target.kind === 'mem-abs' && source.kind === 'reg-index16') {
|
|
643
|
+
return prefixedAbsoluteLd(indexPrefix(source.register), 0x22, target.expression);
|
|
644
|
+
}
|
|
645
|
+
if (target.kind === 'reg8' && target.register === 'a' && source.kind === 'reg-indirect') {
|
|
646
|
+
return {
|
|
647
|
+
size: 1,
|
|
648
|
+
fragments: [{ kind: 'bytes', bytes: [loadAFromIndirectOpcode(source.register)] }],
|
|
649
|
+
};
|
|
650
|
+
}
|
|
651
|
+
if (target.kind === 'reg-indirect' && source.kind === 'reg8' && source.register === 'a') {
|
|
652
|
+
return {
|
|
653
|
+
size: 1,
|
|
654
|
+
fragments: [{ kind: 'bytes', bytes: [storeAToIndirectOpcode(target.register)] }],
|
|
655
|
+
};
|
|
656
|
+
}
|
|
657
|
+
if (target.kind === 'reg-indirect' && target.register === 'hl' && source.kind === 'reg8') {
|
|
658
|
+
return {
|
|
659
|
+
size: 1,
|
|
660
|
+
fragments: [{ kind: 'bytes', bytes: [0x70 + register8Code(source.register)] }],
|
|
661
|
+
};
|
|
662
|
+
}
|
|
663
|
+
if (target.kind === 'reg-indirect' && target.register === 'hl' && source.kind === 'imm') {
|
|
664
|
+
return {
|
|
665
|
+
size: 2,
|
|
666
|
+
fragments: [
|
|
667
|
+
{ kind: 'bytes', bytes: [0x36] },
|
|
668
|
+
{
|
|
669
|
+
kind: 'imm8',
|
|
670
|
+
expression: source.expression,
|
|
671
|
+
failureMessage: LD_UNSUPPORTED_FORM_MESSAGE,
|
|
672
|
+
},
|
|
673
|
+
],
|
|
674
|
+
};
|
|
675
|
+
}
|
|
676
|
+
if (target.kind === 'reg8' && source.kind === 'reg-indirect' && source.register === 'hl') {
|
|
677
|
+
return {
|
|
678
|
+
size: 1,
|
|
679
|
+
fragments: [{ kind: 'bytes', bytes: [0x46 + register8Code(target.register) * 8] }],
|
|
680
|
+
};
|
|
681
|
+
}
|
|
682
|
+
if (target.kind === 'reg8' && source.kind === 'indexed') {
|
|
683
|
+
return {
|
|
684
|
+
size: 3,
|
|
685
|
+
fragments: [
|
|
686
|
+
{
|
|
687
|
+
kind: 'bytes',
|
|
688
|
+
bytes: [indexPrefix(source.register), 0x46 + register8Code(target.register) * 8],
|
|
689
|
+
},
|
|
690
|
+
{
|
|
691
|
+
kind: 'disp8',
|
|
692
|
+
expression: source.displacement,
|
|
693
|
+
message: 'ld (ix/iy+disp) expects disp8',
|
|
694
|
+
},
|
|
695
|
+
],
|
|
696
|
+
};
|
|
697
|
+
}
|
|
698
|
+
if (target.kind === 'indexed' && source.kind === 'reg8') {
|
|
699
|
+
return {
|
|
700
|
+
size: 3,
|
|
701
|
+
fragments: [
|
|
702
|
+
{
|
|
703
|
+
kind: 'bytes',
|
|
704
|
+
bytes: [indexPrefix(target.register), 0x70 + register8Code(source.register)],
|
|
705
|
+
},
|
|
706
|
+
{
|
|
707
|
+
kind: 'disp8',
|
|
708
|
+
expression: target.displacement,
|
|
709
|
+
message: 'ld (ix/iy+disp) expects disp8',
|
|
710
|
+
},
|
|
711
|
+
],
|
|
712
|
+
};
|
|
713
|
+
}
|
|
714
|
+
if (target.kind === 'indexed' && source.kind === 'imm') {
|
|
715
|
+
return {
|
|
716
|
+
size: 4,
|
|
717
|
+
fragments: [
|
|
718
|
+
{ kind: 'bytes', bytes: [indexPrefix(target.register), 0x36] },
|
|
719
|
+
{
|
|
720
|
+
kind: 'disp8',
|
|
721
|
+
expression: target.displacement,
|
|
722
|
+
message: 'ld (ix/iy+disp), n expects disp8',
|
|
723
|
+
},
|
|
724
|
+
{
|
|
725
|
+
kind: 'imm8',
|
|
726
|
+
expression: source.expression,
|
|
727
|
+
failureMessage: LD_UNSUPPORTED_FORM_MESSAGE,
|
|
728
|
+
},
|
|
729
|
+
],
|
|
730
|
+
};
|
|
731
|
+
}
|
|
732
|
+
return {
|
|
733
|
+
size: 0,
|
|
734
|
+
fragments: [],
|
|
735
|
+
};
|
|
736
|
+
}
|
|
737
|
+
function encodeLegacyReg16ByteTransferLd(target, source) {
|
|
738
|
+
if (target.kind !== 'reg16' || source.kind !== 'reg16') {
|
|
205
739
|
return undefined;
|
|
206
|
-
|
|
740
|
+
}
|
|
741
|
+
const transfers = legacyReg16ByteTransferOpcodes(target.register, source.register);
|
|
742
|
+
if (!transfers) {
|
|
207
743
|
return undefined;
|
|
208
|
-
|
|
209
|
-
|
|
210
|
-
|
|
211
|
-
|
|
212
|
-
|
|
213
|
-
|
|
214
|
-
|
|
215
|
-
if (
|
|
216
|
-
|
|
217
|
-
|
|
218
|
-
|
|
744
|
+
}
|
|
745
|
+
return {
|
|
746
|
+
size: transfers.length,
|
|
747
|
+
fragments: [{ kind: 'bytes', bytes: transfers }],
|
|
748
|
+
};
|
|
749
|
+
}
|
|
750
|
+
function legacyReg16ByteTransferOpcodes(target, source) {
|
|
751
|
+
if (target === 'hl' && source === 'de') {
|
|
752
|
+
return [0x62, 0x6b];
|
|
753
|
+
}
|
|
754
|
+
if (target === 'bc' && source === 'de') {
|
|
755
|
+
return [0x42, 0x4b];
|
|
219
756
|
}
|
|
220
757
|
return undefined;
|
|
221
758
|
}
|
|
222
|
-
function
|
|
223
|
-
|
|
224
|
-
|
|
225
|
-
|
|
226
|
-
|
|
227
|
-
|
|
228
|
-
|
|
229
|
-
|
|
230
|
-
|
|
231
|
-
|
|
232
|
-
|
|
233
|
-
|
|
234
|
-
case 'PE':
|
|
235
|
-
return 0xea;
|
|
236
|
-
case 'P':
|
|
237
|
-
return 0xf2;
|
|
238
|
-
case 'M':
|
|
239
|
-
return 0xfa;
|
|
240
|
-
default:
|
|
241
|
-
return undefined;
|
|
759
|
+
function encodeSpecialRegisterLd(target, source) {
|
|
760
|
+
if (target.kind === 'special8' && source.kind === 'reg8' && source.register === 'a') {
|
|
761
|
+
return {
|
|
762
|
+
size: 2,
|
|
763
|
+
fragments: [{ kind: 'bytes', bytes: [0xed, target.register === 'i' ? 0x47 : 0x4f] }],
|
|
764
|
+
};
|
|
765
|
+
}
|
|
766
|
+
if (target.kind === 'reg8' && target.register === 'a' && source.kind === 'special8') {
|
|
767
|
+
return {
|
|
768
|
+
size: 2,
|
|
769
|
+
fragments: [{ kind: 'bytes', bytes: [0xed, source.register === 'i' ? 0x57 : 0x5f] }],
|
|
770
|
+
};
|
|
242
771
|
}
|
|
772
|
+
return undefined;
|
|
243
773
|
}
|
|
244
|
-
function
|
|
245
|
-
|
|
246
|
-
|
|
247
|
-
|
|
248
|
-
|
|
249
|
-
|
|
250
|
-
|
|
251
|
-
|
|
252
|
-
|
|
253
|
-
|
|
254
|
-
|
|
255
|
-
|
|
256
|
-
|
|
257
|
-
}
|
|
258
|
-
|
|
259
|
-
|
|
260
|
-
|
|
261
|
-
|
|
262
|
-
|
|
263
|
-
|
|
264
|
-
case '
|
|
265
|
-
return
|
|
266
|
-
case '
|
|
267
|
-
return
|
|
268
|
-
case '
|
|
269
|
-
return
|
|
270
|
-
case '
|
|
271
|
-
return
|
|
272
|
-
case 'P':
|
|
273
|
-
return 0xf4;
|
|
274
|
-
case 'M':
|
|
275
|
-
return 0xfc;
|
|
276
|
-
default:
|
|
277
|
-
return undefined;
|
|
774
|
+
function absoluteLd(opcode, expression) {
|
|
775
|
+
return {
|
|
776
|
+
size: 3,
|
|
777
|
+
fragments: [
|
|
778
|
+
{ kind: 'bytes', bytes: [opcode] },
|
|
779
|
+
{ kind: 'abs16', expression },
|
|
780
|
+
],
|
|
781
|
+
};
|
|
782
|
+
}
|
|
783
|
+
function prefixedAbsoluteLd(prefix, opcode, expression) {
|
|
784
|
+
return {
|
|
785
|
+
size: 4,
|
|
786
|
+
fragments: [
|
|
787
|
+
{ kind: 'bytes', bytes: [prefix, opcode] },
|
|
788
|
+
{ kind: 'abs16', expression },
|
|
789
|
+
],
|
|
790
|
+
};
|
|
791
|
+
}
|
|
792
|
+
function absoluteRegister16Load(register, expression) {
|
|
793
|
+
switch (register) {
|
|
794
|
+
case 'hl':
|
|
795
|
+
return absoluteLd(0x2a, expression);
|
|
796
|
+
case 'bc':
|
|
797
|
+
return prefixedAbsoluteLd(0xed, 0x4b, expression);
|
|
798
|
+
case 'de':
|
|
799
|
+
return prefixedAbsoluteLd(0xed, 0x5b, expression);
|
|
800
|
+
case 'sp':
|
|
801
|
+
return prefixedAbsoluteLd(0xed, 0x7b, expression);
|
|
278
802
|
}
|
|
279
803
|
}
|
|
280
|
-
function
|
|
281
|
-
switch (
|
|
282
|
-
case '
|
|
283
|
-
return
|
|
284
|
-
case '
|
|
285
|
-
return
|
|
286
|
-
case '
|
|
287
|
-
return
|
|
288
|
-
case '
|
|
289
|
-
return
|
|
290
|
-
|
|
291
|
-
|
|
292
|
-
|
|
293
|
-
|
|
294
|
-
|
|
295
|
-
|
|
296
|
-
|
|
297
|
-
|
|
804
|
+
function absoluteRegister16Store(register, expression) {
|
|
805
|
+
switch (register) {
|
|
806
|
+
case 'hl':
|
|
807
|
+
return absoluteLd(0x22, expression);
|
|
808
|
+
case 'bc':
|
|
809
|
+
return prefixedAbsoluteLd(0xed, 0x43, expression);
|
|
810
|
+
case 'de':
|
|
811
|
+
return prefixedAbsoluteLd(0xed, 0x53, expression);
|
|
812
|
+
case 'sp':
|
|
813
|
+
return prefixedAbsoluteLd(0xed, 0x73, expression);
|
|
814
|
+
}
|
|
815
|
+
}
|
|
816
|
+
function indexPrefix(register) {
|
|
817
|
+
return register === 'ix' ? 0xdd : 0xfd;
|
|
818
|
+
}
|
|
819
|
+
function loadSpOpcode(register) {
|
|
820
|
+
switch (register) {
|
|
821
|
+
case 'hl':
|
|
822
|
+
return [0xf9];
|
|
823
|
+
case 'ix':
|
|
824
|
+
return [0xdd, 0xf9];
|
|
825
|
+
case 'iy':
|
|
826
|
+
return [0xfd, 0xf9];
|
|
298
827
|
default:
|
|
299
|
-
|
|
300
|
-
}
|
|
301
|
-
}
|
|
302
|
-
function encodeFamilyInstruction(family, node, env, diagnostics) {
|
|
303
|
-
switch (family) {
|
|
304
|
-
case 'control':
|
|
305
|
-
return encodeControlInstruction(node, env, diagnostics, {
|
|
306
|
-
diag,
|
|
307
|
-
immValue,
|
|
308
|
-
registerTokenName,
|
|
309
|
-
conditionName,
|
|
310
|
-
symbolicImmBaseName,
|
|
311
|
-
fitsImm16,
|
|
312
|
-
isMemRegName,
|
|
313
|
-
retConditionOpcode,
|
|
314
|
-
callConditionOpcode,
|
|
315
|
-
jpConditionOpcode,
|
|
316
|
-
jrConditionOpcode,
|
|
317
|
-
});
|
|
318
|
-
case 'alu':
|
|
319
|
-
return encodeAluInstruction(node, env, diagnostics, {
|
|
320
|
-
diag,
|
|
321
|
-
regName,
|
|
322
|
-
immValue,
|
|
323
|
-
indexedReg8,
|
|
324
|
-
reg8Code,
|
|
325
|
-
fitsImm8,
|
|
326
|
-
isMemHL,
|
|
327
|
-
memIndexed: (op, env) => memIndexed(op, env, diagnostics),
|
|
328
|
-
});
|
|
329
|
-
case 'io':
|
|
330
|
-
return encodeIoInstruction(node, env, diagnostics, {
|
|
331
|
-
diag,
|
|
332
|
-
regName,
|
|
333
|
-
immValue,
|
|
334
|
-
portImmValue,
|
|
335
|
-
indexedReg8,
|
|
336
|
-
reg8Code,
|
|
337
|
-
fitsImm8,
|
|
338
|
-
});
|
|
339
|
-
case 'ld':
|
|
340
|
-
return encodeLdInstruction(node, env, diagnostics, {
|
|
341
|
-
diag,
|
|
342
|
-
regName,
|
|
343
|
-
immValue,
|
|
344
|
-
indexedReg8,
|
|
345
|
-
reg8Code,
|
|
346
|
-
fitsImm8,
|
|
347
|
-
fitsImm16,
|
|
348
|
-
memAbs16,
|
|
349
|
-
memIndexed: (op, env) => memIndexed(op, env, diagnostics),
|
|
350
|
-
isMemHL,
|
|
351
|
-
isMemRegName,
|
|
352
|
-
isReg16TransferName,
|
|
353
|
-
isPlainHLReg8,
|
|
354
|
-
});
|
|
355
|
-
case 'core':
|
|
356
|
-
return encodeCoreOpsInstruction(node, env, diagnostics, {
|
|
357
|
-
diag,
|
|
358
|
-
regName,
|
|
359
|
-
indexedReg8,
|
|
360
|
-
reg8Code,
|
|
361
|
-
isMemHL,
|
|
362
|
-
memIndexed: (op, env) => memIndexed(op, env, diagnostics),
|
|
363
|
-
});
|
|
364
|
-
case 'bit':
|
|
365
|
-
return encodeBitOpsInstruction(node, env, diagnostics, {
|
|
366
|
-
diag,
|
|
367
|
-
regName,
|
|
368
|
-
immValue,
|
|
369
|
-
indexedReg8,
|
|
370
|
-
reg8Code,
|
|
371
|
-
isMemHL,
|
|
372
|
-
memIndexed: (op, env) => memIndexed(op, env, diagnostics),
|
|
373
|
-
});
|
|
374
|
-
}
|
|
375
|
-
}
|
|
376
|
-
/**
|
|
377
|
-
* Encode a single `asm` instruction node into Z80 machine-code bytes.
|
|
378
|
-
*
|
|
379
|
-
* - Immediate operands may be `imm` expressions (const/enum names and operators), evaluated via the env.
|
|
380
|
-
* - Unsupported forms append an error diagnostic and return `undefined`.
|
|
381
|
-
*/
|
|
382
|
-
export function encodeInstruction(node, env, diagnostics) {
|
|
383
|
-
const diagnosticsBefore = diagnostics.length;
|
|
384
|
-
const head = node.head.toLowerCase();
|
|
385
|
-
const entry = getEncoderRegistryEntry(head);
|
|
386
|
-
if (!entry) {
|
|
387
|
-
diagEncodeAt(diagnostics, node.span, `Unsupported instruction: ${node.head}`);
|
|
388
|
-
return undefined;
|
|
828
|
+
throw new Error(`unsupported LD SP source register: ${register}`);
|
|
389
829
|
}
|
|
390
|
-
|
|
391
|
-
|
|
392
|
-
|
|
393
|
-
|
|
394
|
-
|
|
830
|
+
}
|
|
831
|
+
function halfIndexPrefix(target, source) {
|
|
832
|
+
const register = target.kind === 'reg-half-index'
|
|
833
|
+
? target.register
|
|
834
|
+
: source.kind === 'reg-half-index'
|
|
835
|
+
? source.register
|
|
836
|
+
: undefined;
|
|
837
|
+
if (!register) {
|
|
838
|
+
throw new Error('expected half-index register');
|
|
395
839
|
}
|
|
396
|
-
|
|
397
|
-
|
|
398
|
-
|
|
399
|
-
if (
|
|
400
|
-
return
|
|
401
|
-
|
|
402
|
-
|
|
403
|
-
|
|
404
|
-
|
|
405
|
-
|
|
406
|
-
|
|
407
|
-
|
|
840
|
+
return register.startsWith('ix') ? 0xdd : 0xfd;
|
|
841
|
+
}
|
|
842
|
+
function isEncodableHalfIndexLd(target, source) {
|
|
843
|
+
if (target.kind !== 'reg-half-index' && source.kind !== 'reg-half-index') {
|
|
844
|
+
return false;
|
|
845
|
+
}
|
|
846
|
+
return (isSameHalfIndexFamily(target, source) &&
|
|
847
|
+
isHalfIndexCompatibleByteOperand(target) &&
|
|
848
|
+
isHalfIndexCompatibleByteOperand(source));
|
|
849
|
+
}
|
|
850
|
+
function isSameHalfIndexFamily(target, source) {
|
|
851
|
+
const targetFamily = halfIndexFamily(target);
|
|
852
|
+
const sourceFamily = halfIndexFamily(source);
|
|
853
|
+
return !targetFamily || !sourceFamily || targetFamily === sourceFamily;
|
|
854
|
+
}
|
|
855
|
+
function halfIndexFamily(operand) {
|
|
856
|
+
if (operand.kind !== 'reg-half-index') {
|
|
408
857
|
return undefined;
|
|
409
858
|
}
|
|
410
|
-
|
|
411
|
-
|
|
859
|
+
return operand.register.startsWith('ix') ? 'ix' : 'iy';
|
|
860
|
+
}
|
|
861
|
+
function isHalfIndexCompatibleByteOperand(operand) {
|
|
862
|
+
return (operand.kind === 'reg-half-index' ||
|
|
863
|
+
(operand.kind === 'reg8' && operand.register !== 'h' && operand.register !== 'l'));
|
|
864
|
+
}
|
|
865
|
+
function byteRegisterCode(operand) {
|
|
866
|
+
return operand.kind === 'reg8'
|
|
867
|
+
? register8Code(operand.register)
|
|
868
|
+
: halfIndexRegisterCode(operand.register);
|
|
869
|
+
}
|
|
870
|
+
function halfIndexRegisterCode(register) {
|
|
871
|
+
switch (register) {
|
|
872
|
+
case 'ixh':
|
|
873
|
+
case 'iyh':
|
|
874
|
+
return 4;
|
|
875
|
+
case 'ixl':
|
|
876
|
+
case 'iyl':
|
|
877
|
+
return 5;
|
|
878
|
+
}
|
|
879
|
+
}
|
|
880
|
+
function register8Code(register) {
|
|
881
|
+
switch (register) {
|
|
882
|
+
case 'b':
|
|
883
|
+
return 0;
|
|
884
|
+
case 'c':
|
|
885
|
+
return 1;
|
|
886
|
+
case 'd':
|
|
887
|
+
return 2;
|
|
888
|
+
case 'e':
|
|
889
|
+
return 3;
|
|
890
|
+
case 'h':
|
|
891
|
+
return 4;
|
|
892
|
+
case 'l':
|
|
893
|
+
return 5;
|
|
894
|
+
case 'a':
|
|
895
|
+
return 7;
|
|
896
|
+
}
|
|
897
|
+
}
|
|
898
|
+
function register16Code(register) {
|
|
899
|
+
switch (register) {
|
|
900
|
+
case 'bc':
|
|
901
|
+
return 0;
|
|
902
|
+
case 'de':
|
|
903
|
+
return 1;
|
|
904
|
+
case 'hl':
|
|
905
|
+
return 2;
|
|
906
|
+
case 'sp':
|
|
907
|
+
return 3;
|
|
908
|
+
}
|
|
909
|
+
}
|
|
910
|
+
function loadAFromIndirectOpcode(register) {
|
|
911
|
+
switch (register) {
|
|
912
|
+
case 'bc':
|
|
913
|
+
return 0x0a;
|
|
914
|
+
case 'de':
|
|
915
|
+
return 0x1a;
|
|
916
|
+
case 'hl':
|
|
917
|
+
return 0x7e;
|
|
918
|
+
}
|
|
919
|
+
}
|
|
920
|
+
function storeAToIndirectOpcode(register) {
|
|
921
|
+
switch (register) {
|
|
922
|
+
case 'bc':
|
|
923
|
+
return 0x02;
|
|
924
|
+
case 'de':
|
|
925
|
+
return 0x12;
|
|
926
|
+
case 'hl':
|
|
927
|
+
return 0x77;
|
|
928
|
+
}
|
|
929
|
+
}
|
|
930
|
+
function absoluteTarget(opcode, expression) {
|
|
931
|
+
return {
|
|
932
|
+
size: 3,
|
|
933
|
+
fragments: [
|
|
934
|
+
{ kind: 'bytes', bytes: [opcode] },
|
|
935
|
+
{ kind: 'abs16', expression },
|
|
936
|
+
],
|
|
937
|
+
};
|
|
938
|
+
}
|
|
939
|
+
function jumpIndirect(register) {
|
|
940
|
+
switch (register) {
|
|
941
|
+
case 'hl':
|
|
942
|
+
return { size: 1, fragments: [{ kind: 'bytes', bytes: [0xe9] }] };
|
|
943
|
+
case 'ix':
|
|
944
|
+
return { size: 2, fragments: [{ kind: 'bytes', bytes: [0xdd, 0xe9] }] };
|
|
945
|
+
case 'iy':
|
|
946
|
+
return { size: 2, fragments: [{ kind: 'bytes', bytes: [0xfd, 0xe9] }] };
|
|
947
|
+
}
|
|
948
|
+
}
|
|
949
|
+
function relativeTarget(opcode, mnemonic, expression) {
|
|
950
|
+
return {
|
|
951
|
+
size: 2,
|
|
952
|
+
fragments: [
|
|
953
|
+
{ kind: 'bytes', bytes: [opcode] },
|
|
954
|
+
{ kind: 'rel8', expression, mnemonic },
|
|
955
|
+
],
|
|
956
|
+
};
|
|
957
|
+
}
|
|
958
|
+
function conditionCode(condition) {
|
|
959
|
+
switch (condition) {
|
|
960
|
+
case 'nz':
|
|
961
|
+
return 0;
|
|
962
|
+
case 'z':
|
|
963
|
+
return 1;
|
|
964
|
+
case 'nc':
|
|
965
|
+
return 2;
|
|
966
|
+
case 'c':
|
|
967
|
+
return 3;
|
|
968
|
+
case 'po':
|
|
969
|
+
return 4;
|
|
970
|
+
case 'pe':
|
|
971
|
+
return 5;
|
|
972
|
+
case 'p':
|
|
973
|
+
return 6;
|
|
974
|
+
case 'm':
|
|
975
|
+
return 7;
|
|
976
|
+
}
|
|
977
|
+
}
|
|
978
|
+
function retConditionOpcode(condition) {
|
|
979
|
+
return 0xc0 + conditionCode(condition) * 8;
|
|
980
|
+
}
|
|
981
|
+
function jpConditionOpcode(condition) {
|
|
982
|
+
return 0xc2 + conditionCode(condition) * 8;
|
|
983
|
+
}
|
|
984
|
+
function callConditionOpcode(condition) {
|
|
985
|
+
return 0xc4 + conditionCode(condition) * 8;
|
|
986
|
+
}
|
|
987
|
+
function jrConditionOpcode(condition) {
|
|
988
|
+
return 0x20 + conditionCode(condition) * 8;
|
|
412
989
|
}
|