@fjader/svelte 0.2.1 → 0.2.2

package/dist/components/rendering/Areas.svelte

@@ -3,6 +3,7 @@
 	import { RendererHost } from './RendererHost.svelte';
 	import { getGPUContext } from '../../gpu';
 	import { getCurveWGSL, getCurveResolution } from '../../gpu/CurveShaderLib';
+	import { NAN_WGSL } from '../../gpu/NanShaderLib';
 	import { DEFAULT_FILL_COLOR } from '../../scales/color-utils';
 	import type { ChartContext, WebGPUCanvasContext, CurveType } from '../../types';
 
@@ -159,9 +160,7 @@
   @group(1) @binding(4) var<storage, read> colorValues: array<f32>;
   {{FACET_BINDING}}
 
-  fn isNaN(v: f32) -> bool {
-    return v != v;
-  }
+  ${NAN_WGSL}
 
   // Map (dimension, boundary) to (x, y) based on orientation
   fn makePoint(dimVal: f32, boundaryVal: f32) -> vec2<f32> {

package/dist/components/rendering/Lines.svelte

@@ -3,6 +3,7 @@
 	import { RendererHost } from './RendererHost.svelte';
 	import { getGPUContext } from '../../gpu';
 	import { getCurveWGSL, getCurveResolution } from '../../gpu/CurveShaderLib';
+	import { NAN_WGSL } from '../../gpu/NanShaderLib';
 	import { DEFAULT_STROKE_COLOR } from '../../scales/color-utils';
 	import type { ChartContext, WebGPUCanvasContext, CurveType } from '../../types';
 	import type { M4Decimator } from '../../gpu/decimation/M4Decimator.svelte';
@@ -156,9 +157,7 @@
   @group(1) @binding(3) var<storage, read> colorValues: array<f32>;
   {{FACET_BINDING}}
 
-  fn isNaN(v: f32) -> bool {
-    return v != v;
-  }
+  ${NAN_WGSL}
 
   const DISCARD_POS = vec4<f32>(2.0, 2.0, 2.0, 1.0);
 

package/dist/components/rendering/ParallelLines.svelte

@@ -3,6 +3,7 @@
 	import { RendererHost } from './RendererHost.svelte';
 	import { getGPUContext } from '../../gpu';
 	import { getCurveWGSL, getCurveResolution } from '../../gpu/CurveShaderLib';
+	import { NAN_WGSL } from '../../gpu/NanShaderLib';
 	import { DEFAULT_STROKE_COLOR } from '../../scales/color-utils';
 	import type { ChartContext, CurveType, WebGPUCanvasContext } from '../../types';
 
@@ -123,7 +124,7 @@
   // writes; only linear math is applied to them today.
   @group(1) @binding(3) var<uniform> axisScales: array<ScaleParam, ${MAX_AXES}>;
 
-  fn isNaN(v: f32) -> bool { return v != v; }
+  ${NAN_WGSL}
   const DISCARD_POS = vec4<f32>(2.0, 2.0, 2.0, 1.0);
 
   fn getAxisOrder(visualIdx: u32) -> u32 {

package/dist/data/DataAccessor.js

@@ -29,7 +29,7 @@ export class ArrowDataAccessor {
         // FAST PATH: Single chunk numeric - try to return underlying buffer directly.
         // NULL handling: Query-level COALESCE(CAST(expr AS REAL), 'NaN'::REAL)
         // converts SQL NULLs to the NaN float value, so Arrow columns from Fjader
-        // queries have nullCount=0 and clean buffers. GPU shaders detect NaN (v != v)
+        // queries have nullCount=0 and clean buffers. GPU shaders detect NaN by its bit pattern (NanShaderLib)
         // and discard those vertices to create gaps in lines/areas.
         if (!isStringType && col.data.length === 1) {
             const chunk = col.data[0];

package/dist/gpu/ColorScaleShaderLib.d.ts

@@ -17,4 +17,4 @@ export declare const COLOR_CONFIG_SLOT_BASE_OFFSET = 32;
 export declare const NO_SLOT_TABLE = 4294967295;
 export declare const COLOR_SCALE_STRUCTS = "\nstruct ColorConfig {\n    domainMin: f32,         // byte 0  \u2014 pre-transformed for non-linear types\n    domainMax: f32,         // byte 4  \u2014 pre-transformed for non-linear types\n    rampOffset: u32,        // byte 8\n    paletteOffset: u32,     // byte 12\n    paletteSize: u32,       // byte 16\n    scaleType: u32,         // byte 20 \u2014 scheme rendering type (ordinal/sequential/diverging/cyclical)\n    transformType: u32,     // byte 24 \u2014 normalization transform (linear/log/symlog/sqrt/pow)\n    transformParam: f32,    // byte 28 \u2014 symlog constant C, or pow exponent\n    slotBase: u32,          // byte 32 \u2014 base into identitySlots, or NO_SLOT_TABLE\n    _pad0: u32,             // byte 36\n    _pad1: u32,             // byte 40\n    _pad2: u32,             // byte 44\n}\n\n/**\n * slotBase when this scale's channel already carries a palette index rather\n * than an identity id. Distinct from base 0, which is a real block \u2014 the\n * permanently empty one \u2014 so it cannot be confused with \"not placed\".\n */\nconst NO_SLOT_TABLE: u32 = 0xFFFFFFFFu;\n\nconst COLOR_SCALE_ORDINAL: u32 = 0u;\nconst COLOR_SCALE_SEQUENTIAL: u32 = 1u;\nconst COLOR_SCALE_DIVERGING: u32 = 2u;\nconst COLOR_SCALE_CYCLICAL: u32 = 3u;\n\nconst COLOR_TRANSFORM_LINEAR: u32 = 0u;\nconst COLOR_TRANSFORM_LOG: u32 = 1u;\nconst COLOR_TRANSFORM_SYMLOG: u32 = 2u;\nconst COLOR_TRANSFORM_SQRT: u32 = 3u;\nconst COLOR_TRANSFORM_POW: u32 = 4u;\n";
 export declare const COLOR_SCALE_BINDINGS = "\n@group(2) @binding(1) var<storage, read> colorConfigs: array<ColorConfig>;\n@group(2) @binding(2) var<storage, read> colorRamps: array<vec4<f32>>;\n@group(2) @binding(3) var<storage, read> ordinalPalettes: array<vec4<f32>>;\n";
-export declare const COLOR_SCALE_FUNCTIONS = "\nfn applyColorTransform(config: ColorConfig, value: f32) -> f32 {\n    switch config.transformType {\n        case COLOR_TRANSFORM_LOG: {\n            return log(max(value, 1e-38));\n        }\n        case COLOR_TRANSFORM_SYMLOG: {\n            let c = config.transformParam;\n            return sign(value) * log(1.0 + abs(value / c));\n        }\n        case COLOR_TRANSFORM_SQRT: {\n            return sign(value) * sqrt(abs(value));\n        }\n        case COLOR_TRANSFORM_POW: {\n            return sign(value) * pow(abs(value), config.transformParam);\n        }\n        default: {\n            return value;\n        }\n    }\n}\n\nfn normalizeValue(config: ColorConfig, value: f32) -> f32 {\n    let transformed = applyColorTransform(config, value);\n\n    let range = config.domainMax - config.domainMin;\n\n    if (abs(range) < 0.0001) {\n        return 0.5;\n    }\n\n    let t_raw = (transformed - config.domainMin) / range;\n\n    if (config.scaleType == COLOR_SCALE_CYCLICAL) {\n        return fract(t_raw);\n    }\n\n    return clamp(t_raw, 0.0, 1.0);\n}\n\nfn sampleRamp(config: ColorConfig, t: f32) -> vec4<f32> {\n    let idx = min(u32(t * 255.0), 255u); // Must match COLOR_RAMP_RESOLUTION (256 stops)\n    return colorRamps[config.rampOffset + idx];\n}\n\nfn samplePalette(config: ColorConfig, categoryIndex: u32) -> vec4<f32> {\n    // The channel carries an identity id, which is stable and has nothing to do\n    // with this scale's palette. Resolve it to this scale's own rank first; the\n    // palette is indexed by rank, so the plotted categories take palette colours\n    // in order and the wrap below is over the PLOTTED count, not the dim's.\n    var idx = categoryIndex;\n    if (config.slotBase != NO_SLOT_TABLE) {\n        let slot = identitySlot(config.slotBase, categoryIndex);\n        if (slot < 0.0) {\n            // Not ranked by this scale: a category outside its domain.\n            return vec4<f32>(0.0, 0.0, 0.0, 0.0);\n        }\n        idx = u32(slot);\n    }\n    return ordinalPalettes[config.paletteOffset + (idx % config.paletteSize)];\n}\n\nfn getColorFromScale(scaleIndex: u32, value: f32, nullColor: vec4<f32>) -> vec4<f32> {\n    let config = colorConfigs[scaleIndex];\n\n    if (config.scaleType == COLOR_SCALE_ORDINAL) {\n        // 0-based indexing: -1 = null, 0+ = valid categories\n        if (value < 0.0) {\n            return nullColor;\n        }\n        let catIdx = u32(value);\n        return samplePalette(config, catIdx);\n    }\n\n    if (value != value) {\n        return nullColor;\n    }\n\n    // Log requires strictly positive values \u2014 treat \u22640 as unmappable\n    if (config.transformType == COLOR_TRANSFORM_LOG && value <= 0.0) {\n        return nullColor;\n    }\n\n    let t = normalizeValue(config, value);\n    return sampleRamp(config, t);\n}\n\nfn getOrdinalColor(scaleIndex: u32, categoryIndex: u32, nullColor: vec4<f32>) -> vec4<f32> {\n    // Note: This function expects u32, so caller must handle -1 check before casting\n    let config = colorConfigs[scaleIndex];\n    return samplePalette(config, categoryIndex);\n}\n\nfn getContinuousColor(scaleIndex: u32, value: f32, nullColor: vec4<f32>) -> vec4<f32> {\n    if (value != value) {\n        return nullColor;\n    }\n    let config = colorConfigs[scaleIndex];\n    if (config.transformType == COLOR_TRANSFORM_LOG && value <= 0.0) {\n        return nullColor;\n    }\n    let t = normalizeValue(config, value);\n    return sampleRamp(config, t);\n}\n";
+export declare const COLOR_SCALE_FUNCTIONS: string;

package/dist/gpu/ColorScaleShaderLib.js

@@ -1,3 +1,4 @@
+import { isNanExpr } from './NanShaderLib';
 // src/lib/gpu/ColorScaleShaderLib.ts
 // ---------------------------------------------------------------------------
 // Design note: branching vs JIT-compiled shaders for color normalization
@@ -148,7 +149,7 @@ fn getColorFromScale(scaleIndex: u32, value: f32, nullColor: vec4<f32>) -> vec4<
         return samplePalette(config, catIdx);
     }
 
-    if (value != value) {
+    if (${isNanExpr('value')}) {
         return nullColor;
     }
 
@@ -168,7 +169,7 @@ fn getOrdinalColor(scaleIndex: u32, categoryIndex: u32, nullColor: vec4<f32>) ->
 }
 
 fn getContinuousColor(scaleIndex: u32, value: f32, nullColor: vec4<f32>) -> vec4<f32> {
-    if (value != value) {
+    if (${isNanExpr('value')}) {
         return nullColor;
     }
     let config = colorConfigs[scaleIndex];

package/dist/gpu/NanShaderLib.d.ts

@@ -0,0 +1,30 @@
+/**
+ * NaN tests for WGSL that a shader compiler cannot remove.
+ *
+ * fjader sends nulls to the GPU as NaN. WGSL lets an implementation assume
+ * floats are finite, and Apple's Metal compilers act on that: `v != v` and
+ * `!(v == v)` can compile to `false`, so a NaN goes undetected. Whether that
+ * happens depends on the GPU generation and on the code around the test, so a
+ * check that works on one Mac can be gone on another. /test/nan-probe shows
+ * what a given GPU does.
+ *
+ * These test the bit pattern instead: an exponent of all ones and a non-zero
+ * mantissa. That is integer arithmetic, which no float assumption touches.
+ *
+ * `NAN_BITS` is the quiet NaN written wherever a shader needs to produce one.
+ * Writing it as bits into a u32 view of the buffer keeps it exact; producing
+ * a NaN through float arithmetic is not guaranteed to.
+ */
+/** The quiet NaN fjader writes, as bits. */
+export declare const NAN_BITS_HEX = "0x7FC00000u";
+/**
+ * `isNanBits(u)` for a value read through a u32 view, and `isNaN(v)` for one
+ * already loaded as f32. Prefer the u32 view where a shader can read the
+ * buffer that way: it never loads the NaN as a float at all.
+ */
+export declare const NAN_WGSL = "\nconst NAN_BITS: u32 = 0x7FC00000u;\n\nfn isNanBits(u: u32) -> bool {\n\treturn (u & 0x7fffffffu) > 0x7f800000u;\n}\n\nfn isNaN(v: f32) -> bool {\n\treturn isNanBits(bitcast<u32>(v));\n}\n";
+/**
+ * The same test as an expression, for shader libraries that are pasted into
+ * other shaders and so cannot define functions those shaders may define too.
+ */
+export declare function isNanExpr(f32Expr: string): string;

package/dist/gpu/NanShaderLib.js

@@ -0,0 +1,42 @@
+/**
+ * NaN tests for WGSL that a shader compiler cannot remove.
+ *
+ * fjader sends nulls to the GPU as NaN. WGSL lets an implementation assume
+ * floats are finite, and Apple's Metal compilers act on that: `v != v` and
+ * `!(v == v)` can compile to `false`, so a NaN goes undetected. Whether that
+ * happens depends on the GPU generation and on the code around the test, so a
+ * check that works on one Mac can be gone on another. /test/nan-probe shows
+ * what a given GPU does.
+ *
+ * These test the bit pattern instead: an exponent of all ones and a non-zero
+ * mantissa. That is integer arithmetic, which no float assumption touches.
+ *
+ * `NAN_BITS` is the quiet NaN written wherever a shader needs to produce one.
+ * Writing it as bits into a u32 view of the buffer keeps it exact; producing
+ * a NaN through float arithmetic is not guaranteed to.
+ */
+/** The quiet NaN fjader writes, as bits. */
+export const NAN_BITS_HEX = '0x7FC00000u';
+/**
+ * `isNanBits(u)` for a value read through a u32 view, and `isNaN(v)` for one
+ * already loaded as f32. Prefer the u32 view where a shader can read the
+ * buffer that way: it never loads the NaN as a float at all.
+ */
+export const NAN_WGSL = /* wgsl */ `
+const NAN_BITS: u32 = ${NAN_BITS_HEX};
+
+fn isNanBits(u: u32) -> bool {
+	return (u & 0x7fffffffu) > 0x7f800000u;
+}
+
+fn isNaN(v: f32) -> bool {
+	return isNanBits(bitcast<u32>(v));
+}
+`;
+/**
+ * The same test as an expression, for shader libraries that are pasted into
+ * other shaders and so cannot define functions those shaders may define too.
+ */
+export function isNanExpr(f32Expr) {
+    return `((bitcast<u32>(${f32Expr}) & 0x7fffffffu) > 0x7f800000u)`;
+}

package/dist/gpu/ResolveShader.d.ts

@@ -69,7 +69,7 @@ export declare const RESOLVE_IMMEDIATE_SIZE = 12;
  * hand every dispatch the last one's values. Immediates are pass state, set in
  * command order, so each dispatch reads its own.
  */
-export declare const RESOLVE_SHADER = "\nrequires immediate_address_space;\n\nstruct Params {\n  // Elements in this range. The rest of the buffer is left alone.\n  count: u32,\n  // 0 -> from, 1 -> to. Shared by every element of the range.\n  t: f32,\n  // Where the range starts, in all three buffers alike.\n  offset: u32,\n};\n\n@group(0) @binding(0) var<storage, read>       valueFrom: array<f32>;\n@group(0) @binding(1) var<storage, read>       valueTo:   array<f32>;\n@group(0) @binding(2) var<storage, read_write> resolved:  array<f32>;\nvar<immediate> params: Params;\n\n@compute @workgroup_size(64)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n  if (gid.x >= params.count) {\n    return;\n  }\n  let j = params.offset + gid.x;\n  let a = valueFrom[j];\n  let b = valueTo[j];\n  // A NaN on either side means one end of this transition is not a number, so\n  // there is nothing to interpolate along. Take the destination and be done.\n  // Note the test has to be explicit: every comparison against NaN is false, so\n  // mix() would silently propagate it instead.\n  // Equal ends take b too, so they come out exact on any driver \u2014 see above.\n  let takeTo = a == b || a != a || b != b;\n  resolved[j] = select(mix(a, b, params.t), b, takeTo);\n}\n";
+export declare const RESOLVE_SHADER: string;
 /**
  * The same expression in JS, and the reason it exists.
  *

package/dist/gpu/ResolveShader.js

@@ -1,3 +1,4 @@
+import { isNanExpr } from './NanShaderLib';
 /**
  * The resolve kernel: `resolved[j] = mix(from[j], to[j], t)` over one range.
  *
@@ -96,10 +97,10 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
   let b = valueTo[j];
   // A NaN on either side means one end of this transition is not a number, so
   // there is nothing to interpolate along. Take the destination and be done.
-  // Note the test has to be explicit: every comparison against NaN is false, so
-  // mix() would silently propagate it instead.
+  // Note the test has to be explicit, and on the bits: mix() would silently
+  // propagate a NaN, and a compiler may fold a float test like a != a to false.
   // Equal ends take b too, so they come out exact on any driver — see above.
-  let takeTo = a == b || a != a || b != b;
+  let takeTo = a == b || ${isNanExpr('a')} || ${isNanExpr('b')};
   resolved[j] = select(mix(a, b, params.t), b, takeTo);
 }
 `;

package/dist/gpu/SizeScaleShaderLib.d.ts

@@ -28,4 +28,4 @@ export declare const MAX_SIZE_SLOTS = 64;
  * in WGSL, and the shared slot table already relies on the same thing.
  */
 export declare const SIZE_SCALE_BINDINGS = "\n@group(2) @binding(4) var<uniform> sizeConfigs: array<SizeConfig, 64>;\n";
-export declare const SIZE_SCALE_FUNCTIONS = "\nfn getSizeFromScale(scaleIndex: u32, value: f32) -> f32 {\n    let config = sizeConfigs[scaleIndex];\n\n    // Handle NaN \u2192 rangeMin\n    if (value != value) {\n        return config.rangeMin;\n    }\n\n    let range = config.domainMax - config.domainMin;\n\n    // Degenerate domain \u2192 midpoint of range\n    if (abs(range) < 0.0001) {\n        return (config.rangeMin + config.rangeMax) * 0.5;\n    }\n\n    // Normalize to [0, 1]\n    let t = clamp((value - config.domainMin) / range, 0.0, 1.0);\n\n    // Sqrt for area-proportional scaling\n    let s = sqrt(t);\n\n    // Interpolate to pixel range\n    return config.rangeMin + s * (config.rangeMax - config.rangeMin);\n}\n";
+export declare const SIZE_SCALE_FUNCTIONS: string;

package/dist/gpu/SizeScaleShaderLib.js

@@ -1,3 +1,4 @@
+import { isNanExpr } from './NanShaderLib';
 // src/lib/gpu/SizeScaleShaderLib.js
 export const SIZE_SCALE_STRUCTS = /* wgsl */ `
 struct SizeConfig {
@@ -43,7 +44,7 @@ fn getSizeFromScale(scaleIndex: u32, value: f32) -> f32 {
     let config = sizeConfigs[scaleIndex];
 
     // Handle NaN → rangeMin
-    if (value != value) {
+    if (${isNanExpr('value')}) {
         return config.rangeMin;
     }
 

package/dist/gpu/decimation/M4Shader.d.ts

@@ -27,6 +27,12 @@
  *
  * The x scale's params reach passes 1 and 2 as immediates, pushed before each
  * dispatch, rather than as an index into the global scale table.
+ *
+ * Every pass reads and writes the data through u32 views. NaN (a null, or an
+ * empty bin) is found by its bit pattern and moved as bits, never compared as
+ * a float: Metal compilers may fold `x != x` to false (see NanShaderLib), and
+ * where they do, compaction keeps the empty bins and the line loses every
+ * segment that touches one.
  */
 declare const WORKGROUP_SIZE = 256;
 /** Bytes of immediate data passes 1 and 2 read: one ScaleParam. */
@@ -44,7 +50,7 @@ declare const X_SCALE_IMMEDIATE_SIZE = 16;
  * Group 0: inputLayout (data dummies + config + bins)
  * Group 1: controlLayout (control)
  */
-declare const INIT_BINS_SHADER = "\n\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\nstruct M4Bin {\n\tfirstIdx: atomic<u32>,\n\tlastIdx: atomic<u32>,\n\tminYSortable: atomic<u32>,\n\tmaxYSortable: atomic<u32>,\n\tminYIdx: atomic<u32>,\n\tmaxYIdx: atomic<u32>,\n};\n\nfn floatToSortableUint(f: f32) -> u32 {\n\tlet bits = bitcast<u32>(f);\n\treturn select(~bits, bits ^ 0x80000000u, (bits & 0x80000000u) == 0u);\n}\n\n\n@group(0) @binding(4) var<uniform> config: M4Config;\n@group(0) @binding(5) var<storage, read_write> bins: array<M4Bin>;\n@group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\tlet binKey = gid.x;\n\tlet totalBins = config.numSeries * config.numBins;\n\n\t// Thread 0: read JS decision, set instance count\n\tif (binKey == 0u) {\n\t\tlet outputSize = config.numBins * config.numSeries * 4u;\n\t\t// JS sets _pad: 1 = decimate, 2 = passthrough\n\t\tlet shouldDec = config.decimationMode == 1u;\n\t\tatomicStore(&control[4], select(0u, 1u, shouldDec));\n\t\tatomicStore(&control[1], select(0u, outputSize, shouldDec));\n\t}\n\n\t// Always init bins \u2014 cheap and ensures clean state for potential decimation.\n\tif (binKey >= totalBins) { return; }\n\n\tatomicStore(&bins[binKey].firstIdx, 0xFFFFFFFFu);\n\tatomicStore(&bins[binKey].lastIdx, 0u);\n\tatomicStore(&bins[binKey].minYSortable, 0xFFFFFFFFu);\n\tatomicStore(&bins[binKey].maxYSortable, 0u);\n\tatomicStore(&bins[binKey].minYIdx, 0xFFFFFFFFu);\n\tatomicStore(&bins[binKey].maxYIdx, 0xFFFFFFFFu);\n}\n";
+declare const INIT_BINS_SHADER = "\n\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\nstruct M4Bin {\n\tfirstIdx: atomic<u32>,\n\tlastIdx: atomic<u32>,\n\tminYSortable: atomic<u32>,\n\tmaxYSortable: atomic<u32>,\n\tminYIdx: atomic<u32>,\n\tmaxYIdx: atomic<u32>,\n};\n\nfn sortableFromBits(bits: u32) -> u32 {\n\treturn select(~bits, bits ^ 0x80000000u, (bits & 0x80000000u) == 0u);\n}\n\n\nconst NAN_BITS: u32 = 0x7FC00000u;\n\nfn isNanBits(u: u32) -> bool {\n\treturn (u & 0x7fffffffu) > 0x7f800000u;\n}\n\nfn isNaN(v: f32) -> bool {\n\treturn isNanBits(bitcast<u32>(v));\n}\n\n\n\n@group(0) @binding(4) var<uniform> config: M4Config;\n@group(0) @binding(5) var<storage, read_write> bins: array<M4Bin>;\n@group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\tlet binKey = gid.x;\n\tlet totalBins = config.numSeries * config.numBins;\n\n\t// Thread 0: read JS decision, set instance count\n\tif (binKey == 0u) {\n\t\tlet outputSize = config.numBins * config.numSeries * 4u;\n\t\t// JS sets _pad: 1 = decimate, 2 = passthrough\n\t\tlet shouldDec = config.decimationMode == 1u;\n\t\tatomicStore(&control[4], select(0u, 1u, shouldDec));\n\t\tatomicStore(&control[1], select(0u, outputSize, shouldDec));\n\t}\n\n\t// Always init bins \u2014 cheap and ensures clean state for potential decimation.\n\tif (binKey >= totalBins) { return; }\n\n\tatomicStore(&bins[binKey].firstIdx, 0xFFFFFFFFu);\n\tatomicStore(&bins[binKey].lastIdx, 0u);\n\tatomicStore(&bins[binKey].minYSortable, 0xFFFFFFFFu);\n\tatomicStore(&bins[binKey].maxYSortable, 0u);\n\tatomicStore(&bins[binKey].minYIdx, 0xFFFFFFFFu);\n\tatomicStore(&bins[binKey].maxYIdx, 0xFFFFFFFFu);\n}\n";
 /**
  * Pass 1: Bin each point by scaled x position.
  *
@@ -55,7 +61,7 @@ declare const INIT_BINS_SHADER = "\n\nstruct M4Config {\n\tpointCount: u32,\n\tn
  * Group 1: controlLayout (control)
  * Immediates: the x scale (ScaleParam)
  */
-declare const BIN_POINTS_SHADER = "\nrequires immediate_address_space;\n\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\nstruct M4Bin {\n\tfirstIdx: atomic<u32>,\n\tlastIdx: atomic<u32>,\n\tminYSortable: atomic<u32>,\n\tmaxYSortable: atomic<u32>,\n\tminYIdx: atomic<u32>,\n\tmaxYIdx: atomic<u32>,\n};\n\nfn floatToSortableUint(f: f32) -> u32 {\n\tlet bits = bitcast<u32>(f);\n\treturn select(~bits, bits ^ 0x80000000u, (bits & 0x80000000u) == 0u);\n}\n\n\nstruct ScaleParam {\n\tp1: f32,\n\tp2: f32,\n\tp3: f32,\n\tp4: f32,\n};\n\nvar<immediate> xScale: ScaleParam;\n\n\n@group(0) @binding(0) var<storage, read> xValues: array<f32>;\n@group(0) @binding(1) var<storage, read> yValues: array<f32>;\n@group(0) @binding(2) var<storage, read> seriesValues: array<f32>;\n@group(0) @binding(4) var<uniform> config: M4Config;\n@group(0) @binding(5) var<storage, read_write> bins: array<M4Bin>;\n@group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\t// Only bin if decimating\n\tif (atomicLoad(&control[4]) == 0u) { return; }\n\n\tlet idx = gid.x;\n\tif (idx >= config.pointCount) { return; }\n\n\tlet x = xValues[idx];\n\tlet y = yValues[idx];\n\n\t// Skip NaN points\n\tif (x != x || y != y) { return; }\n\n\tlet domainMin = xScale.p1;\n\tlet domainMax = xScale.p2;\n\n\tlet t = (x - domainMin) / (domainMax - domainMin);\n\n\t// Series: 0-indexed from ViewManager (-1 = null/unknown, 0+ = categories)\n\tlet seriesF = seriesValues[idx];\n\tif (seriesF < 0.0 || seriesF != seriesF) { return; }\n\tlet series = u32(seriesF);\n\tif (series >= config.numSeries) { return; }\n\n\t// Bin assignment: boundary bins capture off-screen points for line connectivity.\n\t// Bins 0 and numBins-1 are boundary bins; bins 1..numBins-2 map to viewport pixels.\n\tvar bin: u32;\n\tif (t < 0.0) {\n\t\tbin = 0u;\n\t} else if (t > 1.0) {\n\t\tbin = config.numBins - 1u;\n\t} else {\n\t\tlet innerBins = config.numBins - 2u;\n\t\tbin = 1u + min(u32(floor(t * f32(innerBins))), innerBins - 1u);\n\t}\n\tlet binKey = series * config.numBins + bin;\n\n\tatomicMin(&bins[binKey].firstIdx, idx);\n\tatomicMax(&bins[binKey].lastIdx, idx);\n\n\tlet ySortable = floatToSortableUint(y);\n\tatomicMin(&bins[binKey].minYSortable, ySortable);\n\tatomicMax(&bins[binKey].maxYSortable, ySortable);\n}\n";
+declare const BIN_POINTS_SHADER = "\nrequires immediate_address_space;\n\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\nstruct M4Bin {\n\tfirstIdx: atomic<u32>,\n\tlastIdx: atomic<u32>,\n\tminYSortable: atomic<u32>,\n\tmaxYSortable: atomic<u32>,\n\tminYIdx: atomic<u32>,\n\tmaxYIdx: atomic<u32>,\n};\n\nfn sortableFromBits(bits: u32) -> u32 {\n\treturn select(~bits, bits ^ 0x80000000u, (bits & 0x80000000u) == 0u);\n}\n\n\nconst NAN_BITS: u32 = 0x7FC00000u;\n\nfn isNanBits(u: u32) -> bool {\n\treturn (u & 0x7fffffffu) > 0x7f800000u;\n}\n\nfn isNaN(v: f32) -> bool {\n\treturn isNanBits(bitcast<u32>(v));\n}\n\n\n\nstruct ScaleParam {\n\tp1: f32,\n\tp2: f32,\n\tp3: f32,\n\tp4: f32,\n};\n\nvar<immediate> xScale: ScaleParam;\n\n\n@group(0) @binding(0) var<storage, read> xBits: array<u32>;\n@group(0) @binding(1) var<storage, read> yBits: array<u32>;\n@group(0) @binding(2) var<storage, read> seriesBits: array<u32>;\n@group(0) @binding(4) var<uniform> config: M4Config;\n@group(0) @binding(5) var<storage, read_write> bins: array<M4Bin>;\n@group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\t// Only bin if decimating\n\tif (atomicLoad(&control[4]) == 0u) { return; }\n\n\tlet idx = gid.x;\n\tif (idx >= config.pointCount) { return; }\n\n\t// Skip NaN points, tested on the bits before either becomes a float\n\tlet xb = xBits[idx];\n\tlet yb = yBits[idx];\n\tif (isNanBits(xb) || isNanBits(yb)) { return; }\n\tlet x = bitcast<f32>(xb);\n\n\tlet domainMin = xScale.p1;\n\tlet domainMax = xScale.p2;\n\n\tlet t = (x - domainMin) / (domainMax - domainMin);\n\n\t// Series: 0-indexed from ViewManager (-1 = null/unknown, 0+ = categories)\n\tlet seriesB = seriesBits[idx];\n\tif (isNanBits(seriesB)) { return; }\n\tlet seriesF = bitcast<f32>(seriesB);\n\tif (seriesF < 0.0) { return; }\n\tlet series = u32(seriesF);\n\tif (series >= config.numSeries) { return; }\n\n\t// Bin assignment: boundary bins capture off-screen points for line connectivity.\n\t// Bins 0 and numBins-1 are boundary bins; bins 1..numBins-2 map to viewport pixels.\n\tvar bin: u32;\n\tif (t < 0.0) {\n\t\tbin = 0u;\n\t} else if (t > 1.0) {\n\t\tbin = config.numBins - 1u;\n\t} else {\n\t\tlet innerBins = config.numBins - 2u;\n\t\tbin = 1u + min(u32(floor(t * f32(innerBins))), innerBins - 1u);\n\t}\n\tlet binKey = series * config.numBins + bin;\n\n\tatomicMin(&bins[binKey].firstIdx, idx);\n\tatomicMax(&bins[binKey].lastIdx, idx);\n\n\tlet ySortable = sortableFromBits(yb);\n\tatomicMin(&bins[binKey].minYSortable, ySortable);\n\tatomicMax(&bins[binKey].maxYSortable, ySortable);\n}\n";
 /**
  * Pass 2: Find indices of min/max Y points.
  * Each thread re-checks if its Y value matches the bin's min/max.
@@ -67,7 +73,7 @@ declare const BIN_POINTS_SHADER = "\nrequires immediate_address_space;\n\nstruct
  * Group 1: controlLayout (control — only reads shouldDecimate)
  * Immediates: the x scale (ScaleParam)
  */
-declare const FIND_MINMAX_SHADER = "\nrequires immediate_address_space;\n\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\nstruct M4Bin {\n\tfirstIdx: atomic<u32>,\n\tlastIdx: atomic<u32>,\n\tminYSortable: atomic<u32>,\n\tmaxYSortable: atomic<u32>,\n\tminYIdx: atomic<u32>,\n\tmaxYIdx: atomic<u32>,\n};\n\nfn floatToSortableUint(f: f32) -> u32 {\n\tlet bits = bitcast<u32>(f);\n\treturn select(~bits, bits ^ 0x80000000u, (bits & 0x80000000u) == 0u);\n}\n\n\nstruct ScaleParam {\n\tp1: f32,\n\tp2: f32,\n\tp3: f32,\n\tp4: f32,\n};\n\nvar<immediate> xScale: ScaleParam;\n\n\n@group(0) @binding(0) var<storage, read> xValues: array<f32>;\n@group(0) @binding(1) var<storage, read> yValues: array<f32>;\n@group(0) @binding(2) var<storage, read> seriesValues: array<f32>;\n@group(0) @binding(4) var<uniform> config: M4Config;\n@group(0) @binding(5) var<storage, read_write> bins: array<M4Bin>;\n@group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\tif (atomicLoad(&control[4]) == 0u) { return; }\n\n\tlet idx = gid.x;\n\tif (idx >= config.pointCount) { return; }\n\n\tlet x = xValues[idx];\n\tlet y = yValues[idx];\n\n\tif (x != x || y != y) { return; }\n\n\tlet domainMin = xScale.p1;\n\tlet domainMax = xScale.p2;\n\n\tlet t = (x - domainMin) / (domainMax - domainMin);\n\n\t// Series: 0-indexed (matches binPoints pass)\n\tlet seriesF = seriesValues[idx];\n\tif (seriesF < 0.0 || seriesF != seriesF) { return; }\n\tlet series = u32(seriesF);\n\tif (series >= config.numSeries) { return; }\n\n\t// Boundary bin clamping (matches binPoints pass)\n\tvar bin: u32;\n\tif (t < 0.0) {\n\t\tbin = 0u;\n\t} else if (t > 1.0) {\n\t\tbin = config.numBins - 1u;\n\t} else {\n\t\tlet innerBins = config.numBins - 2u;\n\t\tbin = 1u + min(u32(floor(t * f32(innerBins))), innerBins - 1u);\n\t}\n\tlet binKey = series * config.numBins + bin;\n\n\tlet ySortable = floatToSortableUint(y);\n\n\tif (ySortable == atomicLoad(&bins[binKey].minYSortable)) {\n\t\tatomicMin(&bins[binKey].minYIdx, idx);\n\t}\n\tif (ySortable == atomicLoad(&bins[binKey].maxYSortable)) {\n\t\tatomicMin(&bins[binKey].maxYIdx, idx);\n\t}\n}\n";
+declare const FIND_MINMAX_SHADER = "\nrequires immediate_address_space;\n\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\nstruct M4Bin {\n\tfirstIdx: atomic<u32>,\n\tlastIdx: atomic<u32>,\n\tminYSortable: atomic<u32>,\n\tmaxYSortable: atomic<u32>,\n\tminYIdx: atomic<u32>,\n\tmaxYIdx: atomic<u32>,\n};\n\nfn sortableFromBits(bits: u32) -> u32 {\n\treturn select(~bits, bits ^ 0x80000000u, (bits & 0x80000000u) == 0u);\n}\n\n\nconst NAN_BITS: u32 = 0x7FC00000u;\n\nfn isNanBits(u: u32) -> bool {\n\treturn (u & 0x7fffffffu) > 0x7f800000u;\n}\n\nfn isNaN(v: f32) -> bool {\n\treturn isNanBits(bitcast<u32>(v));\n}\n\n\n\nstruct ScaleParam {\n\tp1: f32,\n\tp2: f32,\n\tp3: f32,\n\tp4: f32,\n};\n\nvar<immediate> xScale: ScaleParam;\n\n\n@group(0) @binding(0) var<storage, read> xBits: array<u32>;\n@group(0) @binding(1) var<storage, read> yBits: array<u32>;\n@group(0) @binding(2) var<storage, read> seriesBits: array<u32>;\n@group(0) @binding(4) var<uniform> config: M4Config;\n@group(0) @binding(5) var<storage, read_write> bins: array<M4Bin>;\n@group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\tif (atomicLoad(&control[4]) == 0u) { return; }\n\n\tlet idx = gid.x;\n\tif (idx >= config.pointCount) { return; }\n\n\t// NaN skip on the bits (matches binPoints pass)\n\tlet xb = xBits[idx];\n\tlet yb = yBits[idx];\n\tif (isNanBits(xb) || isNanBits(yb)) { return; }\n\tlet x = bitcast<f32>(xb);\n\n\tlet domainMin = xScale.p1;\n\tlet domainMax = xScale.p2;\n\n\tlet t = (x - domainMin) / (domainMax - domainMin);\n\n\t// Series: 0-indexed (matches binPoints pass)\n\tlet seriesB = seriesBits[idx];\n\tif (isNanBits(seriesB)) { return; }\n\tlet seriesF = bitcast<f32>(seriesB);\n\tif (seriesF < 0.0) { return; }\n\tlet series = u32(seriesF);\n\tif (series >= config.numSeries) { return; }\n\n\t// Boundary bin clamping (matches binPoints pass)\n\tvar bin: u32;\n\tif (t < 0.0) {\n\t\tbin = 0u;\n\t} else if (t > 1.0) {\n\t\tbin = config.numBins - 1u;\n\t} else {\n\t\tlet innerBins = config.numBins - 2u;\n\t\tbin = 1u + min(u32(floor(t * f32(innerBins))), innerBins - 1u);\n\t}\n\tlet binKey = series * config.numBins + bin;\n\n\tlet ySortable = sortableFromBits(yb);\n\n\tif (ySortable == atomicLoad(&bins[binKey].minYSortable)) {\n\t\tatomicMin(&bins[binKey].minYIdx, idx);\n\t}\n\tif (ySortable == atomicLoad(&bins[binKey].maxYSortable)) {\n\t\tatomicMin(&bins[binKey].maxYIdx, idx);\n\t}\n}\n";
 /**
  * Pass 3: Emit decimated output arrays.
  * Each thread processes one bin, collecting up to 4 unique indices
@@ -82,7 +88,7 @@ declare const FIND_MINMAX_SHADER = "\nrequires immediate_address_space;\n\nstruc
  * Group 0: emitInputLayout (x, y, color, config, bins)
  * Group 1: outputLayout (xOut, yOut, seriesOut, colorOut)
  */
-declare const EMIT_OUTPUT_SHADER = "\n\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\nstruct M4Bin {\n\tfirstIdx: atomic<u32>,\n\tlastIdx: atomic<u32>,\n\tminYSortable: atomic<u32>,\n\tmaxYSortable: atomic<u32>,\n\tminYIdx: atomic<u32>,\n\tmaxYIdx: atomic<u32>,\n};\n\nfn floatToSortableUint(f: f32) -> u32 {\n\tlet bits = bitcast<u32>(f);\n\treturn select(~bits, bits ^ 0x80000000u, (bits & 0x80000000u) == 0u);\n}\n\n\n// Note: seriesValues not bound here \u2014 series is derived from binKey / numBins.\n// This keeps total storage buffers within WebGPU default limit.\n@group(0) @binding(0) var<storage, read> xValues: array<f32>;\n@group(0) @binding(1) var<storage, read> yValues: array<f32>;\n@group(0) @binding(2) var<storage, read> colorValues: array<f32>;\n@group(0) @binding(3) var<uniform> config: M4Config;\n@group(0) @binding(4) var<storage, read_write> bins: array<M4Bin>;\n@group(1) @binding(0) var<storage, read_write> xOut: array<f32>;\n@group(1) @binding(1) var<storage, read_write> yOut: array<f32>;\n@group(1) @binding(2) var<storage, read_write> seriesOut: array<f32>;\n@group(1) @binding(3) var<storage, read_write> colorOut: array<f32>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\tlet binKey = gid.x;\n\tlet totalBins = config.numSeries * config.numBins;\n\tif (binKey >= totalBins) { return; }\n\n\tlet outBase = binKey * 4u;\n\tlet firstIdx = atomicLoad(&bins[binKey].firstIdx);\n\n\t// Empty bin: write NaN to all 4 output slots\n\t// Use var to avoid const-expression NaN (WGSL disallows NaN in const context)\n\tif (firstIdx == 0xFFFFFFFFu) {\n\t\tvar nanBits = 0x7FC00000u;\n\t\tlet nan = bitcast<f32>(nanBits);\n\t\tfor (var i = 0u; i < 4u; i++) {\n\t\t\txOut[outBase + i] = nan;\n\t\t\tyOut[outBase + i] = nan;\n\t\t\tseriesOut[outBase + i] = nan;\n\t\t\tcolorOut[outBase + i] = nan;\n\t\t}\n\t\treturn;\n\t}\n\n\tlet lastIdx = atomicLoad(&bins[binKey].lastIdx);\n\tlet minYIdx = atomicLoad(&bins[binKey].minYIdx);\n\tlet maxYIdx = atomicLoad(&bins[binKey].maxYIdx);\n\n\t// Collect up to 4 unique indices, sorted by original index (= x-order)\n\tvar indices: array<u32, 4>;\n\tvar count = 0u;\n\n\t// Insert in sorted order, skip duplicates\n\tvar candidates = array<u32, 4>(firstIdx, lastIdx, minYIdx, maxYIdx);\n\n\t// Simple insertion sort for up to 4 candidates\n\tfor (var c = 0u; c < 4u; c++) {\n\t\tlet candidate = candidates[c];\n\t\t// Check if already present\n\t\tvar isDuplicate = false;\n\t\tfor (var k = 0u; k < count; k++) {\n\t\t\tif (indices[k] == candidate) {\n\t\t\t\tisDuplicate = true;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (isDuplicate) { continue; }\n\n\t\t// Insert in sorted position\n\t\tvar insertPos = count;\n\t\tfor (var k = 0u; k < count; k++) {\n\t\t\tif (candidate < indices[k]) {\n\t\t\t\tinsertPos = k;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t// Shift elements right\n\t\tfor (var k = count; k > insertPos; k--) {\n\t\t\tindices[k] = indices[k - 1u];\n\t\t}\n\t\tindices[insertPos] = candidate;\n\t\tcount++;\n\t}\n\n\t// Derive series value from bin key (0-indexed, matching ViewManager convention).\n\t// Vertex shader uses != comparison for series breaks, so any distinct values work.\n\tlet seriesVal = f32(binKey / config.numBins);\n\n\t// Write unique points, fill remaining slots with last unique point\n\tfor (var i = 0u; i < 4u; i++) {\n\t\tlet srcIdx = indices[min(i, count - 1u)];\n\t\txOut[outBase + i] = xValues[srcIdx];\n\t\tyOut[outBase + i] = yValues[srcIdx];\n\t\tseriesOut[outBase + i] = seriesVal;\n\t\tcolorOut[outBase + i] = colorValues[srcIdx];\n\t}\n}\n";
+declare const EMIT_OUTPUT_SHADER = "\n\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\nstruct M4Bin {\n\tfirstIdx: atomic<u32>,\n\tlastIdx: atomic<u32>,\n\tminYSortable: atomic<u32>,\n\tmaxYSortable: atomic<u32>,\n\tminYIdx: atomic<u32>,\n\tmaxYIdx: atomic<u32>,\n};\n\nfn sortableFromBits(bits: u32) -> u32 {\n\treturn select(~bits, bits ^ 0x80000000u, (bits & 0x80000000u) == 0u);\n}\n\n\nconst NAN_BITS: u32 = 0x7FC00000u;\n\nfn isNanBits(u: u32) -> bool {\n\treturn (u & 0x7fffffffu) > 0x7f800000u;\n}\n\nfn isNaN(v: f32) -> bool {\n\treturn isNanBits(bitcast<u32>(v));\n}\n\n\n\n// Note: seriesValues not bound here \u2014 series is derived from binKey / numBins.\n// This keeps total storage buffers within WebGPU default limit.\n@group(0) @binding(0) var<storage, read> xBits: array<u32>;\n@group(0) @binding(1) var<storage, read> yBits: array<u32>;\n@group(0) @binding(2) var<storage, read> colorBits: array<u32>;\n@group(0) @binding(3) var<uniform> config: M4Config;\n@group(0) @binding(4) var<storage, read_write> bins: array<M4Bin>;\n@group(1) @binding(0) var<storage, read_write> xOut: array<u32>;\n@group(1) @binding(1) var<storage, read_write> yOut: array<u32>;\n@group(1) @binding(2) var<storage, read_write> seriesOut: array<u32>;\n@group(1) @binding(3) var<storage, read_write> colorOut: array<u32>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\tlet binKey = gid.x;\n\tlet totalBins = config.numSeries * config.numBins;\n\tif (binKey >= totalBins) { return; }\n\n\tlet outBase = binKey * 4u;\n\tlet firstIdx = atomicLoad(&bins[binKey].firstIdx);\n\n\t// Empty bin: NaN in all 4 output slots, written as bits\n\tif (firstIdx == 0xFFFFFFFFu) {\n\t\tfor (var i = 0u; i < 4u; i++) {\n\t\t\txOut[outBase + i] = NAN_BITS;\n\t\t\tyOut[outBase + i] = NAN_BITS;\n\t\t\tseriesOut[outBase + i] = NAN_BITS;\n\t\t\tcolorOut[outBase + i] = NAN_BITS;\n\t\t}\n\t\treturn;\n\t}\n\n\tlet lastIdx = atomicLoad(&bins[binKey].lastIdx);\n\tlet minYIdx = atomicLoad(&bins[binKey].minYIdx);\n\tlet maxYIdx = atomicLoad(&bins[binKey].maxYIdx);\n\n\t// Collect up to 4 unique indices, sorted by original index (= x-order)\n\tvar indices: array<u32, 4>;\n\tvar count = 0u;\n\n\t// Insert in sorted order, skip duplicates\n\tvar candidates = array<u32, 4>(firstIdx, lastIdx, minYIdx, maxYIdx);\n\n\t// Simple insertion sort for up to 4 candidates\n\tfor (var c = 0u; c < 4u; c++) {\n\t\tlet candidate = candidates[c];\n\t\t// Check if already present\n\t\tvar isDuplicate = false;\n\t\tfor (var k = 0u; k < count; k++) {\n\t\t\tif (indices[k] == candidate) {\n\t\t\t\tisDuplicate = true;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (isDuplicate) { continue; }\n\n\t\t// Insert in sorted position\n\t\tvar insertPos = count;\n\t\tfor (var k = 0u; k < count; k++) {\n\t\t\tif (candidate < indices[k]) {\n\t\t\t\tinsertPos = k;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t// Shift elements right\n\t\tfor (var k = count; k > insertPos; k--) {\n\t\t\tindices[k] = indices[k - 1u];\n\t\t}\n\t\tindices[insertPos] = candidate;\n\t\tcount++;\n\t}\n\n\t// Derive series value from bin key (0-indexed, matching ViewManager convention).\n\t// Vertex shader uses != comparison for series breaks, so any distinct values work.\n\tlet seriesVal = bitcast<u32>(f32(binKey / config.numBins));\n\n\t// Write unique points, fill remaining slots with last unique point.\n\t// Copied as bits, so a value arrives exactly as it left.\n\tfor (var i = 0u; i < 4u; i++) {\n\t\tlet srcIdx = indices[min(i, count - 1u)];\n\t\txOut[outBase + i] = xBits[srcIdx];\n\t\tyOut[outBase + i] = yBits[srcIdx];\n\t\tseriesOut[outBase + i] = seriesVal;\n\t\tcolorOut[outBase + i] = colorBits[srcIdx];\n\t}\n}\n";
 /**
  * Pass 4: Compact non-NaN output points and deduplicate.
  * After the emit pass, empty bins contain NaN. This pass packs real data
@@ -100,7 +106,7 @@ declare const EMIT_OUTPUT_SHADER = "\n\nstruct M4Config {\n\tpointCount: u32,\n\
  * Group 0: fillLayout (config + output arrays)
  * Group 1: controlLayout (control)
  */
-declare const COMPACT_SHADER = "\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\n@group(0) @binding(0) var<uniform> config: M4Config;\n@group(0) @binding(1) var<storage, read_write> xOut: array<f32>;\n@group(0) @binding(2) var<storage, read_write> yOut: array<f32>;\n@group(0) @binding(3) var<storage, read_write> seriesOut: array<f32>;\n@group(0) @binding(4) var<storage, read_write> colorOut: array<f32>;\n@group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;\n\n@compute @workgroup_size(1)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\tif (atomicLoad(&control[4]) == 0u) { return; }\n\n\tlet series = gid.x;\n\tif (series >= config.numSeries) { return; }\n\n\tlet start = series * 4u * config.numBins;\n\tlet end = start + 4u * config.numBins;\n\n\t// Pack non-NaN points to the front, skipping consecutive duplicates.\n\tvar writeIdx = start;\n\tvar nanBits = 0x7FC00000u;\n\tvar lastX: f32 = bitcast<f32>(nanBits);\n\tvar lastY: f32 = bitcast<f32>(nanBits);\n\n\tfor (var i = start; i < end; i++) {\n\t\tlet x = xOut[i];\n\t\tif (x != x) { continue; }\n\t\tlet y = yOut[i];\n\t\tif (x == lastX && y == lastY) { continue; }\n\n\t\tif (writeIdx != i) {\n\t\t\txOut[writeIdx] = x;\n\t\t\tyOut[writeIdx] = y;\n\t\t\tseriesOut[writeIdx] = seriesOut[i];\n\t\t\tcolorOut[writeIdx] = colorOut[i];\n\t\t}\n\t\tlastX = x;\n\t\tlastY = y;\n\t\twriteIdx++;\n\t}\n\n\t// NaN-pad remaining slots\n\tlet nan = bitcast<f32>(nanBits);\n\tfor (var i = writeIdx; i < end; i++) {\n\t\txOut[i] = nan;\n\t\tyOut[i] = nan;\n\t\tseriesOut[i] = nan;\n\t\tcolorOut[i] = nan;\n\t}\n\n\t// Instance count is set by pass 0 (outputSize) \u2014 compact only reorganizes\n\t// data within each series block, it doesn't change the total count.\n\t// The vertex shader discards NaN-padded entries at the end of each block.\n}\n";
+declare const COMPACT_SHADER = "\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\n\nconst NAN_BITS: u32 = 0x7FC00000u;\n\nfn isNanBits(u: u32) -> bool {\n\treturn (u & 0x7fffffffu) > 0x7f800000u;\n}\n\nfn isNaN(v: f32) -> bool {\n\treturn isNanBits(bitcast<u32>(v));\n}\n\n\n@group(0) @binding(0) var<uniform> config: M4Config;\n@group(0) @binding(1) var<storage, read_write> xOut: array<u32>;\n@group(0) @binding(2) var<storage, read_write> yOut: array<u32>;\n@group(0) @binding(3) var<storage, read_write> seriesOut: array<u32>;\n@group(0) @binding(4) var<storage, read_write> colorOut: array<u32>;\n@group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;\n\n@compute @workgroup_size(1)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\tif (atomicLoad(&control[4]) == 0u) { return; }\n\n\tlet series = gid.x;\n\tif (series >= config.numSeries) { return; }\n\n\tlet start = series * 4u * config.numBins;\n\tlet end = start + 4u * config.numBins;\n\n\t// Pack non-NaN points to the front, skipping consecutive duplicates.\n\t// All on bits: NaN by its pattern, duplicates by identical bits. lastX\n\t// starts as NaN, which no kept x can equal.\n\tvar writeIdx = start;\n\tvar lastX = NAN_BITS;\n\tvar lastY = NAN_BITS;\n\n\tfor (var i = start; i < end; i++) {\n\t\tlet x = xOut[i];\n\t\tif (isNanBits(x)) { continue; }\n\t\tlet y = yOut[i];\n\t\tif (x == lastX && y == lastY) { continue; }\n\n\t\tif (writeIdx != i) {\n\t\t\txOut[writeIdx] = x;\n\t\t\tyOut[writeIdx] = y;\n\t\t\tseriesOut[writeIdx] = seriesOut[i];\n\t\t\tcolorOut[writeIdx] = colorOut[i];\n\t\t}\n\t\tlastX = x;\n\t\tlastY = y;\n\t\twriteIdx++;\n\t}\n\n\t// NaN-pad remaining slots\n\tfor (var i = writeIdx; i < end; i++) {\n\t\txOut[i] = NAN_BITS;\n\t\tyOut[i] = NAN_BITS;\n\t\tseriesOut[i] = NAN_BITS;\n\t\tcolorOut[i] = NAN_BITS;\n\t}\n\n\t// Instance count is set by pass 0 (outputSize) \u2014 compact only reorganizes\n\t// data within each series block, it doesn't change the total count.\n\t// The vertex shader discards NaN-padded entries at the end of each block.\n}\n";
 /**
  * Pass 5a: Passthrough copy — raw x,y → output + set indirect count.
  *
@@ -113,7 +119,7 @@ declare const COMPACT_SHADER = "\nstruct M4Config {\n\tpointCount: u32,\n\tnumBi
  * Group 0: passthroughInputLayout (data0, data1, config, control)
  * Group 1: halfOutputLayout (out0, out1)
  */
-declare const PASSTHROUGH_XY_SHADER = "\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\n@group(0) @binding(0) var<storage, read> xIn: array<f32>;\n@group(0) @binding(1) var<storage, read> yIn: array<f32>;\n@group(0) @binding(2) var<uniform> config: M4Config;\n@group(0) @binding(3) var<storage, read_write> control: array<atomic<u32>>;\n@group(1) @binding(0) var<storage, read_write> xOut: array<f32>;\n@group(1) @binding(1) var<storage, read_write> yOut: array<f32>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\t// Only run in passthrough mode\n\tif (atomicLoad(&control[4]) == 1u) { return; }\n\n\tlet idx = gid.x;\n\n\t// Thread 0 sets instance count to raw point count\n\tif (idx == 0u) {\n\t\tatomicStore(&control[1], config.pointCount);\n\t}\n\n\tif (idx >= config.pointCount) { return; }\n\n\txOut[idx] = xIn[idx];\n\tyOut[idx] = yIn[idx];\n}\n";
+declare const PASSTHROUGH_XY_SHADER = "\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\n// Copied as bits, so a null's NaN arrives exactly as it left.\n@group(0) @binding(0) var<storage, read> xIn: array<u32>;\n@group(0) @binding(1) var<storage, read> yIn: array<u32>;\n@group(0) @binding(2) var<uniform> config: M4Config;\n@group(0) @binding(3) var<storage, read_write> control: array<atomic<u32>>;\n@group(1) @binding(0) var<storage, read_write> xOut: array<u32>;\n@group(1) @binding(1) var<storage, read_write> yOut: array<u32>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\t// Only run in passthrough mode\n\tif (atomicLoad(&control[4]) == 1u) { return; }\n\n\tlet idx = gid.x;\n\n\t// Thread 0 sets instance count to raw point count\n\tif (idx == 0u) {\n\t\tatomicStore(&control[1], config.pointCount);\n\t}\n\n\tif (idx >= config.pointCount) { return; }\n\n\txOut[idx] = xIn[idx];\n\tyOut[idx] = yIn[idx];\n}\n";
 /**
  * Pass 5b: Passthrough copy — raw series,color → output.
  *
@@ -125,5 +131,5 @@ declare const PASSTHROUGH_XY_SHADER = "\nstruct M4Config {\n\tpointCount: u32,\n
  * Group 0: passthroughInputLayout (data0, data1, config, control)
  * Group 1: halfOutputLayout (out0, out1)
  */
-declare const PASSTHROUGH_SC_SHADER = "\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\n@group(0) @binding(0) var<storage, read> seriesIn: array<f32>;\n@group(0) @binding(1) var<storage, read> colorIn: array<f32>;\n@group(0) @binding(2) var<uniform> config: M4Config;\n@group(0) @binding(3) var<storage, read_write> control: array<atomic<u32>>;\n@group(1) @binding(0) var<storage, read_write> seriesOut: array<f32>;\n@group(1) @binding(1) var<storage, read_write> colorOut: array<f32>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\t// Only run in passthrough mode\n\tif (atomicLoad(&control[4]) == 1u) { return; }\n\n\tlet idx = gid.x;\n\tif (idx >= config.pointCount) { return; }\n\n\tseriesOut[idx] = seriesIn[idx];\n\tcolorOut[idx] = colorIn[idx];\n}\n";
+declare const PASSTHROUGH_SC_SHADER = "\nstruct M4Config {\n\tpointCount: u32,\n\tnumBins: u32,\n\tnumSeries: u32,\n\t_reserved: u32,\n\t_reserved0: u32,\n\t_reserved1: u32,\n\t_reserved2: u32,\n\tdecimationMode: u32,\n};\n\n// Copied as bits, like pass 5a.\n@group(0) @binding(0) var<storage, read> seriesIn: array<u32>;\n@group(0) @binding(1) var<storage, read> colorIn: array<u32>;\n@group(0) @binding(2) var<uniform> config: M4Config;\n@group(0) @binding(3) var<storage, read_write> control: array<atomic<u32>>;\n@group(1) @binding(0) var<storage, read_write> seriesOut: array<u32>;\n@group(1) @binding(1) var<storage, read_write> colorOut: array<u32>;\n\n@compute @workgroup_size(256)\nfn main(@builtin(global_invocation_id) gid: vec3<u32>) {\n\t// Only run in passthrough mode\n\tif (atomicLoad(&control[4]) == 1u) { return; }\n\n\tlet idx = gid.x;\n\tif (idx >= config.pointCount) { return; }\n\n\tseriesOut[idx] = seriesIn[idx];\n\tcolorOut[idx] = colorIn[idx];\n}\n";
 export { WORKGROUP_SIZE, X_SCALE_IMMEDIATE_SIZE, INIT_BINS_SHADER, BIN_POINTS_SHADER, FIND_MINMAX_SHADER, EMIT_OUTPUT_SHADER, COMPACT_SHADER, PASSTHROUGH_XY_SHADER, PASSTHROUGH_SC_SHADER };

package/dist/gpu/decimation/M4Shader.js

@@ -27,7 +27,14 @@
  *
  * The x scale's params reach passes 1 and 2 as immediates, pushed before each
  * dispatch, rather than as an index into the global scale table.
+ *
+ * Every pass reads and writes the data through u32 views. NaN (a null, or an
+ * empty bin) is found by its bit pattern and moved as bits, never compared as
+ * a float: Metal compilers may fold `x != x` to false (see NanShaderLib), and
+ * where they do, compaction keeps the empty bins and the line loses every
+ * segment that touches one.
  */
+import { NAN_WGSL } from '../NanShaderLib';
 const WORKGROUP_SIZE = 256;
 /**
  * Shared type definitions used across all kernels.
@@ -53,10 +60,11 @@ struct M4Bin {
 	maxYIdx: atomic<u32>,
 };
 
-fn floatToSortableUint(f: f32) -> u32 {
-	let bits = bitcast<u32>(f);
+fn sortableFromBits(bits: u32) -> u32 {
 	return select(~bits, bits ^ 0x80000000u, (bits & 0x80000000u) == 0u);
 }
+
+${NAN_WGSL}
 `;
 /** Bytes of immediate data passes 1 and 2 read: one ScaleParam. */
 const X_SCALE_IMMEDIATE_SIZE = 16;
@@ -135,9 +143,9 @@ requires immediate_address_space;
 ${SHARED_TYPES}
 ${X_SCALE_IMMEDIATE}
 
-@group(0) @binding(0) var<storage, read> xValues: array<f32>;
-@group(0) @binding(1) var<storage, read> yValues: array<f32>;
-@group(0) @binding(2) var<storage, read> seriesValues: array<f32>;
+@group(0) @binding(0) var<storage, read> xBits: array<u32>;
+@group(0) @binding(1) var<storage, read> yBits: array<u32>;
+@group(0) @binding(2) var<storage, read> seriesBits: array<u32>;
 @group(0) @binding(4) var<uniform> config: M4Config;
 @group(0) @binding(5) var<storage, read_write> bins: array<M4Bin>;
 @group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;
@@ -150,11 +158,11 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
 	let idx = gid.x;
 	if (idx >= config.pointCount) { return; }
 
-	let x = xValues[idx];
-	let y = yValues[idx];
-
-	// Skip NaN points
-	if (x != x || y != y) { return; }
+	// Skip NaN points, tested on the bits before either becomes a float
+	let xb = xBits[idx];
+	let yb = yBits[idx];
+	if (isNanBits(xb) || isNanBits(yb)) { return; }
+	let x = bitcast<f32>(xb);
 
 	let domainMin = xScale.p1;
 	let domainMax = xScale.p2;
@@ -162,8 +170,10 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
 	let t = (x - domainMin) / (domainMax - domainMin);
 
 	// Series: 0-indexed from ViewManager (-1 = null/unknown, 0+ = categories)
-	let seriesF = seriesValues[idx];
-	if (seriesF < 0.0 || seriesF != seriesF) { return; }
+	let seriesB = seriesBits[idx];
+	if (isNanBits(seriesB)) { return; }
+	let seriesF = bitcast<f32>(seriesB);
+	if (seriesF < 0.0) { return; }
 	let series = u32(seriesF);
 	if (series >= config.numSeries) { return; }
 
@@ -183,7 +193,7 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
 	atomicMin(&bins[binKey].firstIdx, idx);
 	atomicMax(&bins[binKey].lastIdx, idx);
 
-	let ySortable = floatToSortableUint(y);
+	let ySortable = sortableFromBits(yb);
 	atomicMin(&bins[binKey].minYSortable, ySortable);
 	atomicMax(&bins[binKey].maxYSortable, ySortable);
 }
@@ -204,9 +214,9 @@ requires immediate_address_space;
 ${SHARED_TYPES}
 ${X_SCALE_IMMEDIATE}
 
-@group(0) @binding(0) var<storage, read> xValues: array<f32>;
-@group(0) @binding(1) var<storage, read> yValues: array<f32>;
-@group(0) @binding(2) var<storage, read> seriesValues: array<f32>;
+@group(0) @binding(0) var<storage, read> xBits: array<u32>;
+@group(0) @binding(1) var<storage, read> yBits: array<u32>;
+@group(0) @binding(2) var<storage, read> seriesBits: array<u32>;
 @group(0) @binding(4) var<uniform> config: M4Config;
 @group(0) @binding(5) var<storage, read_write> bins: array<M4Bin>;
 @group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;
@@ -218,10 +228,11 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
 	let idx = gid.x;
 	if (idx >= config.pointCount) { return; }
 
-	let x = xValues[idx];
-	let y = yValues[idx];
-
-	if (x != x || y != y) { return; }
+	// NaN skip on the bits (matches binPoints pass)
+	let xb = xBits[idx];
+	let yb = yBits[idx];
+	if (isNanBits(xb) || isNanBits(yb)) { return; }
+	let x = bitcast<f32>(xb);
 
 	let domainMin = xScale.p1;
 	let domainMax = xScale.p2;
@@ -229,8 +240,10 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
 	let t = (x - domainMin) / (domainMax - domainMin);
 
 	// Series: 0-indexed (matches binPoints pass)
-	let seriesF = seriesValues[idx];
-	if (seriesF < 0.0 || seriesF != seriesF) { return; }
+	let seriesB = seriesBits[idx];
+	if (isNanBits(seriesB)) { return; }
+	let seriesF = bitcast<f32>(seriesB);
+	if (seriesF < 0.0) { return; }
 	let series = u32(seriesF);
 	if (series >= config.numSeries) { return; }
 
@@ -246,7 +259,7 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
 	}
 	let binKey = series * config.numBins + bin;
 
-	let ySortable = floatToSortableUint(y);
+	let ySortable = sortableFromBits(yb);
 
 	if (ySortable == atomicLoad(&bins[binKey].minYSortable)) {
 		atomicMin(&bins[binKey].minYIdx, idx);
@@ -275,15 +288,15 @@ ${SHARED_TYPES}
 
 // Note: seriesValues not bound here — series is derived from binKey / numBins.
 // This keeps total storage buffers within WebGPU default limit.
-@group(0) @binding(0) var<storage, read> xValues: array<f32>;
-@group(0) @binding(1) var<storage, read> yValues: array<f32>;
-@group(0) @binding(2) var<storage, read> colorValues: array<f32>;
+@group(0) @binding(0) var<storage, read> xBits: array<u32>;
+@group(0) @binding(1) var<storage, read> yBits: array<u32>;
+@group(0) @binding(2) var<storage, read> colorBits: array<u32>;
 @group(0) @binding(3) var<uniform> config: M4Config;
 @group(0) @binding(4) var<storage, read_write> bins: array<M4Bin>;
-@group(1) @binding(0) var<storage, read_write> xOut: array<f32>;
-@group(1) @binding(1) var<storage, read_write> yOut: array<f32>;
-@group(1) @binding(2) var<storage, read_write> seriesOut: array<f32>;
-@group(1) @binding(3) var<storage, read_write> colorOut: array<f32>;
+@group(1) @binding(0) var<storage, read_write> xOut: array<u32>;
+@group(1) @binding(1) var<storage, read_write> yOut: array<u32>;
+@group(1) @binding(2) var<storage, read_write> seriesOut: array<u32>;
+@group(1) @binding(3) var<storage, read_write> colorOut: array<u32>;
 
 @compute @workgroup_size(${WORKGROUP_SIZE})
 fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
@@ -294,16 +307,13 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
 	let outBase = binKey * 4u;
 	let firstIdx = atomicLoad(&bins[binKey].firstIdx);
 
-	// Empty bin: write NaN to all 4 output slots
-	// Use var to avoid const-expression NaN (WGSL disallows NaN in const context)
+	// Empty bin: NaN in all 4 output slots, written as bits
 	if (firstIdx == 0xFFFFFFFFu) {
-		var nanBits = 0x7FC00000u;
-		let nan = bitcast<f32>(nanBits);
 		for (var i = 0u; i < 4u; i++) {
-			xOut[outBase + i] = nan;
-			yOut[outBase + i] = nan;
-			seriesOut[outBase + i] = nan;
-			colorOut[outBase + i] = nan;
+			xOut[outBase + i] = NAN_BITS;
+			yOut[outBase + i] = NAN_BITS;
+			seriesOut[outBase + i] = NAN_BITS;
+			colorOut[outBase + i] = NAN_BITS;
 		}
 		return;
 	}
@@ -350,15 +360,16 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
 
 	// Derive series value from bin key (0-indexed, matching ViewManager convention).
 	// Vertex shader uses != comparison for series breaks, so any distinct values work.
-	let seriesVal = f32(binKey / config.numBins);
+	let seriesVal = bitcast<u32>(f32(binKey / config.numBins));
 
-	// Write unique points, fill remaining slots with last unique point
+	// Write unique points, fill remaining slots with last unique point.
+	// Copied as bits, so a value arrives exactly as it left.
 	for (var i = 0u; i < 4u; i++) {
 		let srcIdx = indices[min(i, count - 1u)];
-		xOut[outBase + i] = xValues[srcIdx];
-		yOut[outBase + i] = yValues[srcIdx];
+		xOut[outBase + i] = xBits[srcIdx];
+		yOut[outBase + i] = yBits[srcIdx];
 		seriesOut[outBase + i] = seriesVal;
-		colorOut[outBase + i] = colorValues[srcIdx];
+		colorOut[outBase + i] = colorBits[srcIdx];
 	}
 }
 `;
@@ -391,11 +402,13 @@ struct M4Config {
 	decimationMode: u32,
 };
 
+${NAN_WGSL}
+
 @group(0) @binding(0) var<uniform> config: M4Config;
-@group(0) @binding(1) var<storage, read_write> xOut: array<f32>;
-@group(0) @binding(2) var<storage, read_write> yOut: array<f32>;
-@group(0) @binding(3) var<storage, read_write> seriesOut: array<f32>;
-@group(0) @binding(4) var<storage, read_write> colorOut: array<f32>;
+@group(0) @binding(1) var<storage, read_write> xOut: array<u32>;
+@group(0) @binding(2) var<storage, read_write> yOut: array<u32>;
+@group(0) @binding(3) var<storage, read_write> seriesOut: array<u32>;
+@group(0) @binding(4) var<storage, read_write> colorOut: array<u32>;
 @group(1) @binding(0) var<storage, read_write> control: array<atomic<u32>>;
 
 @compute @workgroup_size(1)
@@ -409,14 +422,15 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
 	let end = start + 4u * config.numBins;
 
 	// Pack non-NaN points to the front, skipping consecutive duplicates.
+	// All on bits: NaN by its pattern, duplicates by identical bits. lastX
+	// starts as NaN, which no kept x can equal.
 	var writeIdx = start;
-	var nanBits = 0x7FC00000u;
-	var lastX: f32 = bitcast<f32>(nanBits);
-	var lastY: f32 = bitcast<f32>(nanBits);
+	var lastX = NAN_BITS;
+	var lastY = NAN_BITS;
 
 	for (var i = start; i < end; i++) {
 		let x = xOut[i];
-		if (x != x) { continue; }
+		if (isNanBits(x)) { continue; }
 		let y = yOut[i];
 		if (x == lastX && y == lastY) { continue; }
 
@@ -432,12 +446,11 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
 	}
 
 	// NaN-pad remaining slots
-	let nan = bitcast<f32>(nanBits);
 	for (var i = writeIdx; i < end; i++) {
-		xOut[i] = nan;
-		yOut[i] = nan;
-		seriesOut[i] = nan;
-		colorOut[i] = nan;
+		xOut[i] = NAN_BITS;
+		yOut[i] = NAN_BITS;
+		seriesOut[i] = NAN_BITS;
+		colorOut[i] = NAN_BITS;
 	}
 
 	// Instance count is set by pass 0 (outputSize) — compact only reorganizes
@@ -469,12 +482,13 @@ struct M4Config {
 	decimationMode: u32,
 };
 
-@group(0) @binding(0) var<storage, read> xIn: array<f32>;
-@group(0) @binding(1) var<storage, read> yIn: array<f32>;
+// Copied as bits, so a null's NaN arrives exactly as it left.
+@group(0) @binding(0) var<storage, read> xIn: array<u32>;
+@group(0) @binding(1) var<storage, read> yIn: array<u32>;
 @group(0) @binding(2) var<uniform> config: M4Config;
 @group(0) @binding(3) var<storage, read_write> control: array<atomic<u32>>;
-@group(1) @binding(0) var<storage, read_write> xOut: array<f32>;
-@group(1) @binding(1) var<storage, read_write> yOut: array<f32>;
+@group(1) @binding(0) var<storage, read_write> xOut: array<u32>;
+@group(1) @binding(1) var<storage, read_write> yOut: array<u32>;
 
 @compute @workgroup_size(${WORKGROUP_SIZE})
 fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
@@ -517,12 +531,13 @@ struct M4Config {
 	decimationMode: u32,
 };
 
-@group(0) @binding(0) var<storage, read> seriesIn: array<f32>;
-@group(0) @binding(1) var<storage, read> colorIn: array<f32>;
+// Copied as bits, like pass 5a.
+@group(0) @binding(0) var<storage, read> seriesIn: array<u32>;
+@group(0) @binding(1) var<storage, read> colorIn: array<u32>;
 @group(0) @binding(2) var<uniform> config: M4Config;
 @group(0) @binding(3) var<storage, read_write> control: array<atomic<u32>>;
-@group(1) @binding(0) var<storage, read_write> seriesOut: array<f32>;
-@group(1) @binding(1) var<storage, read_write> colorOut: array<f32>;
+@group(1) @binding(0) var<storage, read_write> seriesOut: array<u32>;
+@group(1) @binding(1) var<storage, read_write> colorOut: array<u32>;
 
 @compute @workgroup_size(${WORKGROUP_SIZE})
 fn main(@builtin(global_invocation_id) gid: vec3<u32>) {

package/package.json

@@ -18,7 +18,7 @@
 		"type": "git",
 		"url": "git+https://github.com/dlyngman/fjader.git"
 	},
-	"version": "0.2.1",
+	"version": "0.2.2",
 	"type": "module",
 	"svelte": "./dist/index.js",
 	"exports": {