@enjoys/context-engine 1.4.1 → 1.4.2

package/data/completion/pla.json

@@ -1,155 +1,896 @@
-{
-  "language": "pla",
-  "completions": [
-    {
-      "label": "module",
-      "kind": 13,
-      "detail": "keyword module",
-      "documentation": {
-        "value": "module keyword"
-      },
-      "insertText": "module",
-      "sortText": "00_kw"
-    },
-    {
-      "label": "input",
-      "kind": 13,
-      "detail": "keyword input",
-      "documentation": {
-        "value": "input keyword"
-      },
-      "insertText": "input",
-      "sortText": "00_kw"
-    },
-    {
-      "label": "output",
-      "kind": 13,
-      "detail": "keyword output",
-      "documentation": {
-        "value": "output keyword"
-      },
-      "insertText": "output",
-      "sortText": "00_kw"
-    },
-    {
-      "label": "wire",
-      "kind": 13,
-      "detail": "keyword wire",
-      "documentation": {
-        "value": "wire keyword"
-      },
-      "insertText": "wire",
-      "sortText": "00_kw"
-    },
-    {
-      "label": "reg",
-      "kind": 13,
-      "detail": "keyword reg",
-      "documentation": {
-        "value": "reg keyword"
-      },
-      "insertText": "reg",
-      "sortText": "00_kw"
-    },
-    {
-      "label": "begin",
-      "kind": 13,
-      "detail": "keyword begin",
-      "documentation": {
-        "value": "begin keyword"
-      },
-      "insertText": "begin",
-      "sortText": "00_kw"
-    },
-    {
-      "label": "end",
-      "kind": 13,
-      "detail": "keyword end",
-      "documentation": {
-        "value": "end keyword"
-      },
-      "insertText": "end",
-      "sortText": "00_kw"
-    },
-    {
-      "label": "if",
-      "kind": 13,
-      "detail": "keyword if",
-      "documentation": {
-        "value": "if keyword"
-      },
-      "insertText": "if",
-      "sortText": "00_kw"
-    },
-    {
-      "label": "else",
-      "kind": 13,
-      "detail": "keyword else",
-      "documentation": {
-        "value": "else keyword"
-      },
-      "insertText": "else",
-      "sortText": "00_kw"
-    },
-    {
-      "label": "case",
-      "kind": 13,
-      "detail": "keyword case",
-      "documentation": {
-        "value": "case keyword"
-      },
-      "insertText": "case",
-      "sortText": "00_kw"
-    },
-    {
-      "label": "for",
-      "kind": 13,
-      "detail": "keyword for",
-      "documentation": {
-        "value": "for keyword"
-      },
-      "insertText": "for",
-      "sortText": "00_kw"
-    },
-    {
-      "label": "while",
-      "kind": 13,
-      "detail": "keyword while",
-      "documentation": {
-        "value": "while keyword"
-      },
-      "insertText": "while",
-      "sortText": "00_kw"
-    },
-    {
-      "label": "assign",
-      "kind": 13,
-      "detail": "keyword assign",
-      "documentation": {
-        "value": "assign keyword"
-      },
-      "insertText": "assign",
-      "sortText": "00_kw"
-    },
-    {
-      "label": "always",
-      "kind": 13,
-      "detail": "keyword always",
-      "documentation": {
-        "value": "always keyword"
-      },
-      "insertText": "always",
-      "sortText": "00_kw"
-    },
-    {
-      "label": "initial",
-      "kind": 13,
-      "detail": "keyword initial",
-      "documentation": {
-        "value": "initial keyword"
-      },
-      "insertText": "initial",
-      "sortText": "00_kw"
-    }
-  ]
+{
+  "language": "pla",
+  "completions": [
+    {
+      "label": "module",
+      "kind": 17,
+      "detail": "Keyword: module",
+      "documentation": {
+        "value": "Module declaration."
+      },
+      "insertText": "module",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "input",
+      "kind": 17,
+      "detail": "Keyword: input",
+      "documentation": {
+        "value": "Input port."
+      },
+      "insertText": "input",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "output",
+      "kind": 17,
+      "detail": "Keyword: output",
+      "documentation": {
+        "value": "Output port."
+      },
+      "insertText": "output",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "wire",
+      "kind": 17,
+      "detail": "Keyword: wire",
+      "documentation": {
+        "value": "Wire signal."
+      },
+      "insertText": "wire",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "reg",
+      "kind": 17,
+      "detail": "Keyword: reg",
+      "documentation": {
+        "value": "Register signal."
+      },
+      "insertText": "reg",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "begin",
+      "kind": 17,
+      "detail": "Keyword: begin",
+      "documentation": {
+        "value": "Begin block."
+      },
+      "insertText": "begin",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "end",
+      "kind": 17,
+      "detail": "Keyword: end",
+      "documentation": {
+        "value": "End block."
+      },
+      "insertText": "end",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "if",
+      "kind": 17,
+      "detail": "Keyword: if",
+      "documentation": {
+        "value": "Conditional if."
+      },
+      "insertText": "if",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "else",
+      "kind": 17,
+      "detail": "Keyword: else",
+      "documentation": {
+        "value": "Else branch."
+      },
+      "insertText": "else",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "case",
+      "kind": 17,
+      "detail": "Keyword: case",
+      "documentation": {
+        "value": "Case statement."
+      },
+      "insertText": "case",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "for",
+      "kind": 17,
+      "detail": "Keyword: for",
+      "documentation": {
+        "value": "For loop."
+      },
+      "insertText": "for",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "while",
+      "kind": 17,
+      "detail": "Keyword: while",
+      "documentation": {
+        "value": "While loop."
+      },
+      "insertText": "while",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "assign",
+      "kind": 17,
+      "detail": "Keyword: assign",
+      "documentation": {
+        "value": "Continuous assignment."
+      },
+      "insertText": "assign",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "always",
+      "kind": 17,
+      "detail": "Keyword: always",
+      "documentation": {
+        "value": "Always block."
+      },
+      "insertText": "always",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "initial",
+      "kind": 17,
+      "detail": "Keyword: initial",
+      "documentation": {
+        "value": "Initial block."
+      },
+      "insertText": "initial",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "endmodule",
+      "kind": 17,
+      "detail": "Keyword: endmodule",
+      "documentation": {
+        "value": "End module."
+      },
+      "insertText": "endmodule",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "endcase",
+      "kind": 17,
+      "detail": "Keyword: endcase",
+      "documentation": {
+        "value": "End case statement."
+      },
+      "insertText": "endcase",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "parameter",
+      "kind": 17,
+      "detail": "Keyword: parameter",
+      "documentation": {
+        "value": "Parameter constant."
+      },
+      "insertText": "parameter",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "localparam",
+      "kind": 17,
+      "detail": "Keyword: localparam",
+      "documentation": {
+        "value": "Local parameter."
+      },
+      "insertText": "localparam",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "integer",
+      "kind": 17,
+      "detail": "Keyword: integer",
+      "documentation": {
+        "value": "Integer variable."
+      },
+      "insertText": "integer",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "real",
+      "kind": 17,
+      "detail": "Keyword: real",
+      "documentation": {
+        "value": "Real number variable."
+      },
+      "insertText": "real",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "genvar",
+      "kind": 17,
+      "detail": "Keyword: genvar",
+      "documentation": {
+        "value": "Generate variable."
+      },
+      "insertText": "genvar",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "generate",
+      "kind": 17,
+      "detail": "Keyword: generate",
+      "documentation": {
+        "value": "Generate block."
+      },
+      "insertText": "generate",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "endgenerate",
+      "kind": 17,
+      "detail": "Keyword: endgenerate",
+      "documentation": {
+        "value": "End generate block."
+      },
+      "insertText": "endgenerate",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "task",
+      "kind": 17,
+      "detail": "Keyword: task",
+      "documentation": {
+        "value": "Task definition."
+      },
+      "insertText": "task",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "endtask",
+      "kind": 17,
+      "detail": "Keyword: endtask",
+      "documentation": {
+        "value": "End task."
+      },
+      "insertText": "endtask",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "function",
+      "kind": 17,
+      "detail": "Keyword: function",
+      "documentation": {
+        "value": "Function definition."
+      },
+      "insertText": "function",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "endfunction",
+      "kind": 17,
+      "detail": "Keyword: endfunction",
+      "documentation": {
+        "value": "End function."
+      },
+      "insertText": "endfunction",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "posedge",
+      "kind": 17,
+      "detail": "Keyword: posedge",
+      "documentation": {
+        "value": "Positive edge."
+      },
+      "insertText": "posedge",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "negedge",
+      "kind": 17,
+      "detail": "Keyword: negedge",
+      "documentation": {
+        "value": "Negative edge."
+      },
+      "insertText": "negedge",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "default",
+      "kind": 17,
+      "detail": "Keyword: default",
+      "documentation": {
+        "value": "Default case."
+      },
+      "insertText": "default",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "inout",
+      "kind": 17,
+      "detail": "Keyword: inout",
+      "documentation": {
+        "value": "Bidirectional port."
+      },
+      "insertText": "inout",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "supply0",
+      "kind": 17,
+      "detail": "Keyword: supply0",
+      "documentation": {
+        "value": "Logic 0 supply."
+      },
+      "insertText": "supply0",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "supply1",
+      "kind": 17,
+      "detail": "Keyword: supply1",
+      "documentation": {
+        "value": "Logic 1 supply."
+      },
+      "insertText": "supply1",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "tri",
+      "kind": 17,
+      "detail": "Keyword: tri",
+      "documentation": {
+        "value": "Tri-state wire."
+      },
+      "insertText": "tri",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "signed",
+      "kind": 17,
+      "detail": "Keyword: signed",
+      "documentation": {
+        "value": "Signed value."
+      },
+      "insertText": "signed",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "unsigned",
+      "kind": 17,
+      "detail": "Keyword: unsigned",
+      "documentation": {
+        "value": "Unsigned value."
+      },
+      "insertText": "unsigned",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "disable",
+      "kind": 17,
+      "detail": "Keyword: disable",
+      "documentation": {
+        "value": "Disable named block."
+      },
+      "insertText": "disable",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "forever",
+      "kind": 17,
+      "detail": "Keyword: forever",
+      "documentation": {
+        "value": "Forever loop."
+      },
+      "insertText": "forever",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "repeat",
+      "kind": 17,
+      "detail": "Keyword: repeat",
+      "documentation": {
+        "value": "Repeat loop."
+      },
+      "insertText": "repeat",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "wait",
+      "kind": 17,
+      "detail": "Keyword: wait",
+      "documentation": {
+        "value": "Wait for condition."
+      },
+      "insertText": "wait",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "event",
+      "kind": 17,
+      "detail": "Keyword: event",
+      "documentation": {
+        "value": "Event declaration."
+      },
+      "insertText": "event",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "specify",
+      "kind": 17,
+      "detail": "Keyword: specify",
+      "documentation": {
+        "value": "Specify timing block."
+      },
+      "insertText": "specify",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "endspecify",
+      "kind": 17,
+      "detail": "Keyword: endspecify",
+      "documentation": {
+        "value": "End specify block."
+      },
+      "insertText": "endspecify",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "defparam",
+      "kind": 17,
+      "detail": "Keyword: defparam",
+      "documentation": {
+        "value": "Define parameter override."
+      },
+      "insertText": "defparam",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    },
+    {
+      "label": "module def",
+      "kind": 28,
+      "detail": "Module definition",
+      "documentation": {
+        "value": "Define a new module."
+      },
+      "insertText": "module ${1:name}(\n    input ${2:clk},\n    input ${3:rst},\n    input [${4:7}:0] ${5:data_in},\n    output reg [${4:7}:0] ${6:data_out}\n);\n\n${7:// logic}\n\nendmodule",
+      "insertTextRules": 4,
+      "sortText": "02_mod"
+    },
+    {
+      "label": "always @posedge",
+      "kind": 28,
+      "detail": "Clocked always block",
+      "documentation": {
+        "value": "Synchronous always block."
+      },
+      "insertText": "always @(posedge ${1:clk} or posedge ${2:rst}) begin\n    if (${2:rst}) begin\n        ${3:// reset}\n    end else begin\n        ${4:// logic}\n    end\nend",
+      "insertTextRules": 4,
+      "sortText": "02_always"
+    },
+    {
+      "label": "always @*",
+      "kind": 28,
+      "detail": "Combinational always",
+      "documentation": {
+        "value": "Combinational logic always block."
+      },
+      "insertText": "always @(*) begin\n    ${1:// combinational logic}\nend",
+      "insertTextRules": 4,
+      "sortText": "02_always"
+    },
+    {
+      "label": "always_ff",
+      "kind": 28,
+      "detail": "Flip-flop always",
+      "documentation": {
+        "value": "SystemVerilog-style flip-flop."
+      },
+      "insertText": "always @(posedge ${1:clk}) begin\n    if (!${2:rst_n}) begin\n        ${3:q} <= ${4:0};\n    end else begin\n        ${3:q} <= ${5:d};\n    end\nend",
+      "insertTextRules": 4,
+      "sortText": "02_always"
+    },
+    {
+      "label": "if-else",
+      "kind": 28,
+      "detail": "If-else statement",
+      "documentation": {
+        "value": "Conditional if-else."
+      },
+      "insertText": "if (${1:condition}) begin\n    ${2:// true}\nend else begin\n    ${3:// false}\nend",
+      "insertTextRules": 4,
+      "sortText": "03_ctrl"
+    },
+    {
+      "label": "case statement",
+      "kind": 28,
+      "detail": "Case block",
+      "documentation": {
+        "value": "Case/switch statement."
+      },
+      "insertText": "case (${1:sel})\n    ${2:2'b00}: ${3:out} = ${4:a};\n    ${5:2'b01}: ${3:out} = ${6:b};\n    ${7:2'b10}: ${3:out} = ${8:c};\n    default: ${3:out} = ${9:0};\nendcase",
+      "insertTextRules": 4,
+      "sortText": "03_ctrl"
+    },
+    {
+      "label": "for loop",
+      "kind": 28,
+      "detail": "For loop",
+      "documentation": {
+        "value": "For loop construct."
+      },
+      "insertText": "for (${1:i} = ${2:0}; ${1:i} < ${3:8}; ${1:i} = ${1:i} + 1) begin\n    ${4:// body}\nend",
+      "insertTextRules": 4,
+      "sortText": "03_ctrl"
+    },
+    {
+      "label": "generate for",
+      "kind": 28,
+      "detail": "Generate for",
+      "documentation": {
+        "value": "Generate loop for replication."
+      },
+      "insertText": "genvar ${1:i};\ngenerate\n    for (${1:i} = 0; ${1:i} < ${2:8}; ${1:i} = ${1:i} + 1) begin : ${3:gen_block}\n        ${4:// instantiate}\n    end\nendgenerate",
+      "insertTextRules": 4,
+      "sortText": "03_gen"
+    },
+    {
+      "label": "assign stmt",
+      "kind": 28,
+      "detail": "Assign wire",
+      "documentation": {
+        "value": "Continuous wire assignment."
+      },
+      "insertText": "assign ${1:out} = ${2:a} ${3:&} ${4:b};",
+      "insertTextRules": 4,
+      "sortText": "02_assign"
+    },
+    {
+      "label": "parameter def",
+      "kind": 28,
+      "detail": "Parameter",
+      "documentation": {
+        "value": "Define a parameter."
+      },
+      "insertText": "parameter ${1:WIDTH} = ${2:8};",
+      "insertTextRules": 4,
+      "sortText": "02_param"
+    },
+    {
+      "label": "localparam def",
+      "kind": 28,
+      "detail": "Local parameter",
+      "documentation": {
+        "value": "Define a local parameter."
+      },
+      "insertText": "localparam ${1:DEPTH} = ${2:16};",
+      "insertTextRules": 4,
+      "sortText": "02_param"
+    },
+    {
+      "label": "reg declaration",
+      "kind": 28,
+      "detail": "Register",
+      "documentation": {
+        "value": "Declare a register."
+      },
+      "insertText": "reg [${1:7}:0] ${2:data};",
+      "insertTextRules": 4,
+      "sortText": "02_reg"
+    },
+    {
+      "label": "wire declaration",
+      "kind": 28,
+      "detail": "Wire",
+      "documentation": {
+        "value": "Declare a wire."
+      },
+      "insertText": "wire [${1:7}:0] ${2:data};",
+      "insertTextRules": 4,
+      "sortText": "02_wire"
+    },
+    {
+      "label": "input port",
+      "kind": 28,
+      "detail": "Input port",
+      "documentation": {
+        "value": "Declare input port."
+      },
+      "insertText": "input [${1:7}:0] ${2:data_in}",
+      "insertTextRules": 4,
+      "sortText": "02_port"
+    },
+    {
+      "label": "output port",
+      "kind": 28,
+      "detail": "Output port",
+      "documentation": {
+        "value": "Declare output port."
+      },
+      "insertText": "output [${1:7}:0] ${2:data_out}",
+      "insertTextRules": 4,
+      "sortText": "02_port"
+    },
+    {
+      "label": "output reg",
+      "kind": 28,
+      "detail": "Output register",
+      "documentation": {
+        "value": "Declare registered output."
+      },
+      "insertText": "output reg [${1:7}:0] ${2:data_out}",
+      "insertTextRules": 4,
+      "sortText": "02_port"
+    },
+    {
+      "label": "instantiate",
+      "kind": 28,
+      "detail": "Module instance",
+      "documentation": {
+        "value": "Instantiate a module."
+      },
+      "insertText": "${1:module_name} ${2:inst_name}(\n    .${3:port1}(${4:signal1}),\n    .${5:port2}(${6:signal2})\n);",
+      "insertTextRules": 4,
+      "sortText": "03_inst"
+    },
+    {
+      "label": "testbench",
+      "kind": 28,
+      "detail": "Testbench template",
+      "documentation": {
+        "value": "Basic testbench."
+      },
+      "insertText": "module ${1:tb};\n    reg ${2:clk}, ${3:rst};\n    wire [${4:7}:0] ${5:out};\n\n    ${6:dut} uut(\n        .clk(${2:clk}),\n        .rst(${3:rst}),\n        .out(${5:out})\n    );\n\n    initial begin\n        ${2:clk} = 0;\n        forever #${7:5} ${2:clk} = ~${2:clk};\n    end\n\n    initial begin\n        ${3:rst} = 1;\n        #${8:20} ${3:rst} = 0;\n        #${9:100} $$finish;\n    end\nendmodule",
+      "insertTextRules": 4,
+      "sortText": "04_tb"
+    },
+    {
+      "label": "clock gen",
+      "kind": 28,
+      "detail": "Clock generator",
+      "documentation": {
+        "value": "Clock generation."
+      },
+      "insertText": "initial begin\n    ${1:clk} = 0;\n    forever #${2:5} ${1:clk} = ~${1:clk};\nend",
+      "insertTextRules": 4,
+      "sortText": "04_tb"
+    },
+    {
+      "label": "task def",
+      "kind": 28,
+      "detail": "Task",
+      "documentation": {
+        "value": "Define a task."
+      },
+      "insertText": "task ${1:task_name};\n    input ${2:a};\n    output ${3:b};\n    begin\n        ${4:// body}\n    end\nendtask",
+      "insertTextRules": 4,
+      "sortText": "03_task"
+    },
+    {
+      "label": "function def",
+      "kind": 28,
+      "detail": "Function",
+      "documentation": {
+        "value": "Define a function."
+      },
+      "insertText": "function [${1:7}:0] ${2:func_name};\n    input [${1:7}:0] ${3:a};\n    begin\n        ${2:func_name} = ${4:a + 1};\n    end\nendfunction",
+      "insertTextRules": 4,
+      "sortText": "03_func"
+    },
+    {
+      "label": "mux 2:1",
+      "kind": 28,
+      "detail": "2:1 Multiplexer",
+      "documentation": {
+        "value": "2-to-1 multiplexer."
+      },
+      "insertText": "assign ${1:out} = ${2:sel} ? ${3:a} : ${4:b};",
+      "insertTextRules": 4,
+      "sortText": "05_comp"
+    },
+    {
+      "label": "mux 4:1",
+      "kind": 28,
+      "detail": "4:1 Multiplexer",
+      "documentation": {
+        "value": "4-to-1 multiplexer."
+      },
+      "insertText": "always @(*) begin\n    case (${1:sel})\n        2'b00: ${2:out} = ${3:a};\n        2'b01: ${2:out} = ${4:b};\n        2'b10: ${2:out} = ${5:c};\n        2'b11: ${2:out} = ${6:d};\n    endcase\nend",
+      "insertTextRules": 4,
+      "sortText": "05_comp"
+    },
+    {
+      "label": "decoder",
+      "kind": 28,
+      "detail": "Decoder",
+      "documentation": {
+        "value": "Binary decoder."
+      },
+      "insertText": "always @(*) begin\n    ${1:out} = ${2:4}'b0;\n    ${1:out}[${3:sel}] = 1'b1;\nend",
+      "insertTextRules": 4,
+      "sortText": "05_comp"
+    },
+    {
+      "label": "counter",
+      "kind": 28,
+      "detail": "Counter",
+      "documentation": {
+        "value": "Binary counter."
+      },
+      "insertText": "always @(posedge ${1:clk} or posedge ${2:rst}) begin\n    if (${2:rst})\n        ${3:count} <= 0;\n    else\n        ${3:count} <= ${3:count} + 1;\nend",
+      "insertTextRules": 4,
+      "sortText": "05_comp"
+    },
+    {
+      "label": "shift register",
+      "kind": 28,
+      "detail": "Shift register",
+      "documentation": {
+        "value": "Shift register."
+      },
+      "insertText": "always @(posedge ${1:clk}) begin\n    if (${2:rst})\n        ${3:shift_reg} <= 0;\n    else\n        ${3:shift_reg} <= {${3:shift_reg}[${4:6}:0], ${5:data_in}};\nend",
+      "insertTextRules": 4,
+      "sortText": "05_comp"
+    },
+    {
+      "label": "FSM",
+      "kind": 28,
+      "detail": "State machine",
+      "documentation": {
+        "value": "Finite state machine."
+      },
+      "insertText": "// State encoding\nlocalparam ${1:IDLE} = 2'b00, ${2:RUN} = 2'b01, ${3:DONE} = 2'b10;\nreg [1:0] state, next_state;\n\nalways @(posedge clk or posedge rst) begin\n    if (rst) state <= ${1:IDLE};\n    else state <= next_state;\nend\n\nalways @(*) begin\n    next_state = state;\n    case (state)\n        ${1:IDLE}: if (${4:start}) next_state = ${2:RUN};\n        ${2:RUN}: if (${5:done}) next_state = ${3:DONE};\n        ${3:DONE}: next_state = ${1:IDLE};\n    endcase\nend",
+      "insertTextRules": 4,
+      "sortText": "05_fsm"
+    },
+    {
+      "label": "memory",
+      "kind": 28,
+      "detail": "Memory array",
+      "documentation": {
+        "value": "RAM memory block."
+      },
+      "insertText": "reg [${1:7}:0] ${2:mem} [0:${3:255}];\n\nalways @(posedge ${4:clk}) begin\n    if (${5:we})\n        ${2:mem}[${6:addr}] <= ${7:data_in};\n    ${8:data_out} <= ${2:mem}[${6:addr}];\nend",
+      "insertTextRules": 4,
+      "sortText": "05_comp"
+    },
+    {
+      "label": "D flip-flop",
+      "kind": 28,
+      "detail": "D flip-flop",
+      "documentation": {
+        "value": "D flip-flop with reset."
+      },
+      "insertText": "always @(posedge ${1:clk} or posedge ${2:rst}) begin\n    if (${2:rst})\n        ${3:q} <= 1'b0;\n    else\n        ${3:q} <= ${4:d};\nend",
+      "insertTextRules": 4,
+      "sortText": "05_comp"
+    },
+    {
+      "label": "$display",
+      "kind": 28,
+      "detail": "Display",
+      "documentation": {
+        "value": "Display message in simulation."
+      },
+      "insertText": "$$display(\"${1:msg}: %d\", ${2:signal});",
+      "insertTextRules": 4,
+      "sortText": "04_sys"
+    },
+    {
+      "label": "$monitor",
+      "kind": 28,
+      "detail": "Monitor",
+      "documentation": {
+        "value": "Monitor signal changes."
+      },
+      "insertText": "$$monitor(\"${1:%t}: ${2:sig}=%b\", $$time, ${3:signal});",
+      "insertTextRules": 4,
+      "sortText": "04_sys"
+    },
+    {
+      "label": "$finish",
+      "kind": 28,
+      "detail": "Finish",
+      "documentation": {
+        "value": "End simulation."
+      },
+      "insertText": "$$finish;",
+      "insertTextRules": 4,
+      "sortText": "04_sys"
+    },
+    {
+      "label": "$dumpfile",
+      "kind": 28,
+      "detail": "Dump file",
+      "documentation": {
+        "value": "Set VCD dump file."
+      },
+      "insertText": "$$dumpfile(\"${1:dump.vcd}\");\n$$dumpvars(0, ${2:tb});",
+      "insertTextRules": 4,
+      "sortText": "04_sys"
+    },
+    {
+      "label": "#delay",
+      "kind": 28,
+      "detail": "Time delay",
+      "documentation": {
+        "value": "Simulation time delay."
+      },
+      "insertText": "#${1:10};",
+      "insertTextRules": 4,
+      "sortText": "04_sys"
+    },
+    {
+      "label": "adder",
+      "kind": 28,
+      "detail": "Full adder",
+      "documentation": {
+        "value": "Full adder module."
+      },
+      "insertText": "module full_adder(\n    input ${1:a}, ${2:b}, ${3:cin},\n    output ${4:sum}, ${5:cout}\n);\n    assign ${4:sum} = ${1:a} ^ ${2:b} ^ ${3:cin};\n    assign ${5:cout} = (${1:a} & ${2:b}) | (${3:cin} & (${1:a} ^ ${2:b}));\nendmodule",
+      "insertTextRules": 4,
+      "sortText": "05_comp"
+    },
+    {
+      "label": "timescale",
+      "kind": 17,
+      "detail": "Keyword: timescale",
+      "documentation": {
+        "value": "Timescale directive."
+      },
+      "insertText": "timescale",
+      "insertTextRules": 0,
+      "sortText": "00_kw"
+    }
+  ]
 }